1 =========================
2 Dynamic DMA mapping Guide
3 =========================
5 :Author: David S. Miller <davem@redhat.com>
6 :Author: Richard Henderson <rth@cygnus.com>
7 :Author: Jakub Jelinek <jakub@redhat.com>
9 This is a guide to device driver writers on how to use the DMA API
10 with example pseudo-code. For a concise description of the API, see
16 There are several kinds of addresses involved in the DMA API, and it's
17 important to understand the differences.
19 The kernel normally uses virtual addresses. Any address returned by
20 kmalloc(), vmalloc(), and similar interfaces is a virtual address and can
21 be stored in a ``void *``.
23 The virtual memory system (TLB, page tables, etc.) translates virtual
24 addresses to CPU physical addresses, which are stored as "phys_addr_t" or
25 "resource_size_t". The kernel manages device resources like registers as
26 physical addresses. These are the addresses in /proc/iomem. The physical
27 address is not directly useful to a driver; it must use ioremap() to map
28 the space and produce a virtual address.
30 I/O devices use a third kind of address: a "bus address". If a device has
31 registers at an MMIO address, or if it performs DMA to read or write system
32 memory, the addresses used by the device are bus addresses. In some
33 systems, bus addresses are identical to CPU physical addresses, but in
34 general they are not. IOMMUs and host bridges can produce arbitrary
35 mappings between physical and bus addresses.
37 From a device's point of view, DMA uses the bus address space, but it may
38 be restricted to a subset of that space. For example, even if a system
39 supports 64-bit addresses for main memory and PCI BARs, it may use an IOMMU
40 so devices only need to use 32-bit DMA addresses.
42 Here's a picture and some examples::
45 Virtual Physical Address
49 +-------+ +------+ +------+
50 | | |MMIO | Offset | |
51 | | Virtual |Space | applied | |
52 C +-------+ --------> B +------+ ----------> +------+ A
53 | | mapping | | by host | |
54 +-----+ | | | | bridge | | +--------+
55 | | | | +------+ | | | |
56 | CPU | | | | RAM | | | | Device |
58 +-----+ +-------+ +------+ +------+ +--------+
59 | | Virtual |Buffer| Mapping | |
60 X +-------+ --------> Y +------+ <---------- +------+ Z
61 | | mapping | RAM | by IOMMU
66 During the enumeration process, the kernel learns about I/O devices and
67 their MMIO space and the host bridges that connect them to the system. For
68 example, if a PCI device has a BAR, the kernel reads the bus address (A)
69 from the BAR and converts it to a CPU physical address (B). The address B
70 is stored in a struct resource and usually exposed via /proc/iomem. When a
71 driver claims a device, it typically uses ioremap() to map physical address
72 B at a virtual address (C). It can then use, e.g., ioread32(C), to access
73 the device registers at bus address A.
75 If the device supports DMA, the driver sets up a buffer using kmalloc() or
76 a similar interface, which returns a virtual address (X). The virtual
77 memory system maps X to a physical address (Y) in system RAM. The driver
78 can use virtual address X to access the buffer, but the device itself
79 cannot because DMA doesn't go through the CPU virtual memory system.
81 In some simple systems, the device can do DMA directly to physical address
82 Y. But in many others, there is IOMMU hardware that translates DMA
83 addresses to physical addresses, e.g., it translates Z to Y. This is part
84 of the reason for the DMA API: the driver can give a virtual address X to
85 an interface like dma_map_single(), which sets up any required IOMMU
86 mapping and returns the DMA address Z. The driver then tells the device to
87 do DMA to Z, and the IOMMU maps it to the buffer at address Y in system
90 So that Linux can use the dynamic DMA mapping, it needs some help from the
91 drivers, namely it has to take into account that DMA addresses should be
92 mapped only for the time they are actually used and unmapped after the DMA
95 The following API will work of course even on platforms where no such
98 Note that the DMA API works with any bus independent of the underlying
99 microprocessor architecture. You should use the DMA API rather than the
100 bus-specific DMA API, i.e., use the dma_map_*() interfaces rather than the
101 pci_map_*() interfaces.
103 First of all, you should make sure::
105 #include <linux/dma-mapping.h>
107 is in your driver, which provides the definition of dma_addr_t. This type
108 can hold any valid DMA address for the platform and should be used
109 everywhere you hold a DMA address returned from the DMA mapping functions.
111 What memory is DMA'able?
112 ========================
114 The first piece of information you must know is what kernel memory can
115 be used with the DMA mapping facilities. There has been an unwritten
116 set of rules regarding this, and this text is an attempt to finally
119 If you acquired your memory via the page allocator
120 (i.e. __get_free_page*()) or the generic memory allocators
121 (i.e. kmalloc() or kmem_cache_alloc()) then you may DMA to/from
122 that memory using the addresses returned from those routines.
124 This means specifically that you may _not_ use the memory/addresses
125 returned from vmalloc() for DMA. It is possible to DMA to the
126 _underlying_ memory mapped into a vmalloc() area, but this requires
127 walking page tables to get the physical addresses, and then
128 translating each of those pages back to a kernel address using
129 something like __va(). [ EDIT: Update this when we integrate
130 Gerd Knorr's generic code which does this. ]
132 This rule also means that you may use neither kernel image addresses
133 (items in data/text/bss segments), nor module image addresses, nor
134 stack addresses for DMA. These could all be mapped somewhere entirely
135 different than the rest of physical memory. Even if those classes of
136 memory could physically work with DMA, you'd need to ensure the I/O
137 buffers were cacheline-aligned. Without that, you'd see cacheline
138 sharing problems (data corruption) on CPUs with DMA-incoherent caches.
139 (The CPU could write to one word, DMA would write to a different one
140 in the same cache line, and one of them could be overwritten.)
142 Also, this means that you cannot take the return of a kmap()
143 call and DMA to/from that. This is similar to vmalloc().
145 What about block I/O and networking buffers? The block I/O and
146 networking subsystems make sure that the buffers they use are valid
147 for you to DMA from/to.
149 DMA addressing capabilities
150 ===========================
152 By default, the kernel assumes that your device can address 32-bits of DMA
153 addressing. For a 64-bit capable device, this needs to be increased, and for
154 a device with limitations, it needs to be decreased.
156 Special note about PCI: PCI-X specification requires PCI-X devices to support
157 64-bit addressing (DAC) for all transactions. And at least one platform (SGI
158 SN2) requires 64-bit consistent allocations to operate correctly when the IO
159 bus is in PCI-X mode.
161 For correct operation, you must set the DMA mask to inform the kernel about
162 your devices DMA addressing capabilities.
164 This is performed via a call to dma_set_mask_and_coherent()::
166 int dma_set_mask_and_coherent(struct device *dev, u64 mask);
168 which will set the mask for both streaming and coherent APIs together. If you
169 have some special requirements, then the following two separate calls can be
172 The setup for streaming mappings is performed via a call to
175 int dma_set_mask(struct device *dev, u64 mask);
177 The setup for consistent allocations is performed via a call
178 to dma_set_coherent_mask()::
180 int dma_set_coherent_mask(struct device *dev, u64 mask);
182 Here, dev is a pointer to the device struct of your device, and mask is a bit
183 mask describing which bits of an address your device supports. Often the
184 device struct of your device is embedded in the bus-specific device struct of
185 your device. For example, &pdev->dev is a pointer to the device struct of a
186 PCI device (pdev is a pointer to the PCI device struct of your device).
188 These calls usually return zero to indicated your device can perform DMA
189 properly on the machine given the address mask you provided, but they might
190 return an error if the mask is too small to be supportable on the given
191 system. If it returns non-zero, your device cannot perform DMA properly on
192 this platform, and attempting to do so will result in undefined behavior.
193 You must not use DMA on this device unless the dma_set_mask family of
194 functions has returned success.
196 This means that in the failure case, you have two options:
198 1) Use some non-DMA mode for data transfer, if possible.
199 2) Ignore this device and do not initialize it.
201 It is recommended that your driver print a kernel KERN_WARNING message when
202 setting the DMA mask fails. In this manner, if a user of your driver reports
203 that performance is bad or that the device is not even detected, you can ask
204 them for the kernel messages to find out exactly why.
206 The standard 64-bit addressing device would do something like this::
208 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64))) {
209 dev_warn(dev, "mydev: No suitable DMA available\n");
210 goto ignore_this_device;
213 If the device only supports 32-bit addressing for descriptors in the
214 coherent allocations, but supports full 64-bits for streaming mappings
215 it would look like this:
217 if (dma_set_mask(dev, DMA_BIT_MASK(64))) {
218 dev_warn(dev, "mydev: No suitable DMA available\n");
219 goto ignore_this_device;
222 The coherent mask will always be able to set the same or a smaller mask as
223 the streaming mask. However for the rare case that a device driver only
224 uses consistent allocations, one would have to check the return value from
225 dma_set_coherent_mask().
227 Finally, if your device can only drive the low 24-bits of
228 address you might do something like::
230 if (dma_set_mask(dev, DMA_BIT_MASK(24))) {
231 dev_warn(dev, "mydev: 24-bit DMA addressing not available\n");
232 goto ignore_this_device;
235 When dma_set_mask() or dma_set_mask_and_coherent() is successful, and
236 returns zero, the kernel saves away this mask you have provided. The
237 kernel will use this information later when you make DMA mappings.
239 There is a case which we are aware of at this time, which is worth
240 mentioning in this documentation. If your device supports multiple
241 functions (for example a sound card provides playback and record
242 functions) and the various different functions have _different_
243 DMA addressing limitations, you may wish to probe each mask and
244 only provide the functionality which the machine can handle. It
245 is important that the last call to dma_set_mask() be for the
248 Here is pseudo-code showing how this might be done::
250 #define PLAYBACK_ADDRESS_BITS DMA_BIT_MASK(32)
251 #define RECORD_ADDRESS_BITS DMA_BIT_MASK(24)
253 struct my_sound_card *card;
257 if (!dma_set_mask(dev, PLAYBACK_ADDRESS_BITS)) {
258 card->playback_enabled = 1;
260 card->playback_enabled = 0;
261 dev_warn(dev, "%s: Playback disabled due to DMA limitations\n",
264 if (!dma_set_mask(dev, RECORD_ADDRESS_BITS)) {
265 card->record_enabled = 1;
267 card->record_enabled = 0;
268 dev_warn(dev, "%s: Record disabled due to DMA limitations\n",
272 A sound card was used as an example here because this genre of PCI
273 devices seems to be littered with ISA chips given a PCI front end,
274 and thus retaining the 16MB DMA addressing limitations of ISA.
276 Types of DMA mappings
277 =====================
279 There are two types of DMA mappings:
281 - Consistent DMA mappings which are usually mapped at driver
282 initialization, unmapped at the end and for which the hardware should
283 guarantee that the device and the CPU can access the data
284 in parallel and will see updates made by each other without any
285 explicit software flushing.
287 Think of "consistent" as "synchronous" or "coherent".
289 The current default is to return consistent memory in the low 32
290 bits of the DMA space. However, for future compatibility you should
291 set the consistent mask even if this default is fine for your
294 Good examples of what to use consistent mappings for are:
296 - Network card DMA ring descriptors.
297 - SCSI adapter mailbox command data structures.
298 - Device firmware microcode executed out of
301 The invariant these examples all require is that any CPU store
302 to memory is immediately visible to the device, and vice
303 versa. Consistent mappings guarantee this.
307 Consistent DMA memory does not preclude the usage of
308 proper memory barriers. The CPU may reorder stores to
309 consistent memory just as it may normal memory. Example:
310 if it is important for the device to see the first word
311 of a descriptor updated before the second, you must do
314 desc->word0 = address;
316 desc->word1 = DESC_VALID;
318 in order to get correct behavior on all platforms.
320 Also, on some platforms your driver may need to flush CPU write
321 buffers in much the same way as it needs to flush write buffers
322 found in PCI bridges (such as by reading a register's value
325 - Streaming DMA mappings which are usually mapped for one DMA
326 transfer, unmapped right after it (unless you use dma_sync_* below)
327 and for which hardware can optimize for sequential accesses.
329 Think of "streaming" as "asynchronous" or "outside the coherency
332 Good examples of what to use streaming mappings for are:
334 - Networking buffers transmitted/received by a device.
335 - Filesystem buffers written/read by a SCSI device.
337 The interfaces for using this type of mapping were designed in
338 such a way that an implementation can make whatever performance
339 optimizations the hardware allows. To this end, when using
340 such mappings you must be explicit about what you want to happen.
342 Neither type of DMA mapping has alignment restrictions that come from
343 the underlying bus, although some devices may have such restrictions.
344 Also, systems with caches that aren't DMA-coherent will work better
345 when the underlying buffers don't share cache lines with other data.
348 Using Consistent DMA mappings
349 =============================
351 To allocate and map large (PAGE_SIZE or so) consistent DMA regions,
354 dma_addr_t dma_handle;
356 cpu_addr = dma_alloc_coherent(dev, size, &dma_handle, gfp);
358 where device is a ``struct device *``. This may be called in interrupt
359 context with the GFP_ATOMIC flag.
361 Size is the length of the region you want to allocate, in bytes.
363 This routine will allocate RAM for that region, so it acts similarly to
364 __get_free_pages() (but takes size instead of a page order). If your
365 driver needs regions sized smaller than a page, you may prefer using
366 the dma_pool interface, described below.
368 The consistent DMA mapping interfaces, for non-NULL dev, will by
369 default return a DMA address which is 32-bit addressable. Even if the
370 device indicates (via DMA mask) that it may address the upper 32-bits,
371 consistent allocation will only return > 32-bit addresses for DMA if
372 the consistent DMA mask has been explicitly changed via
373 dma_set_coherent_mask(). This is true of the dma_pool interface as
376 dma_alloc_coherent() returns two values: the virtual address which you
377 can use to access it from the CPU and dma_handle which you pass to the
380 The CPU virtual address and the DMA address are both
381 guaranteed to be aligned to the smallest PAGE_SIZE order which
382 is greater than or equal to the requested size. This invariant
383 exists (for example) to guarantee that if you allocate a chunk
384 which is smaller than or equal to 64 kilobytes, the extent of the
385 buffer you receive will not cross a 64K boundary.
387 To unmap and free such a DMA region, you call::
389 dma_free_coherent(dev, size, cpu_addr, dma_handle);
391 where dev, size are the same as in the above call and cpu_addr and
392 dma_handle are the values dma_alloc_coherent() returned to you.
393 This function may not be called in interrupt context.
395 If your driver needs lots of smaller memory regions, you can write
396 custom code to subdivide pages returned by dma_alloc_coherent(),
397 or you can use the dma_pool API to do that. A dma_pool is like
398 a kmem_cache, but it uses dma_alloc_coherent(), not __get_free_pages().
399 Also, it understands common hardware constraints for alignment,
400 like queue heads needing to be aligned on N byte boundaries.
402 Create a dma_pool like this::
404 struct dma_pool *pool;
406 pool = dma_pool_create(name, dev, size, align, boundary);
408 The "name" is for diagnostics (like a kmem_cache name); dev and size
409 are as above. The device's hardware alignment requirement for this
410 type of data is "align" (which is expressed in bytes, and must be a
411 power of two). If your device has no boundary crossing restrictions,
412 pass 0 for boundary; passing 4096 says memory allocated from this pool
413 must not cross 4KByte boundaries (but at that time it may be better to
414 use dma_alloc_coherent() directly instead).
416 Allocate memory from a DMA pool like this::
418 cpu_addr = dma_pool_alloc(pool, flags, &dma_handle);
420 flags are GFP_KERNEL if blocking is permitted (not in_interrupt nor
421 holding SMP locks), GFP_ATOMIC otherwise. Like dma_alloc_coherent(),
422 this returns two values, cpu_addr and dma_handle.
424 Free memory that was allocated from a dma_pool like this::
426 dma_pool_free(pool, cpu_addr, dma_handle);
428 where pool is what you passed to dma_pool_alloc(), and cpu_addr and
429 dma_handle are the values dma_pool_alloc() returned. This function
430 may be called in interrupt context.
432 Destroy a dma_pool by calling::
434 dma_pool_destroy(pool);
436 Make sure you've called dma_pool_free() for all memory allocated
437 from a pool before you destroy the pool. This function may not
438 be called in interrupt context.
443 The interfaces described in subsequent portions of this document
444 take a DMA direction argument, which is an integer and takes on
445 one of the following values::
452 You should provide the exact DMA direction if you know it.
454 DMA_TO_DEVICE means "from main memory to the device"
455 DMA_FROM_DEVICE means "from the device to main memory"
456 It is the direction in which the data moves during the DMA
459 You are _strongly_ encouraged to specify this as precisely
462 If you absolutely cannot know the direction of the DMA transfer,
463 specify DMA_BIDIRECTIONAL. It means that the DMA can go in
464 either direction. The platform guarantees that you may legally
465 specify this, and that it will work, but this may be at the
466 cost of performance for example.
468 The value DMA_NONE is to be used for debugging. One can
469 hold this in a data structure before you come to know the
470 precise direction, and this will help catch cases where your
471 direction tracking logic has failed to set things up properly.
473 Another advantage of specifying this value precisely (outside of
474 potential platform-specific optimizations of such) is for debugging.
475 Some platforms actually have a write permission boolean which DMA
476 mappings can be marked with, much like page protections in the user
477 program address space. Such platforms can and do report errors in the
478 kernel logs when the DMA controller hardware detects violation of the
481 Only streaming mappings specify a direction, consistent mappings
482 implicitly have a direction attribute setting of
485 The SCSI subsystem tells you the direction to use in the
486 'sc_data_direction' member of the SCSI command your driver is
489 For Networking drivers, it's a rather simple affair. For transmit
490 packets, map/unmap them with the DMA_TO_DEVICE direction
491 specifier. For receive packets, just the opposite, map/unmap them
492 with the DMA_FROM_DEVICE direction specifier.
494 Using Streaming DMA mappings
495 ============================
497 The streaming DMA mapping routines can be called from interrupt
498 context. There are two versions of each map/unmap, one which will
499 map/unmap a single memory region, and one which will map/unmap a
502 To map a single region, you do::
504 struct device *dev = &my_dev->dev;
505 dma_addr_t dma_handle;
506 void *addr = buffer->ptr;
507 size_t size = buffer->len;
509 dma_handle = dma_map_single(dev, addr, size, direction);
510 if (dma_mapping_error(dev, dma_handle)) {
512 * reduce current DMA mapping usage,
513 * delay and try again later or
516 goto map_error_handling;
521 dma_unmap_single(dev, dma_handle, size, direction);
523 You should call dma_mapping_error() as dma_map_single() could fail and return
524 error. Doing so will ensure that the mapping code will work correctly on all
525 DMA implementations without any dependency on the specifics of the underlying
526 implementation. Using the returned address without checking for errors could
527 result in failures ranging from panics to silent data corruption. The same
528 applies to dma_map_page() as well.
530 You should call dma_unmap_single() when the DMA activity is finished, e.g.,
531 from the interrupt which told you that the DMA transfer is done.
533 Using CPU pointers like this for single mappings has a disadvantage:
534 you cannot reference HIGHMEM memory in this way. Thus, there is a
535 map/unmap interface pair akin to dma_{map,unmap}_single(). These
536 interfaces deal with page/offset pairs instead of CPU pointers.
539 struct device *dev = &my_dev->dev;
540 dma_addr_t dma_handle;
541 struct page *page = buffer->page;
542 unsigned long offset = buffer->offset;
543 size_t size = buffer->len;
545 dma_handle = dma_map_page(dev, page, offset, size, direction);
546 if (dma_mapping_error(dev, dma_handle)) {
548 * reduce current DMA mapping usage,
549 * delay and try again later or
552 goto map_error_handling;
557 dma_unmap_page(dev, dma_handle, size, direction);
559 Here, "offset" means byte offset within the given page.
561 You should call dma_mapping_error() as dma_map_page() could fail and return
562 error as outlined under the dma_map_single() discussion.
564 You should call dma_unmap_page() when the DMA activity is finished, e.g.,
565 from the interrupt which told you that the DMA transfer is done.
567 With scatterlists, you map a region gathered from several regions by::
569 int i, count = dma_map_sg(dev, sglist, nents, direction);
570 struct scatterlist *sg;
572 for_each_sg(sglist, sg, count, i) {
573 hw_address[i] = sg_dma_address(sg);
574 hw_len[i] = sg_dma_len(sg);
577 where nents is the number of entries in the sglist.
579 The implementation is free to merge several consecutive sglist entries
580 into one (e.g. if DMA mapping is done with PAGE_SIZE granularity, any
581 consecutive sglist entries can be merged into one provided the first one
582 ends and the second one starts on a page boundary - in fact this is a huge
583 advantage for cards which either cannot do scatter-gather or have very
584 limited number of scatter-gather entries) and returns the actual number
585 of sg entries it mapped them to. On failure 0 is returned.
587 Then you should loop count times (note: this can be less than nents times)
588 and use sg_dma_address() and sg_dma_len() macros where you previously
589 accessed sg->address and sg->length as shown above.
591 To unmap a scatterlist, just call::
593 dma_unmap_sg(dev, sglist, nents, direction);
595 Again, make sure DMA activity has already finished.
599 The 'nents' argument to the dma_unmap_sg call must be
600 the _same_ one you passed into the dma_map_sg call,
601 it should _NOT_ be the 'count' value _returned_ from the
604 Every dma_map_{single,sg}() call should have its dma_unmap_{single,sg}()
605 counterpart, because the DMA address space is a shared resource and
606 you could render the machine unusable by consuming all DMA addresses.
608 If you need to use the same streaming DMA region multiple times and touch
609 the data in between the DMA transfers, the buffer needs to be synced
610 properly in order for the CPU and device to see the most up-to-date and
611 correct copy of the DMA buffer.
613 So, firstly, just map it with dma_map_{single,sg}(), and after each DMA
614 transfer call either::
616 dma_sync_single_for_cpu(dev, dma_handle, size, direction);
620 dma_sync_sg_for_cpu(dev, sglist, nents, direction);
624 Then, if you wish to let the device get at the DMA area again,
625 finish accessing the data with the CPU, and then before actually
626 giving the buffer to the hardware call either::
628 dma_sync_single_for_device(dev, dma_handle, size, direction);
632 dma_sync_sg_for_device(dev, sglist, nents, direction);
638 The 'nents' argument to dma_sync_sg_for_cpu() and
639 dma_sync_sg_for_device() must be the same passed to
640 dma_map_sg(). It is _NOT_ the count returned by
643 After the last DMA transfer call one of the DMA unmap routines
644 dma_unmap_{single,sg}(). If you don't touch the data from the first
645 dma_map_*() call till dma_unmap_*(), then you don't have to call the
646 dma_sync_*() routines at all.
648 Here is pseudo code which shows a situation in which you would need
649 to use the dma_sync_*() interfaces::
651 my_card_setup_receive_buffer(struct my_card *cp, char *buffer, int len)
655 mapping = dma_map_single(cp->dev, buffer, len, DMA_FROM_DEVICE);
656 if (dma_mapping_error(cp->dev, mapping)) {
658 * reduce current DMA mapping usage,
659 * delay and try again later or
662 goto map_error_handling;
667 cp->rx_dma = mapping;
669 give_rx_buf_to_card(cp);
674 my_card_interrupt_handler(int irq, void *devid, struct pt_regs *regs)
676 struct my_card *cp = devid;
679 if (read_card_status(cp) == RX_BUF_TRANSFERRED) {
680 struct my_card_header *hp;
682 /* Examine the header to see if we wish
683 * to accept the data. But synchronize
684 * the DMA transfer with the CPU first
685 * so that we see updated contents.
687 dma_sync_single_for_cpu(&cp->dev, cp->rx_dma,
691 /* Now it is safe to examine the buffer. */
692 hp = (struct my_card_header *) cp->rx_buf;
693 if (header_is_ok(hp)) {
694 dma_unmap_single(&cp->dev, cp->rx_dma, cp->rx_len,
696 pass_to_upper_layers(cp->rx_buf);
697 make_and_setup_new_rx_buf(cp);
699 /* CPU should not write to
700 * DMA_FROM_DEVICE-mapped area,
701 * so dma_sync_single_for_device() is
702 * not needed here. It would be required
703 * for DMA_BIDIRECTIONAL mapping if
704 * the memory was modified.
706 give_rx_buf_to_card(cp);
711 Drivers converted fully to this interface should not use virt_to_bus() any
712 longer, nor should they use bus_to_virt(). Some drivers have to be changed a
713 little bit, because there is no longer an equivalent to bus_to_virt() in the
714 dynamic DMA mapping scheme - you have to always store the DMA addresses
715 returned by the dma_alloc_coherent(), dma_pool_alloc(), and dma_map_single()
716 calls (dma_map_sg() stores them in the scatterlist itself if the platform
717 supports dynamic DMA mapping in hardware) in your driver structures and/or
718 in the card registers.
720 All drivers should be using these interfaces with no exceptions. It
721 is planned to completely remove virt_to_bus() and bus_to_virt() as
722 they are entirely deprecated. Some ports already do not provide these
723 as it is impossible to correctly support them.
728 DMA address space is limited on some architectures and an allocation
729 failure can be determined by:
731 - checking if dma_alloc_coherent() returns NULL or dma_map_sg returns 0
733 - checking the dma_addr_t returned from dma_map_single() and dma_map_page()
734 by using dma_mapping_error()::
736 dma_addr_t dma_handle;
738 dma_handle = dma_map_single(dev, addr, size, direction);
739 if (dma_mapping_error(dev, dma_handle)) {
741 * reduce current DMA mapping usage,
742 * delay and try again later or
745 goto map_error_handling;
748 - unmap pages that are already mapped, when mapping error occurs in the middle
749 of a multiple page mapping attempt. These example are applicable to
750 dma_map_page() as well.
754 dma_addr_t dma_handle1;
755 dma_addr_t dma_handle2;
757 dma_handle1 = dma_map_single(dev, addr, size, direction);
758 if (dma_mapping_error(dev, dma_handle1)) {
760 * reduce current DMA mapping usage,
761 * delay and try again later or
764 goto map_error_handling1;
766 dma_handle2 = dma_map_single(dev, addr, size, direction);
767 if (dma_mapping_error(dev, dma_handle2)) {
769 * reduce current DMA mapping usage,
770 * delay and try again later or
773 goto map_error_handling2;
779 dma_unmap_single(dma_handle1);
785 * if buffers are allocated in a loop, unmap all mapped buffers when
786 * mapping error is detected in the middle
790 dma_addr_t array[DMA_BUFFERS];
793 for (i = 0; i < DMA_BUFFERS; i++) {
797 dma_addr = dma_map_single(dev, addr, size, direction);
798 if (dma_mapping_error(dev, dma_addr)) {
800 * reduce current DMA mapping usage,
801 * delay and try again later or
804 goto map_error_handling;
806 array[i].dma_addr = dma_addr;
814 for (i = 0; i < save_index; i++) {
818 dma_unmap_single(array[i].dma_addr);
821 Networking drivers must call dev_kfree_skb() to free the socket buffer
822 and return NETDEV_TX_OK if the DMA mapping fails on the transmit hook
823 (ndo_start_xmit). This means that the socket buffer is just dropped in
826 SCSI drivers must return SCSI_MLQUEUE_HOST_BUSY if the DMA mapping
827 fails in the queuecommand hook. This means that the SCSI subsystem
828 passes the command to the driver again later.
830 Optimizing Unmap State Space Consumption
831 ========================================
833 On many platforms, dma_unmap_{single,page}() is simply a nop.
834 Therefore, keeping track of the mapping address and length is a waste
835 of space. Instead of filling your drivers up with ifdefs and the like
836 to "work around" this (which would defeat the whole purpose of a
837 portable API) the following facilities are provided.
839 Actually, instead of describing the macros one by one, we'll
840 transform some example code.
842 1) Use DEFINE_DMA_UNMAP_{ADDR,LEN} in state saving structures.
855 DEFINE_DMA_UNMAP_ADDR(mapping);
856 DEFINE_DMA_UNMAP_LEN(len);
859 2) Use dma_unmap_{addr,len}_set() to set these values.
862 ringp->mapping = FOO;
867 dma_unmap_addr_set(ringp, mapping, FOO);
868 dma_unmap_len_set(ringp, len, BAR);
870 3) Use dma_unmap_{addr,len}() to access these values.
873 dma_unmap_single(dev, ringp->mapping, ringp->len,
878 dma_unmap_single(dev,
879 dma_unmap_addr(ringp, mapping),
880 dma_unmap_len(ringp, len),
883 It really should be self-explanatory. We treat the ADDR and LEN
884 separately, because it is possible for an implementation to only
885 need the address in order to perform the unmap operation.
890 If you are just writing drivers for Linux and do not maintain
891 an architecture port for the kernel, you can safely skip down
894 1) Struct scatterlist requirements.
896 You need to enable CONFIG_NEED_SG_DMA_LENGTH if the architecture
897 supports IOMMUs (including software IOMMU).
901 Architectures must ensure that kmalloc'ed buffer is
902 DMA-safe. Drivers and subsystems depend on it. If an architecture
903 isn't fully DMA-coherent (i.e. hardware doesn't ensure that data in
904 the CPU cache is identical to data in main memory),
905 ARCH_DMA_MINALIGN must be set so that the memory allocator
906 makes sure that kmalloc'ed buffer doesn't share a cache line with
907 the others. See arch/arm/include/asm/cache.h as an example.
909 Note that ARCH_DMA_MINALIGN is about DMA memory alignment
910 constraints. You don't need to worry about the architecture data
911 alignment constraints (e.g. the alignment constraints about 64-bit
917 This document, and the API itself, would not be in its current
918 form without the feedback and suggestions from numerous individuals.
919 We would like to specifically mention, in no particular order, the
922 Russell King <rmk@arm.linux.org.uk>
923 Leo Dagum <dagum@barrel.engr.sgi.com>
924 Ralf Baechle <ralf@oss.sgi.com>
925 Grant Grundler <grundler@cup.hp.com>
926 Jay Estabrook <Jay.Estabrook@compaq.com>
927 Thomas Sailer <sailer@ife.ee.ethz.ch>
928 Andrea Arcangeli <andrea@suse.de>
929 Jens Axboe <jens.axboe@oracle.com>
930 David Mosberger-Tang <davidm@hpl.hp.com>