5 This document describes the usage and semantics of the arm64 ELF hwcaps.
11 Some hardware or software features are only available on some CPU
12 implementations, and/or with certain kernel configurations, but have no
13 architected discovery mechanism available to userspace code at EL0. The
14 kernel exposes the presence of these features to userspace through a set
15 of flags called hwcaps, exposed in the auxilliary vector.
17 Userspace software can test for features by acquiring the AT_HWCAP or
18 AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant
21 bool floating_point_is_present(void)
23 unsigned long hwcaps = getauxval(AT_HWCAP);
24 if (hwcaps & HWCAP_FP)
30 Where software relies on a feature described by a hwcap, it should check
31 the relevant hwcap flag to verify that the feature is present before
32 attempting to make use of the feature.
34 Features cannot be probed reliably through other means. When a feature
35 is not available, attempting to use it may result in unpredictable
36 behaviour, and is not guaranteed to result in any reliable indication
37 that the feature is unavailable, such as a SIGILL.
40 2. Interpretation of hwcaps
41 ---------------------------
43 The majority of hwcaps are intended to indicate the presence of features
44 which are described by architected ID registers inaccessible to
45 userspace code at EL0. These hwcaps are defined in terms of ID register
46 fields, and should be interpreted with reference to the definition of
47 these fields in the ARM Architecture Reference Manual (ARM ARM).
49 Such hwcaps are described below in the form::
51 Functionality implied by idreg.field == val.
53 Such hwcaps indicate the availability of functionality that the ARM ARM
54 defines as being present when idreg.field has value val, but do not
55 indicate that idreg.field is precisely equal to val, nor do they
56 indicate the absence of functionality implied by other values of
59 Other hwcaps may indicate the presence of features which cannot be
60 described by ID registers alone. These may be described without
61 reference to ID registers, and may refer to other documentation.
64 3. The hwcaps exposed in AT_HWCAP
65 ---------------------------------
68 Functionality implied by ID_AA64PFR0_EL1.FP == 0b0000.
71 Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0000.
74 The generic timer is configured to generate events at a frequency of
78 Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0001.
81 Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0010.
84 Functionality implied by ID_AA64ISAR0_EL1.SHA1 == 0b0001.
87 Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0001.
90 Functionality implied by ID_AA64ISAR0_EL1.CRC32 == 0b0001.
93 Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0010.
96 Functionality implied by ID_AA64PFR0_EL1.FP == 0b0001.
99 Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0001.
102 EL0 access to certain ID registers is available, to the extent
103 described by Documentation/arm64/cpu-feature-registers.rst.
105 These ID registers may imply the availability of features.
108 Functionality implied by ID_AA64ISAR0_EL1.RDM == 0b0001.
111 Functionality implied by ID_AA64ISAR1_EL1.JSCVT == 0b0001.
114 Functionality implied by ID_AA64ISAR1_EL1.FCMA == 0b0001.
117 Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0001.
120 Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0001.
124 Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.
127 Functionality implied by ID_AA64ISAR0_EL1.SHA3 == 0b0001.
130 Functionality implied by ID_AA64ISAR0_EL1.SM3 == 0b0001.
133 Functionality implied by ID_AA64ISAR0_EL1.SM4 == 0b0001.
136 Functionality implied by ID_AA64ISAR0_EL1.DP == 0b0001.
139 Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0010.
142 Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001.
146 Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001.
150 Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.
154 Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.
158 Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.
162 Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.
166 Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.
169 Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001.
172 Functionality implied by ID_AA64PFR0_EL1.DIT == 0b0001.
175 Functionality implied by ID_AA64MMFR2_EL1.AT == 0b0001.
178 Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0010.
181 Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0001.
185 Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.
188 Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010.
191 Functionality implied by ID_AA64ISAR1_EL1.APA == 0b0001 or
192 ID_AA64ISAR1_EL1.API == 0b0001, as described by
193 Documentation/arm64/pointer-authentication.rst.
196 Functionality implied by ID_AA64ISAR1_EL1.GPA == 0b0001 or
197 ID_AA64ISAR1_EL1.GPI == 0b0001, as described by
198 Documentation/arm64/pointer-authentication.rst.
202 Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.
205 4. Unused AT_HWCAP bits
206 -----------------------
208 For interoperation with userspace, the kernel guarantees that bits 62
209 and 63 of AT_HWCAP will always be returned as 0.