1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM CPUs bindings
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
19 https://www.devicetree.org/specifications/
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
23 ================================
24 Convention used in this document
25 ================================
27 This document follows the conventions described in the Devicetree
28 Specification, with the addition:
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
33 =====================================
34 cpus and cpu node bindings definition
35 =====================================
37 The ARM architecture, in accordance with the Devicetree Specification,
38 requires the cpus and cpu nodes to be present and contain the properties
45 Usage and definition depend on ARM architecture version and
48 On uniprocessor ARM architectures previous to v7
49 this property is required and must be set to 0.
51 On ARM 11 MPcore based systems this property is
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
59 On 32-bit ARM v7 or later systems this property is
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
66 All other bits in the reg cell must be set to 0.
68 On ARM v8 64-bit systems this property is required
69 and matches the MPIDR_EL1 register affinity bits.
71 * If cpus node's #address-cells property is set to 2
73 The first reg cell bits [7:0] must be set to
74 bits [39:32] of MPIDR_EL1.
76 The second reg cell bits [23:0] must be set to
77 bits [23:0] of MPIDR_EL1.
79 * If cpus node's #address-cells property is set to 1
81 The reg cell bits [23:0] must be set to bits [23:0]
84 All other bits in the reg cells must be set to 0.
118 - arm,armv8 # Only for s/w models
152 - nvidia,tegra132-denver
153 - nvidia,tegra186-denver
154 - nvidia,tegra194-carmel
163 - $ref: '/schemas/types.yaml#/definitions/string'
165 # On ARM v8 64-bit this property is required
169 # On ARM 32-bit systems this property is optional
172 - allwinner,sun6i-a31
173 - allwinner,sun8i-a23
174 - allwinner,sun9i-a80-smp
175 - allwinner,sun8i-a83t-smp
177 - amlogic,meson8b-smp
179 - brcm,bcm11351-cpu-method
185 - marvell,armada-375-smp
186 - marvell,armada-380-smp
187 - marvell,armada-390-smp
188 - marvell,armada-xp-smp
189 - marvell,98dx3236-smp
190 - mediatek,mt6589-smp
191 - mediatek,mt81xx-tz-smp
196 - renesas,r9a06g032-smp
197 - rockchip,rk3036-smp
198 - rockchip,rk3066-smp
199 - socionext,milbeaut-m10v-smp
203 $ref: '/schemas/types.yaml#/definitions/uint64'
206 Required for systems that have an "enable-method"
207 property value of "spin-table".
208 On ARM v8 64-bit systems must be a two cell
209 property identifying a 64-bit zero-initialised
213 $ref: '/schemas/types.yaml#/definitions/phandle-array'
215 List of phandles to idle state nodes supported
216 by this cpu (see ./idle-states.txt).
219 $ref: '/schemas/types.yaml#/definitions/uint32'
221 u32 value representing CPU capacity (see ./cpu-capacity.txt) in
222 DMIPS/MHz, relative to highest capacity-dmips-mhz
225 dynamic-power-coefficient:
226 $ref: '/schemas/types.yaml#/definitions/uint32'
228 A u32 value that represents the running time dynamic
229 power coefficient in units of uW/MHz/V^2. The
230 coefficient can either be calculated from power
231 measurements or derived by analysis.
233 The dynamic power consumption of the CPU is
234 proportional to the square of the Voltage (V) and
235 the clock frequency (f). The coefficient is used to
236 calculate the dynamic power as below -
238 Pdyn = dynamic-power-coefficient * V^2 * f
240 where voltage is in V, frequency is in MHz.
243 $ref: '/schemas/types.yaml#/definitions/phandle'
245 Specifies the SAW* node associated with this CPU.
247 Required for systems that have an "enable-method" property
248 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
250 * arm/msm/qcom,saw2.txt
253 $ref: '/schemas/types.yaml#/definitions/phandle'
255 Specifies the ACC* node associated with this CPU.
257 Required for systems that have an "enable-method" property
258 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
260 * arm/msm/qcom,kpss-acc.txt
263 $ref: '/schemas/types.yaml#/definitions/phandle'
265 Specifies the syscon node controlling the cpu core power domains.
267 Optional for systems that have an "enable-method"
268 property value of "rockchip,rk3066-smp"
269 While optional, it is the preferred way to get access to
270 the cpu-core power-domains.
278 rockchip,pmu: [enable-method]
284 #address-cells = <1>;
288 compatible = "arm,cortex-a15";
294 compatible = "arm,cortex-a15";
300 compatible = "arm,cortex-a7";
306 compatible = "arm,cortex-a7";
312 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
315 #address-cells = <1>;
319 compatible = "arm,cortex-a8";
325 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
328 #address-cells = <1>;
332 compatible = "arm,arm926ej-s";
338 // Example 4 (ARM Cortex-A57 64-bit system):
341 #address-cells = <2>;
345 compatible = "arm,cortex-a57";
347 enable-method = "spin-table";
348 cpu-release-addr = <0 0x20000000>;
353 compatible = "arm,cortex-a57";
355 enable-method = "spin-table";
356 cpu-release-addr = <0 0x20000000>;
361 compatible = "arm,cortex-a57";
363 enable-method = "spin-table";
364 cpu-release-addr = <0 0x20000000>;
369 compatible = "arm,cortex-a57";
371 enable-method = "spin-table";
372 cpu-release-addr = <0 0x20000000>;
377 compatible = "arm,cortex-a57";
379 enable-method = "spin-table";
380 cpu-release-addr = <0 0x20000000>;
385 compatible = "arm,cortex-a57";
387 enable-method = "spin-table";
388 cpu-release-addr = <0 0x20000000>;
393 compatible = "arm,cortex-a57";
395 enable-method = "spin-table";
396 cpu-release-addr = <0 0x20000000>;
401 compatible = "arm,cortex-a57";
403 enable-method = "spin-table";
404 cpu-release-addr = <0 0x20000000>;
409 compatible = "arm,cortex-a57";
411 enable-method = "spin-table";
412 cpu-release-addr = <0 0x20000000>;
417 compatible = "arm,cortex-a57";
419 enable-method = "spin-table";
420 cpu-release-addr = <0 0x20000000>;
425 compatible = "arm,cortex-a57";
427 enable-method = "spin-table";
428 cpu-release-addr = <0 0x20000000>;
433 compatible = "arm,cortex-a57";
435 enable-method = "spin-table";
436 cpu-release-addr = <0 0x20000000>;
441 compatible = "arm,cortex-a57";
443 enable-method = "spin-table";
444 cpu-release-addr = <0 0x20000000>;
449 compatible = "arm,cortex-a57";
451 enable-method = "spin-table";
452 cpu-release-addr = <0 0x20000000>;
457 compatible = "arm,cortex-a57";
459 enable-method = "spin-table";
460 cpu-release-addr = <0 0x20000000>;
465 compatible = "arm,cortex-a57";
467 enable-method = "spin-table";
468 cpu-release-addr = <0 0x20000000>;