1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM CPUs bindings
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
19 https://www.devicetree.org/specifications/
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
23 ================================
24 Convention used in this document
25 ================================
27 This document follows the conventions described in the Devicetree
28 Specification, with the addition:
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
33 =====================================
34 cpus and cpu node bindings definition
35 =====================================
37 The ARM architecture, in accordance with the Devicetree Specification,
38 requires the cpus and cpu nodes to be present and contain the properties
45 Usage and definition depend on ARM architecture version and
48 On uniprocessor ARM architectures previous to v7
49 this property is required and must be set to 0.
51 On ARM 11 MPcore based systems this property is
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
59 On 32-bit ARM v7 or later systems this property is
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
66 All other bits in the reg cell must be set to 0.
68 On ARM v8 64-bit systems this property is required
69 and matches the MPIDR_EL1 register affinity bits.
71 * If cpus node's #address-cells property is set to 2
73 The first reg cell bits [7:0] must be set to
74 bits [39:32] of MPIDR_EL1.
76 The second reg cell bits [23:0] must be set to
77 bits [23:0] of MPIDR_EL1.
79 * If cpus node's #address-cells property is set to 1
81 The reg cell bits [23:0] must be set to bits [23:0]
84 All other bits in the reg cells must be set to 0.
118 - arm,armv8 # Only for s/w models
152 - nvidia,tegra132-denver
153 - nvidia,tegra186-denver
154 - nvidia,tegra194-carmel
162 - $ref: '/schemas/types.yaml#/definitions/string'
164 # On ARM v8 64-bit this property is required
168 # On ARM 32-bit systems this property is optional
171 - allwinner,sun6i-a31
172 - allwinner,sun8i-a23
173 - allwinner,sun9i-a80-smp
174 - allwinner,sun8i-a83t-smp
176 - amlogic,meson8b-smp
178 - brcm,bcm11351-cpu-method
184 - marvell,armada-375-smp
185 - marvell,armada-380-smp
186 - marvell,armada-390-smp
187 - marvell,armada-xp-smp
188 - marvell,98dx3236-smp
189 - mediatek,mt6589-smp
190 - mediatek,mt81xx-tz-smp
195 - renesas,r9a06g032-smp
196 - rockchip,rk3036-smp
197 - rockchip,rk3066-smp
198 - socionext,milbeaut-m10v-smp
202 $ref: '/schemas/types.yaml#/definitions/uint64'
205 Required for systems that have an "enable-method"
206 property value of "spin-table".
207 On ARM v8 64-bit systems must be a two cell
208 property identifying a 64-bit zero-initialised
212 $ref: '/schemas/types.yaml#/definitions/phandle-array'
214 List of phandles to idle state nodes supported
215 by this cpu (see ./idle-states.txt).
218 $ref: '/schemas/types.yaml#/definitions/uint32'
220 u32 value representing CPU capacity (see ./cpu-capacity.txt) in
221 DMIPS/MHz, relative to highest capacity-dmips-mhz
224 dynamic-power-coefficient:
225 $ref: '/schemas/types.yaml#/definitions/uint32'
227 A u32 value that represents the running time dynamic
228 power coefficient in units of uW/MHz/V^2. The
229 coefficient can either be calculated from power
230 measurements or derived by analysis.
232 The dynamic power consumption of the CPU is
233 proportional to the square of the Voltage (V) and
234 the clock frequency (f). The coefficient is used to
235 calculate the dynamic power as below -
237 Pdyn = dynamic-power-coefficient * V^2 * f
239 where voltage is in V, frequency is in MHz.
242 $ref: '/schemas/types.yaml#/definitions/phandle'
244 Specifies the SAW* node associated with this CPU.
246 Required for systems that have an "enable-method" property
247 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
249 * arm/msm/qcom,saw2.txt
252 $ref: '/schemas/types.yaml#/definitions/phandle'
254 Specifies the ACC* node associated with this CPU.
256 Required for systems that have an "enable-method" property
257 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
259 * arm/msm/qcom,kpss-acc.txt
262 $ref: '/schemas/types.yaml#/definitions/phandle'
264 Specifies the syscon node controlling the cpu core power domains.
266 Optional for systems that have an "enable-method"
267 property value of "rockchip,rk3066-smp"
268 While optional, it is the preferred way to get access to
269 the cpu-core power-domains.
277 rockchip,pmu: [enable-method]
283 #address-cells = <1>;
287 compatible = "arm,cortex-a15";
293 compatible = "arm,cortex-a15";
299 compatible = "arm,cortex-a7";
305 compatible = "arm,cortex-a7";
311 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
314 #address-cells = <1>;
318 compatible = "arm,cortex-a8";
324 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
327 #address-cells = <1>;
331 compatible = "arm,arm926ej-s";
337 // Example 4 (ARM Cortex-A57 64-bit system):
340 #address-cells = <2>;
344 compatible = "arm,cortex-a57";
346 enable-method = "spin-table";
347 cpu-release-addr = <0 0x20000000>;
352 compatible = "arm,cortex-a57";
354 enable-method = "spin-table";
355 cpu-release-addr = <0 0x20000000>;
360 compatible = "arm,cortex-a57";
362 enable-method = "spin-table";
363 cpu-release-addr = <0 0x20000000>;
368 compatible = "arm,cortex-a57";
370 enable-method = "spin-table";
371 cpu-release-addr = <0 0x20000000>;
376 compatible = "arm,cortex-a57";
378 enable-method = "spin-table";
379 cpu-release-addr = <0 0x20000000>;
384 compatible = "arm,cortex-a57";
386 enable-method = "spin-table";
387 cpu-release-addr = <0 0x20000000>;
392 compatible = "arm,cortex-a57";
394 enable-method = "spin-table";
395 cpu-release-addr = <0 0x20000000>;
400 compatible = "arm,cortex-a57";
402 enable-method = "spin-table";
403 cpu-release-addr = <0 0x20000000>;
408 compatible = "arm,cortex-a57";
410 enable-method = "spin-table";
411 cpu-release-addr = <0 0x20000000>;
416 compatible = "arm,cortex-a57";
418 enable-method = "spin-table";
419 cpu-release-addr = <0 0x20000000>;
424 compatible = "arm,cortex-a57";
426 enable-method = "spin-table";
427 cpu-release-addr = <0 0x20000000>;
432 compatible = "arm,cortex-a57";
434 enable-method = "spin-table";
435 cpu-release-addr = <0 0x20000000>;
440 compatible = "arm,cortex-a57";
442 enable-method = "spin-table";
443 cpu-release-addr = <0 0x20000000>;
448 compatible = "arm,cortex-a57";
450 enable-method = "spin-table";
451 cpu-release-addr = <0 0x20000000>;
456 compatible = "arm,cortex-a57";
458 enable-method = "spin-table";
459 cpu-release-addr = <0 0x20000000>;
464 compatible = "arm,cortex-a57";
466 enable-method = "spin-table";
467 cpu-release-addr = <0 0x20000000>;