1 Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
2 ---------------------------------------------------------
5 - compatible : Should be "xlnx,zynq-can-1.0" for Zynq CAN
6 controllers and "xlnx,axi-can-1.00.a" for Axi CAN
8 - reg : Physical base address and size of the Axi CAN/Zynq
10 - interrupts : Property with a value describing the interrupt
12 - clock-names : List of input clock names - "can_clk", "pclk"
13 (For CANPS), "can_clk" , "s_axi_aclk"(For AXI CAN)
14 (See clock bindings for details).
15 - clocks : Clock phandles (see clock bindings for details).
16 - tx-fifo-depth : Can Tx fifo depth.
17 - rx-fifo-depth : Can Rx fifo depth.
22 For Zynq CANPS Dts file:
23 zynq_can_0: can@e0008000 {
24 compatible = "xlnx,zynq-can-1.0";
25 clocks = <&clkc 19>, <&clkc 36>;
26 clock-names = "can_clk", "pclk";
27 reg = <0xe0008000 0x1000>;
28 interrupts = <0 28 4>;
29 interrupt-parent = <&intc>;
30 tx-fifo-depth = <0x40>;
31 rx-fifo-depth = <0x40>;
34 axi_can_0: axi-can@40000000 {
35 compatible = "xlnx,axi-can-1.00.a";
36 clocks = <&clkc 0>, <&clkc 1>;
37 clock-names = "can_clk","s_axi_aclk" ;
38 reg = <0x40000000 0x10000>;
39 interrupt-parent = <&intc>;
40 interrupts = <0 59 1>;
41 tx-fifo-depth = <0x40>;
42 rx-fifo-depth = <0x40>;