1 * Allwinner sun8i GMAC ethernet controller
3 This device is a platform glue layer for stmmac.
4 Please see stmmac.txt for the other unchanged properties.
7 - compatible: must be one of the following string:
8 "allwinner,sun8i-a83t-emac"
9 "allwinner,sun8i-h3-emac"
10 "allwinner,sun8i-r40-gmac"
11 "allwinner,sun8i-v3s-emac"
12 "allwinner,sun50i-a64-emac"
13 - reg: address and length of the register for the device.
14 - interrupts: interrupt for the device
15 - interrupt-names: must be "macirq"
16 - clocks: A phandle to the reference clock for this device
17 - clock-names: must be "stmmaceth"
18 - resets: A phandle to the reset control for this device
19 - reset-names: must be "stmmaceth"
20 - phy-mode: See ethernet.txt
21 - phy-handle: See ethernet.txt
22 - #address-cells: shall be 1
23 - #size-cells: shall be 0
24 - syscon: A phandle to the device containing the EMAC or GMAC clock register
27 - allwinner,tx-delay-ps: TX clock delay chain value in ps.
28 Range is 0-700. Default is 0.
29 Unavailable for allwinner,sun8i-r40-gmac
30 - allwinner,rx-delay-ps: RX clock delay chain value in ps.
31 Range is 0-3100. Default is 0.
32 Range is 0-700 for allwinner,sun8i-r40-gmac
33 Both delay properties need to be a multiple of 100. They control the
34 clock delay for external RGMII PHY. They do not apply to the internal
35 PHY or external non-RGMII PHYs.
37 Optional properties for the following compatibles:
38 - "allwinner,sun8i-h3-emac",
39 - "allwinner,sun8i-v3s-emac":
40 - allwinner,leds-active-low: EPHY LEDs are active low
42 Required child node of emac:
43 - mdio bus node: should be named mdio with compatible "snps,dwmac-mdio"
45 Required properties of the mdio node:
46 - #address-cells: shall be 1
47 - #size-cells: shall be 0
49 The device node referenced by "phy" or "phy-handle" must be a child node
50 of the mdio node. See phy.txt for the generic PHY bindings.
52 The following compatibles require that the emac node have a mdio-mux child
53 node called "mdio-mux":
54 - "allwinner,sun8i-h3-emac"
55 - "allwinner,sun8i-v3s-emac":
56 Required properties for the mdio-mux node:
57 - compatible = "allwinner,sun8i-h3-mdio-mux"
58 - mdio-parent-bus: a phandle to EMAC mdio
59 - one child mdio for the integrated mdio with the compatible
60 "allwinner,sun8i-h3-mdio-internal"
61 - one child mdio for the external mdio if present (V3s have none)
62 Required properties for the mdio-mux children node:
63 - reg: 1 for internal MDIO bus, 2 for external MDIO bus
65 The following compatibles require a PHY node representing the integrated
66 PHY, under the integrated MDIO bus node if an mdio-mux node is used:
67 - "allwinner,sun8i-h3-emac",
68 - "allwinner,sun8i-v3s-emac":
70 Additional information regarding generic multiplexer properties can be found
71 at Documentation/devicetree/bindings/net/mdio-mux.txt
73 Required properties of the integrated phy node:
74 - clocks: a phandle to the reference clock for the EPHY
75 - resets: a phandle to the reset control for the EPHY
76 - Must be a child of the integrated mdio
78 Example with integrated PHY:
79 emac: ethernet@1c0b000 {
80 compatible = "allwinner,sun8i-h3-emac";
82 reg = <0x01c0b000 0x104>;
83 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-names = "macirq";
85 resets = <&ccu RST_BUS_EMAC>;
86 reset-names = "stmmaceth";
87 clocks = <&ccu CLK_BUS_EMAC>;
88 clock-names = "stmmaceth";
92 phy-handle = <&int_mii_phy>;
94 allwinner,leds-active-low;
99 compatible = "snps,dwmac-mdio";
103 compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux";
104 #address-cells = <1>;
107 mdio-parent-bus = <&mdio>;
110 compatible = "allwinner,sun8i-h3-mdio-internal";
112 #address-cells = <1>;
114 int_mii_phy: ethernet-phy@1 {
116 clocks = <&ccu CLK_BUS_EPHY>;
117 resets = <&ccu RST_BUS_EPHY>;
123 #address-cells = <1>;
129 Example with external PHY:
130 emac: ethernet@1c0b000 {
131 compatible = "allwinner,sun8i-h3-emac";
133 reg = <0x01c0b000 0x104>;
134 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
135 interrupt-names = "macirq";
136 resets = <&ccu RST_BUS_EMAC>;
137 reset-names = "stmmaceth";
138 clocks = <&ccu CLK_BUS_EMAC>;
139 clock-names = "stmmaceth";
140 #address-cells = <1>;
143 phy-handle = <&ext_rgmii_phy>;
145 allwinner,leds-active-low;
148 #address-cells = <1>;
150 compatible = "snps,dwmac-mdio";
154 compatible = "allwinner,sun8i-h3-mdio-mux";
155 #address-cells = <1>;
158 mdio-parent-bus = <&mdio>;
161 compatible = "allwinner,sun8i-h3-mdio-internal";
163 #address-cells = <1>;
165 int_mii_phy: ethernet-phy@1 {
167 clocks = <&ccu CLK_BUS_EPHY>;
168 resets = <&ccu RST_BUS_EPHY>;
173 #address-cells = <1>;
175 ext_rgmii_phy: ethernet-phy@1 {
182 Example with SoC without integrated PHY
184 emac: ethernet@1c0b000 {
185 compatible = "allwinner,sun8i-a83t-emac";
187 reg = <0x01c0b000 0x104>;
188 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
189 interrupt-names = "macirq";
190 resets = <&ccu RST_BUS_EMAC>;
191 reset-names = "stmmaceth";
192 clocks = <&ccu CLK_BUS_EMAC>;
193 clock-names = "stmmaceth";
194 #address-cells = <1>;
197 phy-handle = <&ext_rgmii_phy>;
201 compatible = "snps,dwmac-mdio";
202 #address-cells = <1>;
204 ext_rgmii_phy: ethernet-phy@1 {