1 Qualcomm QMP PHY controller
2 ===========================
4 QMP phy controller supports physical layer functionality for a number of
5 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
8 - compatible: compatible list, contains:
9 "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
10 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
11 "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
12 "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
13 "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
14 "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
17 - index 0: address and length of register set for PHY's common
19 - index 1: address and length of the DP_COM control block (for
20 "qcom,sdm845-qmp-usb3-phy" only).
23 - For "qcom,sdm845-qmp-usb3-phy":
24 - Should be: "reg-base", "dp_com"
26 - The reg-names property shouldn't be defined.
28 - #clock-cells: must be 1
29 - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
30 interface (for pipe based PHYs). These clock are then gate-controlled
32 - #address-cells: must be 1
33 - #size-cells: must be 1
34 - ranges: must be present
36 - clocks: a list of phandles and clock-specifier pairs,
37 one for each entry in clock-names.
38 - clock-names: "cfg_ahb" for phy config clock,
39 "aux" for phy aux clock,
40 "ref" for 19.2 MHz ref clk,
41 "com_aux" for phy common block aux clock,
42 "ref_aux" for phy reference aux clock,
44 For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
45 For "qcom,msm8996-qmp-pcie-phy" must contain:
46 "aux", "cfg_ahb", "ref".
47 For "qcom,msm8996-qmp-usb3-phy" must contain:
48 "aux", "cfg_ahb", "ref".
49 For "qcom,sdm845-qmp-usb3-phy" must contain:
50 "aux", "cfg_ahb", "ref", "com_aux".
51 For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
52 "aux", "cfg_ahb", "ref", "com_aux".
53 For "qcom,sdm845-qmp-ufs-phy" must contain:
56 - resets: a list of phandles and reset controller specifier pairs,
57 one for each entry in reset-names.
58 - reset-names: "phy" for reset of phy block,
59 "common" for phy common block reset,
60 "cfg" for phy's ahb cfg block reset.
62 For "qcom,ipq8074-qmp-pcie-phy" must contain:
64 For "qcom,msm8996-qmp-pcie-phy" must contain:
65 "phy", "common", "cfg".
66 For "qcom,msm8996-qmp-usb3-phy" must contain
68 For "qcom,sdm845-qmp-usb3-phy" must contain:
70 For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
72 For "qcom,sdm845-qmp-ufs-phy": no resets are listed.
74 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
75 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
78 - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
82 - Each device node of QMP phy is required to have as many child nodes as
83 the number of lanes the PHY has.
85 Required properties for child node:
86 - reg: list of offset and length pairs of register sets for PHY blocks -
90 - index 3: pcs_misc (optional)
92 - #phy-cells: must be 0
94 Required properties child node of pcie and usb3 qmp phys:
95 - clocks: a list of phandles and clock-specifier pairs,
96 one for each entry in clock-names.
97 - clock-names: Must contain following:
98 "pipe<lane-number>" for pipe clock specific to each lane.
99 - clock-output-names: Name of the PHY clock that will be the parent for
100 the above pipe clock.
102 For "qcom,ipq8074-qmp-pcie-phy":
103 - "pcie20_phy0_pipe_clk" Pipe Clock parent
105 "pcie20_phy1_pipe_clk"
107 Required properties for child node of PHYs with lane reset, AKA:
108 "qcom,msm8996-qmp-pcie-phy"
109 - resets: a list of phandles and reset controller specifier pairs,
110 one for each entry in reset-names.
111 - reset-names: Must contain following:
112 "lane<lane-number>" for reset specific to each lane.
116 compatible = "qcom,msm8996-qmp-pcie-phy";
117 reg = <0x34000 0x488>;
119 #address-cells = <1>;
123 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
124 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
125 <&gcc GCC_PCIE_CLKREF_CLK>;
126 clock-names = "aux", "cfg_ahb", "ref";
128 vdda-phy-supply = <&pm8994_l28>;
129 vdda-pll-supply = <&pm8994_l12>;
131 resets = <&gcc GCC_PCIE_PHY_BCR>,
132 <&gcc GCC_PCIE_PHY_COM_BCR>,
133 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
134 reset-names = "phy", "common", "cfg";
136 pciephy_0: lane@35000 {
137 reg = <0x35000 0x130>,
142 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
143 clock-names = "pipe0";
144 clock-output-names = "pcie_0_pipe_clk_src";
145 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
146 reset-names = "lane0";
149 pciephy_1: lane@36000 {