1 * Samsung Exynos Power Domains
3 Exynos processors include support for multiple power domains which are used
4 to gate power to one or more peripherals on the processor.
7 - compatible: should be one of the following.
8 * samsung,exynos4210-pd - for exynos4210 type power domain.
9 * samsung,exynos5433-pd - for exynos5433 type power domain.
10 - reg: physical base address of the controller and length of memory mapped
12 - #power-domain-cells: number of cells in power domain specifier;
16 - clocks: List of clock handles. The parent clocks of the input clocks to the
17 devices in this power domain are set to oscclk before power gating
18 and restored back after powering on a domain. This is required for
19 all domains which are powered on and off and not required for unused
21 - clock-names: The following clocks can be specified:
22 - oscclk: Oscillator clock.
23 - clkN: Input clocks to the devices in this power domain. These clocks
24 will be reparented to oscclk before swithing power domain off.
25 Their original parent will be brought back after turning on
26 the domain. Maximum of 4 clocks (N = 0 to 3) are supported.
27 - asbN: Clocks required by asynchronous bridges (ASB) present in
28 the power domain. These clock should be enabled during power
29 domain on/off operations.
30 - power-domains: phandle pointing to the parent power domain, for more details
31 see Documentation/devicetree/bindings/power/power_domain.txt
33 Node of a device using power domains must have a power-domains property
34 defined with a phandle to respective power domain.
38 lcd0: power-domain-lcd0 {
39 compatible = "samsung,exynos4210-pd";
40 reg = <0x10023C00 0x10>;
41 #power-domain-cells = <0>;
44 mfc_pd: power-domain@10044060 {
45 compatible = "samsung,exynos4210-pd";
46 reg = <0x10044060 0x20>;
47 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
48 clock-names = "oscclk", "clk0";
49 #power-domain-cells = <0>;
52 See Documentation/devicetree/bindings/power/power_domain.txt for description
53 of consumer-side bindings.