2 * linux/arch/alpha/kernel/pci.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
9 /* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * PCI-PCI bridges cleanup
15 #include <linux/string.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/ioport.h>
19 #include <linux/kernel.h>
20 #include <linux/bootmem.h>
21 #include <linux/module.h>
22 #include <linux/cache.h>
23 #include <linux/slab.h>
24 #include <asm/machvec.h>
31 * Some string constants used by the various core logics.
34 const char *const pci_io_names[] = {
35 "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
36 "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
39 const char *const pci_mem_names[] = {
40 "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
41 "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
44 const char pci_hae0_name[] = "HAE0";
47 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
52 * The PCI controller list.
55 struct pci_controller *hose_head, **hose_tail = &hose_head;
56 struct pci_controller *pci_isa_hose;
62 static void quirk_isa_bridge(struct pci_dev *dev)
64 dev->class = PCI_CLASS_BRIDGE_ISA << 8;
66 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
68 static void quirk_cypress(struct pci_dev *dev)
70 /* The Notorious Cy82C693 chip. */
72 /* The generic legacy mode IDE fixup in drivers/pci/probe.c
73 doesn't work correctly with the Cypress IDE controller as
74 it has non-standard register layout. Fix that. */
75 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
76 dev->resource[2].start = dev->resource[3].start = 0;
77 dev->resource[2].end = dev->resource[3].end = 0;
78 dev->resource[2].flags = dev->resource[3].flags = 0;
79 if (PCI_FUNC(dev->devfn) == 2) {
80 dev->resource[0].start = 0x170;
81 dev->resource[0].end = 0x177;
82 dev->resource[1].start = 0x376;
83 dev->resource[1].end = 0x376;
87 /* The Cypress bridge responds on the PCI bus in the address range
88 0xffff0000-0xffffffff (conventional x86 BIOS ROM). There is no
89 way to turn this off. The bridge also supports several extended
90 BIOS ranges (disabled after power-up), and some consoles do turn
91 them on. So if we use a large direct-map window, or a large SG
92 window, we must avoid the entire 0xfff00000-0xffffffff region. */
93 if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
94 if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
95 __direct_map_size = 0xfff00000UL - __direct_map_base;
97 struct pci_controller *hose = dev->sysdata;
98 struct pci_iommu_arena *pci = hose->sg_pci;
99 if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
100 pci->size = 0xfff00000UL - pci->dma_base;
104 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
106 /* Called for each device after PCI setup is done. */
107 static void pcibios_fixup_final(struct pci_dev *dev)
109 unsigned int class = dev->class >> 8;
111 if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) {
112 dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
116 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
118 /* Just declaring that the power-of-ten prefixes are actually the
119 power-of-two ones doesn't make it true :) */
125 pcibios_align_resource(void *data, const struct resource *res,
126 resource_size_t size, resource_size_t align)
128 struct pci_dev *dev = data;
129 struct pci_controller *hose = dev->sysdata;
130 unsigned long alignto;
131 resource_size_t start = res->start;
133 if (res->flags & IORESOURCE_IO) {
134 /* Make sure we start at our min on all hoses */
135 if (start - hose->io_space->start < PCIBIOS_MIN_IO)
136 start = PCIBIOS_MIN_IO + hose->io_space->start;
139 * Put everything into 0x00-0xff region modulo 0x400
142 start = (start + 0x3ff) & ~0x3ff;
144 else if (res->flags & IORESOURCE_MEM) {
145 /* Make sure we start at our min on all hoses */
146 if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
147 start = PCIBIOS_MIN_MEM + hose->mem_space->start;
150 * The following holds at least for the Low Cost
151 * Alpha implementation of the PCI interface:
153 * In sparse memory address space, the first
154 * octant (16MB) of every 128MB segment is
155 * aliased to the very first 16 MB of the
156 * address space (i.e., it aliases the ISA
157 * memory address space). Thus, we try to
158 * avoid allocating PCI devices in that range.
159 * Can be allocated in 2nd-7th octant only.
160 * Devices that need more than 112MB of
161 * address space must be accessed through
162 * dense memory space only!
165 /* Align to multiple of size of minimum base. */
166 alignto = max_t(resource_size_t, 0x1000, align);
167 start = ALIGN(start, alignto);
168 if (hose->sparse_mem_base && size <= 7 * 16*MB) {
169 if (((start / (16*MB)) & 0x7) == 0) {
170 start &= ~(128*MB - 1);
172 start = ALIGN(start, alignto);
174 if (start/(128*MB) != (start + size - 1)/(128*MB)) {
175 start &= ~(128*MB - 1);
176 start += (128 + 16)*MB;
177 start = ALIGN(start, alignto);
191 if (alpha_mv.init_pci)
196 subsys_initcall(pcibios_init);
198 #ifdef ALPHA_RESTORE_SRM_SETUP
199 /* Store PCI device configuration left by SRM here. */
200 struct pdev_srm_saved_conf
202 struct pdev_srm_saved_conf *next;
206 static struct pdev_srm_saved_conf *srm_saved_configs;
208 static void pdev_save_srm_config(struct pci_dev *dev)
210 struct pdev_srm_saved_conf *tmp;
211 static int printed = 0;
213 if (!alpha_using_srm || pci_has_flag(PCI_PROBE_ONLY))
217 printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
221 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
223 printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
226 tmp->next = srm_saved_configs;
231 srm_saved_configs = tmp;
235 pci_restore_srm_config(void)
237 struct pdev_srm_saved_conf *tmp;
239 /* No need to restore if probed only. */
240 if (pci_has_flag(PCI_PROBE_ONLY))
243 /* Restore SRM config. */
244 for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
245 pci_restore_state(tmp->dev);
249 #define pdev_save_srm_config(dev) do {} while (0)
252 void pcibios_fixup_bus(struct pci_bus *bus)
254 struct pci_dev *dev = bus->self;
256 if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
257 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
258 pci_read_bridge_bases(bus);
261 list_for_each_entry(dev, &bus->devices, bus_list) {
262 pdev_save_srm_config(dev);
267 * If we set up a device for bus mastering, we need to check the latency
268 * timer as certain firmware forgets to set it properly, as seen
269 * on SX164 and LX164 with SRM.
272 pcibios_set_master(struct pci_dev *dev)
275 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
276 if (lat >= 16) return;
277 printk("PCI: Setting latency timer of device %s to 64\n",
279 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
283 pcibios_claim_one_bus(struct pci_bus *b)
286 struct pci_bus *child_bus;
288 list_for_each_entry(dev, &b->devices, bus_list) {
291 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
292 struct resource *r = &dev->resource[i];
294 if (r->parent || !r->start || !r->flags)
296 if (pci_has_flag(PCI_PROBE_ONLY) ||
297 (r->flags & IORESOURCE_PCI_FIXED)) {
298 if (pci_claim_resource(dev, i) == 0)
301 pci_claim_bridge_resource(dev, i);
306 list_for_each_entry(child_bus, &b->children, node)
307 pcibios_claim_one_bus(child_bus);
311 pcibios_claim_console_setup(void)
315 list_for_each_entry(b, &pci_root_buses, node)
316 pcibios_claim_one_bus(b);
320 common_init_pci(void)
322 struct pci_controller *hose;
323 struct list_head resources;
324 struct pci_host_bridge *bridge;
327 int need_domain_info = 0;
332 /* Scan all of the recorded PCI controllers. */
333 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
334 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
336 /* Adjust hose mem_space limit to prevent PCI allocations
337 in the iommu windows. */
338 pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
339 end = hose->mem_space->start + pci_mem_end;
340 if (hose->mem_space->end > end)
341 hose->mem_space->end = end;
343 INIT_LIST_HEAD(&resources);
344 pci_add_resource_offset(&resources, hose->io_space,
345 hose->io_space->start);
346 pci_add_resource_offset(&resources, hose->mem_space,
347 hose->mem_space->start);
349 bridge = pci_alloc_host_bridge(0);
353 list_splice_init(&resources, &bridge->windows);
354 bridge->dev.parent = NULL;
355 bridge->sysdata = hose;
356 bridge->busnr = next_busno;
357 bridge->ops = alpha_mv.pci_ops;
358 bridge->swizzle_irq = alpha_mv.pci_swizzle;
359 bridge->map_irq = alpha_mv.pci_map_irq;
361 ret = pci_scan_root_bus_bridge(bridge);
363 pci_free_host_bridge(bridge);
367 bus = hose->bus = bridge->bus;
368 hose->need_domain_info = need_domain_info;
369 next_busno = bus->busn_res.end + 1;
370 /* Don't allow 8-bit bus number overflow inside the hose -
371 reserve some space for bridges. */
372 if (next_busno > 224) {
374 need_domain_info = 1;
378 pcibios_claim_console_setup();
380 pci_assign_unassigned_resources();
381 for (hose = hose_head; hose; hose = hose->next) {
384 pci_bus_add_devices(bus);
388 struct pci_controller * __init
389 alloc_pci_controller(void)
391 struct pci_controller *hose;
393 hose = alloc_bootmem(sizeof(*hose));
396 hose_tail = &hose->next;
401 struct resource * __init
404 return alloc_bootmem(sizeof(struct resource));
408 /* Provide information on locations of various I/O regions in physical
409 memory. Do this on a per-card basis so that we choose the right hose. */
412 sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
414 struct pci_controller *hose;
417 /* from hose or from bus.devfn */
418 if (which & IOBASE_FROM_HOSE) {
419 for(hose = hose_head; hose; hose = hose->next)
420 if (hose->index == bus) break;
421 if (!hose) return -ENODEV;
423 /* Special hook for ISA access. */
424 if (bus == 0 && dfn == 0) {
427 dev = pci_get_bus_and_slot(bus, dfn);
435 switch (which & ~IOBASE_FROM_HOSE) {
438 case IOBASE_SPARSE_MEM:
439 return hose->sparse_mem_base;
440 case IOBASE_DENSE_MEM:
441 return hose->dense_mem_base;
442 case IOBASE_SPARSE_IO:
443 return hose->sparse_io_base;
444 case IOBASE_DENSE_IO:
445 return hose->dense_io_base;
446 case IOBASE_ROOT_BUS:
447 return hose->bus->number;
453 /* Destroy an __iomem token. Not copied from lib/iomap.c. */
455 void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
461 EXPORT_SYMBOL(pci_iounmap);
463 /* FIXME: Some boxes have multiple ISA bridges! */
464 struct pci_dev *isa_bridge;
465 EXPORT_SYMBOL(isa_bridge);