2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 # This program is free software; you can redistribute it and/or modify
5 # it under the terms of the GNU General Public License version 2 as
6 # published by the Free Software Foundation.
12 select ARCH_HAS_DMA_COHERENT_TO_PFN
13 select ARCH_HAS_PTE_SPECIAL
14 select ARCH_HAS_SETUP_DMA_OPS
15 select ARCH_HAS_SYNC_DMA_FOR_CPU
16 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
17 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
18 select ARCH_32BIT_OFF_T
19 select BUILDTIME_EXTABLE_SORT
20 select CLONE_BACKWARDS
22 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
23 select GENERIC_CLOCKEVENTS
24 select GENERIC_FIND_FIRST_BIT
25 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
26 select GENERIC_IRQ_SHOW
27 select GENERIC_PCI_IOMAP
28 select GENERIC_PENDING_IRQ if SMP
29 select GENERIC_SCHED_CLOCK
30 select GENERIC_SMP_IDLE_THREAD
32 select HAVE_ARCH_TRACEHOOK
33 select HAVE_DEBUG_STACKOVERFLOW
34 select HAVE_FUTEX_CMPXCHG if FUTEX
35 select HAVE_IOREMAP_PROT
36 select HAVE_KERNEL_GZIP
37 select HAVE_KERNEL_LZMA
39 select HAVE_KRETPROBES
40 select HAVE_MOD_ARCH_SPECIFIC
42 select HAVE_PERF_EVENTS
43 select HANDLE_DOMAIN_IRQ
45 select MODULES_USE_ELF_RELA
47 select OF_EARLY_FLATTREE
48 select PCI_SYSCALL if PCI
49 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
51 config ARCH_HAS_CACHE_LINE_SIZE
54 config TRACE_IRQFLAGS_SUPPORT
57 config LOCKDEP_SUPPORT
60 config SCHED_OMIT_FRAME_POINTER
66 config ARCH_DISCONTIGMEM_ENABLE
69 config ARCH_FLATMEM_ENABLE
78 config GENERIC_CALIBRATE_DELAY
81 config GENERIC_HWEIGHT
84 config STACKTRACE_SUPPORT
88 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
92 menu "ARC Architecture Configuration"
94 menu "ARC Platform/SoC/Board"
96 source "arch/arc/plat-tb10x/Kconfig"
97 source "arch/arc/plat-axs10x/Kconfig"
98 #New platform adds here
99 source "arch/arc/plat-eznps/Kconfig"
100 source "arch/arc/plat-hsdk/Kconfig"
105 prompt "ARC Instruction Set"
110 select CPU_NO_EFFICIENT_FFS
112 The original ARC ISA of ARC600/700 cores
116 select ARC_TIMERS_64BIT
118 ISA for the Next Generation ARC-HS cores
122 menu "ARC CPU Configuration"
126 default ARC_CPU_770 if ISA_ARCOMPACT
127 default ARC_CPU_HS if ISA_ARCV2
135 Support for ARC750 core
141 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
142 This core has a bunch of cool new features:
143 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
144 Shared Address Spaces (for sharing TLB entries in MMU)
145 -Caches: New Prog Model, Region Flush
146 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
154 Support for ARC HS38x Cores based on ARCv2 ISA
155 The notable features are:
156 - SMP configurations of upto 4 core with coherency
157 - Optional L2 Cache and IO-Coherency
158 - Revised Interrupt Architecture (multiple priorites, reg banks,
159 auto stack switch, auto regfile save/restore)
160 - MMUv4 (PIPT dcache, Huge Pages)
162 * 64bit load/store: LDD, STD
163 * Hardware assisted divide/remainder: DIV, REM
164 * Function prologue/epilogue: ENTER_S, LEAVE_S
165 * IRQ enable/disable: CLRI, SETI
166 * pop count: FFS, FLS
167 * SETcc, BMSKN, XBFU...
171 config CPU_BIG_ENDIAN
172 bool "Enable Big Endian Mode"
174 Build kernel for Big Endian Mode of ARC CPU
177 bool "Symmetric Multi-Processing"
178 select ARC_MCIP if ISA_ARCV2
180 This enables support for systems with more than one CPU.
185 int "Maximum number of CPUs (2-4096)"
189 config ARC_SMP_HALT_ON_RESET
190 bool "Enable Halt-on-reset boot mode"
192 In SMP configuration cores can be configured as Halt-on-reset
193 or they could all start at same time. For Halt-on-reset, non
194 masters are parked until Master kicks them so they can start of
195 at designated entry point. For other case, all jump to common
196 entry point and spin wait for Master's signal.
201 bool "ARConnect Multicore IP (MCIP) Support "
205 This IP block enables SMP in ARC-HS38 cores.
206 It provides for cross-core interrupts, multi-core debug
207 hardware semaphores, shared memory,....
210 bool "Enable Cache Support"
215 config ARC_CACHE_LINE_SHIFT
216 int "Cache Line Length (as power of 2)"
220 Starting with ARC700 4.9, Cache line length is configurable,
221 This option specifies "N", with Line-len = 2 power N
222 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
223 Linux only supports same line lengths for I and D caches.
225 config ARC_HAS_ICACHE
226 bool "Use Instruction Cache"
229 config ARC_HAS_DCACHE
230 bool "Use Data Cache"
233 config ARC_CACHE_PAGES
234 bool "Per Page Cache Control"
236 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
238 This can be used to over-ride the global I/D Cache Enable on a
239 per-page basis (but only for pages accessed via MMU such as
240 Kernel Virtual address or User Virtual Address)
241 TLB entries have a per-page Cache Enable Bit.
242 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
243 Global DISABLE + Per Page ENABLE won't work
245 config ARC_CACHE_VIPT_ALIASING
246 bool "Support VIPT Aliasing D$"
247 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
254 Single Cycle RAMS to store Fast Path Code
257 int "ICCM Size in KB"
259 depends on ARC_HAS_ICCM
264 Single Cycle RAMS to store Fast Path Data
267 int "DCCM Size in KB"
269 depends on ARC_HAS_DCCM
272 hex "DCCM map address"
274 depends on ARC_HAS_DCCM
278 default ARC_MMU_V3 if ARC_CPU_770
279 default ARC_MMU_V2 if ARC_CPU_750D
280 default ARC_MMU_V4 if ARC_CPU_HS
292 Fixed the deficiency of v1 - possible thrashing in memcpy scenario
293 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
297 depends on ARC_CPU_770
299 Introduced with ARC700 4.10: New Features
300 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
301 Shared Address Spaces (SASID)
313 prompt "MMU Page Size"
314 default ARC_PAGE_SIZE_8K
316 config ARC_PAGE_SIZE_8K
319 Choose between 8k vs 16k
321 config ARC_PAGE_SIZE_16K
323 depends on ARC_MMU_V3 || ARC_MMU_V4
325 config ARC_PAGE_SIZE_4K
327 depends on ARC_MMU_V3 || ARC_MMU_V4
332 prompt "MMU Super Page Size"
333 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
334 default ARC_HUGEPAGE_2M
336 config ARC_HUGEPAGE_2M
339 config ARC_HUGEPAGE_16M
345 int "Maximum NUMA Nodes (as a power of 2)"
346 default "0" if !DISCONTIGMEM
347 default "1" if DISCONTIGMEM
348 depends on NEED_MULTIPLE_NODES
350 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
355 config ARC_COMPACT_IRQ_LEVELS
356 bool "Setup Timer IRQ as high Priority"
357 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
360 config ARC_FPU_SAVE_RESTORE
361 bool "Enable FPU state persistence across context switch"
363 Double Precision Floating Point unit had dedicated regs which
364 need to be saved/restored across context-switch.
365 Note that ARC FPU is overly simplistic, unlike say x86, which has
366 hardware pieces to allow software to conditionally save/restore,
367 based on actual usage of FPU by a task. Thus our implemn does
368 this for all tasks in system.
376 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
378 depends on !ARC_CANT_LLSC
381 bool "Insn: SWAPE (endian-swap)"
386 config ARC_USE_UNALIGNED_MEM_ACCESS
387 bool "Enable unaligned access in HW"
389 select HAVE_EFFICIENT_UNALIGNED_ACCESS
391 The ARC HS architecture supports unaligned memory access
392 which is disabled by default. Enable unaligned access in
393 hardware and use software to use it
396 bool "Insn: 64bit LDD/STD"
398 Enable gcc to generate 64-bit load/store instructions
399 ISA mandates even/odd registers to allow encoding of two
400 dest operands with 2 possible source operands.
403 config ARC_HAS_DIV_REM
404 bool "Insn: div, divu, rem, remu"
407 config ARC_HAS_ACCL_REGS
408 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
411 Depending on the configuration, CPU can contain accumulator reg-pair
412 (also referred to as r58:r59). These can also be used by gcc as GPR so
413 kernel needs to save/restore per process
415 config ARC_IRQ_NO_AUTOSAVE
416 bool "Disable hardware autosave regfile on interrupts"
419 On HS cores, taken interrupt auto saves the regfile on stack.
420 This is programmable and can be optionally disabled in which case
421 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
425 endmenu # "ARC CPU Configuration"
427 config LINUX_LINK_BASE
428 hex "Kernel link address"
431 ARC700 divides the 32 bit phy address space into two equal halves
432 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
433 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
434 Typically Linux kernel is linked at the start of untransalted addr,
435 hence the default value of 0x8zs.
436 However some customers have peripherals mapped at this addr, so
437 Linux needs to be scooted a bit.
438 If you don't know what the above means, leave this setting alone.
439 This needs to match memory start address specified in Device Tree
441 config LINUX_RAM_BASE
442 hex "RAM base address"
443 default LINUX_LINK_BASE
445 By default Linux is linked at base of RAM. However in some special
446 cases (such as HSDK), Linux can't be linked at start of DDR, hence
450 bool "High Memory Support"
451 select ARCH_DISCONTIGMEM_ENABLE
453 With ARC 2G:2G address split, only upper 2G is directly addressable by
454 kernel. Enable this to potentially allow access to rest of 2G and PAE
458 bool "Support for the 40-bit Physical Address Extension"
461 select PHYS_ADDR_T_64BIT
463 Enable access to physical memory beyond 4G, only supported on
464 ARC cores with 40 bit Physical Addressing support
466 config ARC_KVADDR_SIZE
467 int "Kernel Virtual Address Space size (MB)"
471 The kernel address space is carved out of 256MB of translated address
472 space for catering to vmalloc, modules, pkmap, fixmap. This however may
473 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
474 this to be stretched to 512 MB (by extending into the reserved
477 config ARC_CURR_IN_REG
478 bool "Dedicate Register r25 for current_task pointer"
481 This reserved Register R25 to point to Current Task in
482 kernel mode. This saves memory access for each such access
485 config ARC_EMUL_UNALIGNED
486 bool "Emulate unaligned memory access (userspace only)"
487 select SYSCTL_ARCH_UNALIGN_NO_WARN
488 select SYSCTL_ARCH_UNALIGN_ALLOW
489 depends on ISA_ARCOMPACT
491 This enables misaligned 16 & 32 bit memory access from user space.
492 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
493 potential bugs in code
496 int "Timer Frequency"
499 config ARC_METAWARE_HLINK
500 bool "Support for Metaware debugger assisted Host access"
502 This options allows a Linux userland apps to directly access
503 host file system (open/creat/read/write etc) with help from
504 Metaware Debugger. This can come in handy for Linux-host communication
505 when there is no real usable peripheral such as EMAC.
513 config ARC_DW2_UNWIND
514 bool "Enable DWARF specific kernel stack unwind"
518 Compiles the kernel with DWARF unwind information and can be used
519 to get stack backtraces.
521 If you say Y here the resulting kernel image will be slightly larger
522 but not slower, and it will give very useful debugging information.
523 If you don't debug the kernel, you can say N, but we may not be able
524 to solve problems without frame unwind information
526 config ARC_DBG_TLB_PARANOIA
527 bool "Paranoia Checks in Low Level TLB Handlers"
531 config ARC_BUILTIN_DTB_NAME
532 string "Built in DTB"
534 Set the name of the DTB to embed in the vmlinux binary
535 Leaving it blank selects the minimal "skeleton" dtb
537 endmenu # "ARC Architecture Configuration"
539 config FORCE_MAX_ZONEORDER
540 int "Maximum zone order"
541 default "12" if ARC_HUGEPAGE_16M
544 source "kernel/power/Kconfig"