arch/arc/boot/dts/hsdk.dts

   1 /*
   2  * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Device Tree for ARC HS Development Kit
  11  */
  12 /dts-v1/;
  13
  14 #include <dt-bindings/net/ti-dp83867.h>
  15
  16 / {
  17         model = "snps,hsdk";
  18         compatible = "snps,hsdk";
  19
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         chosen {
  24                 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "snps,archs38";
  34                         reg = <0>;
  35                         clocks = <&core_clk>;
  36                 };
  37
  38                 cpu@1 {
  39                         device_type = "cpu";
  40                         compatible = "snps,archs38";
  41                         reg = <1>;
  42                         clocks = <&core_clk>;
  43                 };
  44
  45                 cpu@2 {
  46                         device_type = "cpu";
  47                         compatible = "snps,archs38";
  48                         reg = <2>;
  49                         clocks = <&core_clk>;
  50                 };
  51
  52                 cpu@3 {
  53                         device_type = "cpu";
  54                         compatible = "snps,archs38";
  55                         reg = <3>;
  56                         clocks = <&core_clk>;
  57                 };
  58         };
  59
  60         input_clk: input-clk {
  61                 #clock-cells = <0>;
  62                 compatible = "fixed-clock";
  63                 clock-frequency = <33333333>;
  64         };
  65
  66         cpu_intc: cpu-interrupt-controller {
  67                 compatible = "snps,archs-intc";
  68                 interrupt-controller;
  69                 #interrupt-cells = <1>;
  70         };
  71
  72         idu_intc: idu-interrupt-controller {
  73                 compatible = "snps,archs-idu-intc";
  74                 interrupt-controller;
  75                 #interrupt-cells = <1>;
  76                 interrupt-parent = <&cpu_intc>;
  77         };
  78
  79         arcpct: pct {
  80                 compatible = "snps,archs-pct";
  81         };
  82
  83         /* TIMER0 with interrupt for clockevent */
  84         timer {
  85                 compatible = "snps,arc-timer";
  86                 interrupts = <16>;
  87                 interrupt-parent = <&cpu_intc>;
  88                 clocks = <&core_clk>;
  89         };
  90
  91         /* 64-bit Global Free Running Counter */
  92         gfrc {
  93                 compatible = "snps,archs-timer-gfrc";
  94                 clocks = <&core_clk>;
  95         };
  96
  97         soc {
  98                 compatible = "simple-bus";
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 interrupt-parent = <&idu_intc>;
 102
 103                 ranges = <0x00000000 0xf0000000 0x10000000>;
 104
 105                 core_clk: core-clk@0 {
 106                         compatible = "snps,hsdk-core-pll-clock";
 107                         reg = <0x00 0x10>, <0x14B8 0x4>;
 108                         #clock-cells = <0>;
 109                         clocks = <&input_clk>;
 110                 };
 111
 112                 serial: serial@5000 {
 113                         compatible = "snps,dw-apb-uart";
 114                         reg = <0x5000 0x100>;
 115                         clock-frequency = <33330000>;
 116                         interrupts = <6>;
 117                         baud = <115200>;
 118                         reg-shift = <2>;
 119                         reg-io-width = <4>;
 120                 };
 121
 122                 gmacclk: gmacclk {
 123                         compatible = "fixed-clock";
 124                         clock-frequency = <400000000>;
 125                         #clock-cells = <0>;
 126                 };
 127
 128                 mmcclk_ciu: mmcclk-ciu {
 129                         compatible = "fixed-clock";
 130                         /*
 131                          * DW sdio controller has external ciu clock divider
 132                          * controlled via register in SDIO IP. Due to its
 133                          * unexpected default value (it should devide by 1
 134                          * but it devides by 8) SDIO IP uses wrong clock and
 135                          * works unstable (see STAR 9001204800)
 136                          * So add temporary fix and change clock frequency
 137                          * from 100000000 to 12500000 Hz until we fix dw sdio
 138                          * driver itself.
 139                          */
 140                         clock-frequency = <12500000>;
 141                         #clock-cells = <0>;
 142                 };
 143
 144                 mmcclk_biu: mmcclk-biu {
 145                         compatible = "fixed-clock";
 146                         clock-frequency = <400000000>;
 147                         #clock-cells = <0>;
 148                 };
 149
 150                 ethernet@8000 {
 151                         #interrupt-cells = <1>;
 152                         compatible = "snps,dwmac";
 153                         reg = <0x8000 0x2000>;
 154                         interrupts = <10>;
 155                         interrupt-names = "macirq";
 156                         phy-mode = "rgmii";
 157                         snps,pbl = <32>;
 158                         clocks = <&gmacclk>;
 159                         clock-names = "stmmaceth";
 160                         phy-handle = <&phy0>;
 161
 162                         mdio {
 163                                 #address-cells = <1>;
 164                                 #size-cells = <0>;
 165                                 compatible = "snps,dwmac-mdio";
 166                                 phy0: ethernet-phy@0 {
 167                                         reg = <0>;
 168                                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 169                                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 170                                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 171                                 };
 172                         };
 173                 };
 174
 175                 ohci@60000 {
 176                         compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
 177                         reg = <0x60000 0x100>;
 178                         interrupts = <15>;
 179                 };
 180
 181                 ehci@40000 {
 182                         compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
 183                         reg = <0x40000 0x100>;
 184                         interrupts = <15>;
 185                 };
 186
 187                 mmc@a000 {
 188                         compatible = "altr,socfpga-dw-mshc";
 189                         reg = <0xa000 0x400>;
 190                         num-slots = <1>;
 191                         fifo-depth = <16>;
 192                         card-detect-delay = <200>;
 193                         clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
 194                         clock-names = "biu", "ciu";
 195                         interrupts = <12>;
 196                         bus-width = <4>;
 197                 };
 198         };
 199
 200         memory@80000000 {
 201                 #address-cells = <1>;
 202                 #size-cells = <1>;
 203                 device_type = "memory";
 204                 reg = <0x80000000 0x40000000>;  /* 1 GiB */
 205         };
 206 };