arch/arc/plat-hsdk/platform.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ARC HSDK Platform support code
   4  *
   5  * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
   6  */
   7
   8 #include <linux/init.h>
   9 #include <linux/smp.h>
  10 #include <asm/arcregs.h>
  11 #include <asm/io.h>
  12 #include <asm/mach_desc.h>
  13
  14 #define ARC_CCM_UNUSED_ADDR     0x60000000
  15
  16 static void __init hsdk_init_per_cpu(unsigned int cpu)
  17 {
  18         /*
  19          * By default ICCM is mapped to 0x7z while this area is used for
  20          * kernel virtual mappings, so move it to currently unused area.
  21          */
  22         if (cpuinfo_arc700[cpu].iccm.sz)
  23                 write_aux_reg(ARC_REG_AUX_ICCM, ARC_CCM_UNUSED_ADDR);
  24
  25         /*
  26          * By default DCCM is mapped to 0x8z while this area is used by kernel,
  27          * so move it to currently unused area.
  28          */
  29         if (cpuinfo_arc700[cpu].dccm.sz)
  30                 write_aux_reg(ARC_REG_AUX_DCCM, ARC_CCM_UNUSED_ADDR);
  31 }
  32
  33 #define ARC_PERIPHERAL_BASE     0xf0000000
  34 #define CREG_BASE               (ARC_PERIPHERAL_BASE + 0x1000)
  35
  36 #define SDIO_BASE               (ARC_PERIPHERAL_BASE + 0xA000)
  37 #define SDIO_UHS_REG_EXT        (SDIO_BASE + 0x108)
  38 #define SDIO_UHS_REG_EXT_DIV_2  (2 << 30)
  39
  40 #define HSDK_GPIO_INTC          (ARC_PERIPHERAL_BASE + 0x3000)
  41
  42 static void __init hsdk_enable_gpio_intc_wire(void)
  43 {
  44         /*
  45          * Peripherals on CPU Card are wired to cpu intc via intermediate
  46          * DW APB GPIO blocks (mainly for debouncing)
  47          *
  48          *         ---------------------
  49          *        |  snps,archs-intc  |
  50          *        ---------------------
  51          *                  |
  52          *        ----------------------
  53          *        | snps,archs-idu-intc |
  54          *        ----------------------
  55          *         |   |     |   |    |
  56          *         | [eth] [USB]    [... other peripherals]
  57          *         |
  58          * -------------------
  59          * | snps,dw-apb-intc |
  60          * -------------------
  61          *  |      |   |   |
  62          * [Bt] [HAPS]   [... other peripherals]
  63          *
  64          * Current implementation of "irq-dw-apb-ictl" driver doesn't work well
  65          * with stacked INTCs. In particular problem happens if its master INTC
  66          * not yet instantiated. See discussion here -
  67          * https://lkml.org/lkml/2015/3/4/755
  68          *
  69          * So setup the first gpio block as a passive pass thru and hide it from
  70          * DT hardware topology - connect intc directly to cpu intc
  71          * The GPIO "wire" needs to be init nevertheless (here)
  72          *
  73          * One side adv is that peripheral interrupt handling avoids one nested
  74          * intc ISR hop
  75          *
  76          * According to HSDK User's Manual [1], "Table 2 Interrupt Mapping"
  77          * we have the following GPIO input lines used as sources of interrupt:
  78          * - GPIO[0] - Bluetooth interrupt of RS9113 module
  79          * - GPIO[2] - HAPS interrupt (on HapsTrak 3 connector)
  80          * - GPIO[3] - Audio codec (MAX9880A) interrupt
  81          * - GPIO[8-23] - Available on Arduino and PMOD_x headers
  82          * For now there's no use of Arduino and PMOD_x headers in Linux
  83          * use-case so we only enable lines 0, 2 and 3.
  84          *
  85          * [1] https://github.com/foss-for-synopsys-dwc-arc-processors/ARC-Development-Systems-Forum/wiki/docs/ARC_HSDK_User_Guide.pdf
  86          */
  87 #define GPIO_INTEN              (HSDK_GPIO_INTC + 0x30)
  88 #define GPIO_INTMASK            (HSDK_GPIO_INTC + 0x34)
  89 #define GPIO_INTTYPE_LEVEL      (HSDK_GPIO_INTC + 0x38)
  90 #define GPIO_INT_POLARITY       (HSDK_GPIO_INTC + 0x3c)
  91 #define GPIO_INT_CONNECTED_MASK 0x0d
  92
  93         iowrite32(0xffffffff, (void __iomem *) GPIO_INTMASK);
  94         iowrite32(~GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTMASK);
  95         iowrite32(0x00000000, (void __iomem *) GPIO_INTTYPE_LEVEL);
  96         iowrite32(0xffffffff, (void __iomem *) GPIO_INT_POLARITY);
  97         iowrite32(GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTEN);
  98 }
  99
 100 enum hsdk_axi_masters {
 101         M_HS_CORE = 0,
 102         M_HS_RTT,
 103         M_AXI_TUN,
 104         M_HDMI_VIDEO,
 105         M_HDMI_AUDIO,
 106         M_USB_HOST,
 107         M_ETHERNET,
 108         M_SDIO,
 109         M_GPU,
 110         M_DMAC_0,
 111         M_DMAC_1,
 112         M_DVFS
 113 };
 114
 115 #define UPDATE_VAL      1
 116
 117 /*
 118  * This is modified configuration of AXI bridge. Default settings
 119  * are specified in "Table 111 CREG Address Decoder register reset values".
 120  *
 121  * AXI_M_m_SLV{0|1} - Slave Select register for master 'm'.
 122  * Possible slaves are:
 123  *  - 0  => no slave selected
 124  *  - 1  => DDR controller port #1
 125  *  - 2  => SRAM controller
 126  *  - 3  => AXI tunnel
 127  *  - 4  => EBI controller
 128  *  - 5  => ROM controller
 129  *  - 6  => AXI2APB bridge
 130  *  - 7  => DDR controller port #2
 131  *  - 8  => DDR controller port #3
 132  *  - 9  => HS38x4 IOC
 133  *  - 10 => HS38x4 DMI
 134  * AXI_M_m_OFFSET{0|1} - Addr Offset register for master 'm'
 135  *
 136  * Please read ARC HS Development IC Specification, section 17.2 for more
 137  * information about apertures configuration.
 138  *
 139  * m    master          AXI_M_m_SLV0    AXI_M_m_SLV1    AXI_M_m_OFFSET0 AXI_M_m_OFFSET1
 140  * 0    HS (CBU)        0x11111111      0x63111111      0xFEDCBA98      0x0E543210
 141  * 1    HS (RTT)        0x77777777      0x77777777      0xFEDCBA98      0x76543210
 142  * 2    AXI Tunnel      0x88888888      0x88888888      0xFEDCBA98      0x76543210
 143  * 3    HDMI-VIDEO      0x77777777      0x77777777      0xFEDCBA98      0x76543210
 144  * 4    HDMI-ADUIO      0x77777777      0x77777777      0xFEDCBA98      0x76543210
 145  * 5    USB-HOST        0x77777777      0x77999999      0xFEDCBA98      0x76DCBA98
 146  * 6    ETHERNET        0x77777777      0x77999999      0xFEDCBA98      0x76DCBA98
 147  * 7    SDIO            0x77777777      0x77999999      0xFEDCBA98      0x76DCBA98
 148  * 8    GPU             0x77777777      0x77777777      0xFEDCBA98      0x76543210
 149  * 9    DMAC (port #1)  0x77777777      0x77777777      0xFEDCBA98      0x76543210
 150  * 10   DMAC (port #2)  0x77777777      0x77777777      0xFEDCBA98      0x76543210
 151  * 11   DVFS            0x00000000      0x60000000      0x00000000      0x00000000
 152  */
 153
 154 #define CREG_AXI_M_SLV0(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m)))
 155 #define CREG_AXI_M_SLV1(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x04))
 156 #define CREG_AXI_M_OFT0(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x08))
 157 #define CREG_AXI_M_OFT1(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x0C))
 158 #define CREG_AXI_M_UPDT(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x14))
 159
 160 #define CREG_AXI_M_HS_CORE_BOOT ((void __iomem *)(CREG_BASE + 0x010))
 161
 162 #define CREG_PAE                ((void __iomem *)(CREG_BASE + 0x180))
 163 #define CREG_PAE_UPDT           ((void __iomem *)(CREG_BASE + 0x194))
 164
 165 static void __init hsdk_init_memory_bridge(void)
 166 {
 167         u32 reg;
 168
 169         /*
 170          * M_HS_CORE has one unique register - BOOT.
 171          * We need to clean boot mirror (BOOT[1:0]) bits in them to avoid first
 172          * aperture to be masked by 'boot mirror'.
 173          */
 174         reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3);
 175         writel(reg, CREG_AXI_M_HS_CORE_BOOT);
 176         writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));
 177         writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
 178         writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));
 179         writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
 180         writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
 181
 182         writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));
 183         writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));
 184         writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));
 185         writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));
 186         writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));
 187
 188         writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));
 189         writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));
 190         writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));
 191         writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));
 192         writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));
 193
 194         writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));
 195         writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));
 196         writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));
 197         writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));
 198         writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));
 199
 200         writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));
 201         writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));
 202         writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));
 203         writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));
 204         writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));
 205
 206         writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));
 207         writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));
 208         writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));
 209         writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));
 210         writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
 211
 212         writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));
 213         writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));
 214         writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));
 215         writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));
 216         writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
 217
 218         writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));
 219         writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));
 220         writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));
 221         writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));
 222         writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
 223
 224         writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
 225         writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
 226         writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
 227         writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
 228         writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
 229
 230         writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
 231         writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0));
 232         writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
 233         writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0));
 234         writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
 235
 236         writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
 237         writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1));
 238         writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
 239         writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1));
 240         writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
 241
 242         writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
 243         writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
 244         writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
 245         writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
 246         writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
 247
 248         /*
 249          * PAE remapping for DMA clients does not work due to an RTL bug, so
 250          * CREG_PAE register must be programmed to all zeroes, otherwise it
 251          * will cause problems with DMA to/from peripherals even if PAE40 is
 252          * not used.
 253          */
 254         writel(0x00000000, CREG_PAE);
 255         writel(UPDATE_VAL, CREG_PAE_UPDT);
 256 }
 257
 258 static void __init hsdk_init_early(void)
 259 {
 260         hsdk_init_memory_bridge();
 261
 262         /*
 263          * Switch SDIO external ciu clock divider from default div-by-8 to
 264          * minimum possible div-by-2.
 265          */
 266         iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
 267
 268         hsdk_enable_gpio_intc_wire();
 269 }
 270
 271 static const char *hsdk_compat[] __initconst = {
 272         "snps,hsdk",
 273         NULL,
 274 };
 275
 276 MACHINE_START(SIMULATION, "hsdk")
 277         .dt_compat      = hsdk_compat,
 278         .init_early     = hsdk_init_early,
 279         .init_per_cpu   = hsdk_init_per_cpu,
 280 MACHINE_END