4 select ARCH_CLOCKSOURCE_DATA
5 select ARCH_HAS_DEBUG_VIRTUAL
6 select ARCH_HAS_DEVMEM_IS_ALLOWED
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_SET_MEMORY
9 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
10 select ARCH_HAS_STRICT_MODULE_RWX if MMU
11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
12 select ARCH_HAVE_CUSTOM_GPIO_H
13 select ARCH_HAS_GCOV_PROFILE_ALL
14 select ARCH_MIGHT_HAVE_PC_PARPORT
15 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
16 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
17 select ARCH_SUPPORTS_ATOMIC_RMW
18 select ARCH_USE_BUILTIN_BSWAP
19 select ARCH_USE_CMPXCHG_LOCKREF
20 select ARCH_WANT_IPC_PARSE_VERSION
21 select BUILDTIME_EXTABLE_SORT if MMU
22 select CLONE_BACKWARDS
23 select CPU_PM if (SUSPEND || CPU_IDLE)
24 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
26 select EDAC_ATOMIC_SCRUB
27 select GENERIC_ALLOCATOR
28 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
29 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
30 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
31 select GENERIC_CPU_AUTOPROBE
32 select GENERIC_EARLY_IOREMAP
33 select GENERIC_IDLE_POLL_SETUP
34 select GENERIC_IRQ_PROBE
35 select GENERIC_IRQ_SHOW
36 select GENERIC_IRQ_SHOW_LEVEL
37 select GENERIC_PCI_IOMAP
38 select GENERIC_SCHED_CLOCK
39 select GENERIC_SMP_IDLE_THREAD
40 select GENERIC_STRNCPY_FROM_USER
41 select GENERIC_STRNLEN_USER
42 select HANDLE_DOMAIN_IRQ
43 select HARDIRQS_SW_RESEND
44 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
45 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
46 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
47 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
48 select HAVE_ARCH_MMAP_RND_BITS if MMU
49 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
50 select HAVE_ARCH_TRACEHOOK
51 select HAVE_ARM_SMCCC if CPU_V7
53 select HAVE_CC_STACKPROTECTOR
54 select HAVE_CONTEXT_TRACKING
55 select HAVE_C_RECORDMCOUNT
56 select HAVE_DEBUG_KMEMLEAK
57 select HAVE_DMA_API_DEBUG
58 select HAVE_DMA_CONTIGUOUS if MMU
59 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
60 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
61 select HAVE_EXIT_THREAD
62 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
63 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
64 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
65 select HAVE_GCC_PLUGINS
66 select HAVE_GENERIC_DMA_COHERENT
67 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
68 select HAVE_IDE if PCI || ISA || PCMCIA
69 select HAVE_IRQ_TIME_ACCOUNTING
70 select HAVE_KERNEL_GZIP
71 select HAVE_KERNEL_LZ4
72 select HAVE_KERNEL_LZMA
73 select HAVE_KERNEL_LZO
75 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
76 select HAVE_KRETPROBES if (HAVE_KPROBES)
78 select HAVE_MOD_ARCH_SPECIFIC
80 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
81 select HAVE_OPTPROBES if !THUMB2_KERNEL
82 select HAVE_PERF_EVENTS
84 select HAVE_PERF_USER_STACK_DUMP
85 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
86 select HAVE_REGS_AND_STACK_ACCESS_API
87 select HAVE_SYSCALL_TRACEPOINTS
89 select HAVE_VIRT_CPU_ACCOUNTING_GEN
90 select IRQ_FORCED_THREADING
91 select MODULES_USE_ELF_REL
93 select OF_EARLY_FLATTREE if OF
94 select OF_RESERVED_MEM if OF
96 select OLD_SIGSUSPEND3
97 select PERF_USE_VMALLOC
99 select SYS_SUPPORTS_APM_EMULATION
100 # Above selects are sorted alphabetically; please add new ones
101 # according to that. Thanks.
103 The ARM series is a line of low-power-consumption RISC chip designs
104 licensed by ARM Ltd and targeted at embedded applications and
105 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
106 manufactured, but legacy ARM-based PC hardware remains popular in
107 Europe. There is an ARM Linux project with a web page at
108 <http://www.arm.linux.org.uk/>.
110 config ARM_HAS_SG_CHAIN
111 select ARCH_HAS_SG_CHAIN
114 config NEED_SG_DMA_LENGTH
117 config ARM_DMA_USE_IOMMU
119 select ARM_HAS_SG_CHAIN
120 select NEED_SG_DMA_LENGTH
124 config ARM_DMA_IOMMU_ALIGNMENT
125 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
129 DMA mapping framework by default aligns all buffers to the smallest
130 PAGE_SIZE order which is greater than or equal to the requested buffer
131 size. This works well for buffers up to a few hundreds kilobytes, but
132 for larger buffers it just a waste of address space. Drivers which has
133 relatively small addressing window (like 64Mib) might run out of
134 virtual space with just a few allocations.
136 With this parameter you can specify the maximum PAGE_SIZE order for
137 DMA IOMMU buffers. Larger buffers will be aligned only to this
138 specified order. The order is expressed as a power of two multiplied
143 config MIGHT_HAVE_PCI
146 config SYS_SUPPORTS_APM_EMULATION
151 select GENERIC_ALLOCATOR
162 The Extended Industry Standard Architecture (EISA) bus was
163 developed as an open alternative to the IBM MicroChannel bus.
165 The EISA bus provided some of the features of the IBM MicroChannel
166 bus while maintaining backward compatibility with cards made for
167 the older ISA bus. The EISA bus saw limited use between 1988 and
168 1995 when it was made obsolete by the PCI bus.
170 Say Y here if you are building a kernel for an EISA-based machine.
177 config STACKTRACE_SUPPORT
181 config LOCKDEP_SUPPORT
185 config TRACE_IRQFLAGS_SUPPORT
189 config RWSEM_XCHGADD_ALGORITHM
193 config ARCH_HAS_ILOG2_U32
196 config ARCH_HAS_ILOG2_U64
199 config ARCH_HAS_BANDGAP
202 config FIX_EARLYCON_MEM
205 config GENERIC_HWEIGHT
209 config GENERIC_CALIBRATE_DELAY
213 config ARCH_MAY_HAVE_PC_FDC
219 config NEED_DMA_MAP_STATE
222 config ARCH_SUPPORTS_UPROBES
225 config ARCH_HAS_DMA_SET_COHERENT_MASK
228 config GENERIC_ISA_DMA
234 config NEED_RET_TO_USER
242 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
243 default DRAM_BASE if REMAP_VECTORS_TO_RAM
246 The base address of exception vectors. This must be two pages
249 config ARM_PATCH_PHYS_VIRT
250 bool "Patch physical to virtual translations at runtime" if EMBEDDED
252 depends on !XIP_KERNEL && MMU
254 Patch phys-to-virt and virt-to-phys translation functions at
255 boot and module load time according to the position of the
256 kernel in system memory.
258 This can only be used with non-XIP MMU kernels where the base
259 of physical memory is at a 16MB boundary.
261 Only disable this option if you know that you do not require
262 this feature (eg, building a kernel for a single machine) and
263 you need to shrink the kernel to the minimal size.
265 config NEED_MACH_IO_H
268 Select this when mach/io.h is required to provide special
269 definitions for this platform. The need for mach/io.h should
270 be avoided when possible.
272 config NEED_MACH_MEMORY_H
275 Select this when mach/memory.h is required to provide special
276 definitions for this platform. The need for mach/memory.h should
277 be avoided when possible.
280 hex "Physical address of main memory" if MMU
281 depends on !ARM_PATCH_PHYS_VIRT
282 default DRAM_BASE if !MMU
283 default 0x00000000 if ARCH_EBSA110 || \
289 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
290 default 0x20000000 if ARCH_S5PV210
291 default 0xc0000000 if ARCH_SA1100
293 Please provide the physical address corresponding to the
294 location of main memory in your system.
300 config PGTABLE_LEVELS
302 default 3 if ARM_LPAE
305 source "init/Kconfig"
307 source "kernel/Kconfig.freezer"
312 bool "MMU-based Paged Memory Management Support"
315 Select if you want MMU-based virtualised addressing space
316 support by paged memory management. If unsure, say 'Y'.
318 config ARCH_MMAP_RND_BITS_MIN
321 config ARCH_MMAP_RND_BITS_MAX
322 default 14 if PAGE_OFFSET=0x40000000
323 default 15 if PAGE_OFFSET=0x80000000
327 # The "ARM system type" choice list is ordered alphabetically by option
328 # text. Please add new entries in the option alphabetic order.
331 prompt "ARM system type"
332 default ARM_SINGLE_ARMV7M if !MMU
333 default ARCH_MULTIPLATFORM if MMU
335 config ARCH_MULTIPLATFORM
336 bool "Allow multiple platforms to be selected"
338 select ARM_HAS_SG_CHAIN
339 select ARM_PATCH_PHYS_VIRT
343 select GENERIC_CLOCKEVENTS
344 select MIGHT_HAVE_PCI
345 select MULTI_IRQ_HANDLER
346 select PCI_DOMAINS if PCI
350 config ARM_SINGLE_ARMV7M
351 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
358 select GENERIC_CLOCKEVENTS
365 select ARCH_USES_GETTIMEOFFSET
368 select NEED_MACH_IO_H
369 select NEED_MACH_MEMORY_H
372 This is an evaluation board for the StrongARM processor available
373 from Digital. It has limited hardware on-board, including an
374 Ethernet interface, two PCMCIA sockets, two serial ports and a
379 select ARCH_HAS_HOLES_MEMORYMODEL
381 select ARM_PATCH_PHYS_VIRT
387 select GENERIC_CLOCKEVENTS
390 This enables support for the Cirrus EP93xx series of CPUs.
392 config ARCH_FOOTBRIDGE
396 select GENERIC_CLOCKEVENTS
398 select NEED_MACH_IO_H if !MMU
399 select NEED_MACH_MEMORY_H
401 Support for systems based on the DC21285 companion chip
402 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
405 bool "Hilscher NetX based"
409 select GENERIC_CLOCKEVENTS
411 This enables support for systems based on the Hilscher NetX Soc
417 select NEED_MACH_MEMORY_H
418 select NEED_RET_TO_USER
424 Support for Intel's IOP13XX (XScale) family of processors.
432 select NEED_RET_TO_USER
436 Support for Intel's 80219 and IOP32X (XScale) family of
445 select NEED_RET_TO_USER
449 Support for Intel's IOP33X (XScale) family of processors.
454 select ARCH_HAS_DMA_SET_COHERENT_MASK
455 select ARCH_SUPPORTS_BIG_ENDIAN
458 select DMABOUNCE if PCI
459 select GENERIC_CLOCKEVENTS
461 select MIGHT_HAVE_PCI
462 select NEED_MACH_IO_H
463 select USB_EHCI_BIG_ENDIAN_DESC
464 select USB_EHCI_BIG_ENDIAN_MMIO
466 Support for Intel's IXP4XX (XScale) family of processors.
471 select GENERIC_CLOCKEVENTS
473 select MIGHT_HAVE_PCI
474 select MULTI_IRQ_HANDLER
478 select PLAT_ORION_LEGACY
480 select PM_GENERIC_DOMAINS if PM
482 Support for the Marvell Dove SoC 88AP510
485 bool "Micrel/Kendin KS8695"
488 select GENERIC_CLOCKEVENTS
490 select NEED_MACH_MEMORY_H
492 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
493 System-on-Chip devices.
496 bool "Nuvoton W90X900 CPU"
500 select GENERIC_CLOCKEVENTS
503 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
504 At present, the w90x900 has been renamed nuc900, regarding
505 the ARM series product line, you can login the following
506 link address to know more.
508 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
509 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
515 select CLKSRC_LPC32XX
518 select GENERIC_CLOCKEVENTS
520 select MULTI_IRQ_HANDLER
524 Support for the NXP LPC32XX family of processors
527 bool "PXA2xx/PXA3xx-based"
530 select ARM_CPU_SUSPEND if PM
537 select CPU_XSCALE if !CPU_XSC3
538 select GENERIC_CLOCKEVENTS
543 select MULTI_IRQ_HANDLER
547 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
553 select ARCH_MAY_HAVE_PC_FDC
554 select ARCH_SPARSEMEM_ENABLE
555 select ARCH_USES_GETTIMEOFFSET
559 select HAVE_PATA_PLATFORM
561 select NEED_MACH_IO_H
562 select NEED_MACH_MEMORY_H
565 On the Acorn Risc-PC, Linux can support the internal IDE disk and
566 CD-ROM interface, serial and parallel port, and the floppy drive.
571 select ARCH_SPARSEMEM_ENABLE
575 select TIMER_OF if OF
578 select GENERIC_CLOCKEVENTS
583 select MULTI_IRQ_HANDLER
584 select NEED_MACH_MEMORY_H
587 Support for StrongARM 11x0 based boards.
590 bool "Samsung S3C24XX SoCs"
593 select CLKSRC_SAMSUNG_PWM
594 select GENERIC_CLOCKEVENTS
597 select HAVE_S3C2410_I2C if I2C
598 select HAVE_S3C2410_WATCHDOG if WATCHDOG
599 select HAVE_S3C_RTC if RTC_CLASS
600 select MULTI_IRQ_HANDLER
601 select NEED_MACH_IO_H
604 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
605 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
606 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
607 Samsung SMDK2410 development board (and derivatives).
611 select ARCH_HAS_HOLES_MEMORYMODEL
614 select GENERIC_ALLOCATOR
615 select GENERIC_CLOCKEVENTS
616 select GENERIC_IRQ_CHIP
622 Support for TI's DaVinci platform.
627 select ARCH_HAS_HOLES_MEMORYMODEL
631 select GENERIC_CLOCKEVENTS
632 select GENERIC_IRQ_CHIP
636 select MULTI_IRQ_HANDLER
637 select NEED_MACH_IO_H if PCCARD
638 select NEED_MACH_MEMORY_H
641 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
645 menu "Multiple platform selection"
646 depends on ARCH_MULTIPLATFORM
648 comment "CPU Core family selection"
651 bool "ARMv4 based platforms (FA526)"
652 depends on !ARCH_MULTI_V6_V7
653 select ARCH_MULTI_V4_V5
656 config ARCH_MULTI_V4T
657 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
658 depends on !ARCH_MULTI_V6_V7
659 select ARCH_MULTI_V4_V5
660 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
661 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
662 CPU_ARM925T || CPU_ARM940T)
665 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
666 depends on !ARCH_MULTI_V6_V7
667 select ARCH_MULTI_V4_V5
668 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
669 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
670 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
672 config ARCH_MULTI_V4_V5
676 bool "ARMv6 based platforms (ARM11)"
677 select ARCH_MULTI_V6_V7
681 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
683 select ARCH_MULTI_V6_V7
687 config ARCH_MULTI_V6_V7
689 select MIGHT_HAVE_CACHE_L2X0
691 config ARCH_MULTI_CPU_AUTO
692 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
698 bool "Dummy Virtual Machine"
699 depends on ARCH_MULTI_V7
702 select ARM_GIC_V2M if PCI
704 select ARM_GIC_V3_ITS if PCI
706 select HAVE_ARM_ARCH_TIMER
709 # This is sorted alphabetically by mach-* pathname. However, plat-*
710 # Kconfigs may be included either alphabetically (according to the
711 # plat- suffix) or along side the corresponding mach-* source.
713 source "arch/arm/mach-mvebu/Kconfig"
715 source "arch/arm/mach-actions/Kconfig"
717 source "arch/arm/mach-alpine/Kconfig"
719 source "arch/arm/mach-artpec/Kconfig"
721 source "arch/arm/mach-asm9260/Kconfig"
723 source "arch/arm/mach-at91/Kconfig"
725 source "arch/arm/mach-axxia/Kconfig"
727 source "arch/arm/mach-bcm/Kconfig"
729 source "arch/arm/mach-berlin/Kconfig"
731 source "arch/arm/mach-clps711x/Kconfig"
733 source "arch/arm/mach-cns3xxx/Kconfig"
735 source "arch/arm/mach-davinci/Kconfig"
737 source "arch/arm/mach-digicolor/Kconfig"
739 source "arch/arm/mach-dove/Kconfig"
741 source "arch/arm/mach-ep93xx/Kconfig"
743 source "arch/arm/mach-footbridge/Kconfig"
745 source "arch/arm/mach-gemini/Kconfig"
747 source "arch/arm/mach-highbank/Kconfig"
749 source "arch/arm/mach-hisi/Kconfig"
751 source "arch/arm/mach-integrator/Kconfig"
753 source "arch/arm/mach-iop32x/Kconfig"
755 source "arch/arm/mach-iop33x/Kconfig"
757 source "arch/arm/mach-iop13xx/Kconfig"
759 source "arch/arm/mach-ixp4xx/Kconfig"
761 source "arch/arm/mach-keystone/Kconfig"
763 source "arch/arm/mach-ks8695/Kconfig"
765 source "arch/arm/mach-meson/Kconfig"
767 source "arch/arm/mach-moxart/Kconfig"
769 source "arch/arm/mach-aspeed/Kconfig"
771 source "arch/arm/mach-mv78xx0/Kconfig"
773 source "arch/arm/mach-imx/Kconfig"
775 source "arch/arm/mach-mediatek/Kconfig"
777 source "arch/arm/mach-mxs/Kconfig"
779 source "arch/arm/mach-netx/Kconfig"
781 source "arch/arm/mach-nomadik/Kconfig"
783 source "arch/arm/mach-nspire/Kconfig"
785 source "arch/arm/plat-omap/Kconfig"
787 source "arch/arm/mach-omap1/Kconfig"
789 source "arch/arm/mach-omap2/Kconfig"
791 source "arch/arm/mach-orion5x/Kconfig"
793 source "arch/arm/mach-picoxcell/Kconfig"
795 source "arch/arm/mach-pxa/Kconfig"
796 source "arch/arm/plat-pxa/Kconfig"
798 source "arch/arm/mach-mmp/Kconfig"
800 source "arch/arm/mach-oxnas/Kconfig"
802 source "arch/arm/mach-qcom/Kconfig"
804 source "arch/arm/mach-realview/Kconfig"
806 source "arch/arm/mach-rockchip/Kconfig"
808 source "arch/arm/mach-sa1100/Kconfig"
810 source "arch/arm/mach-socfpga/Kconfig"
812 source "arch/arm/mach-spear/Kconfig"
814 source "arch/arm/mach-sti/Kconfig"
816 source "arch/arm/mach-stm32/Kconfig"
818 source "arch/arm/mach-s3c24xx/Kconfig"
820 source "arch/arm/mach-s3c64xx/Kconfig"
822 source "arch/arm/mach-s5pv210/Kconfig"
824 source "arch/arm/mach-exynos/Kconfig"
825 source "arch/arm/plat-samsung/Kconfig"
827 source "arch/arm/mach-shmobile/Kconfig"
829 source "arch/arm/mach-sunxi/Kconfig"
831 source "arch/arm/mach-prima2/Kconfig"
833 source "arch/arm/mach-tango/Kconfig"
835 source "arch/arm/mach-tegra/Kconfig"
837 source "arch/arm/mach-u300/Kconfig"
839 source "arch/arm/mach-uniphier/Kconfig"
841 source "arch/arm/mach-ux500/Kconfig"
843 source "arch/arm/mach-versatile/Kconfig"
845 source "arch/arm/mach-vexpress/Kconfig"
846 source "arch/arm/plat-versatile/Kconfig"
848 source "arch/arm/mach-vt8500/Kconfig"
850 source "arch/arm/mach-w90x900/Kconfig"
852 source "arch/arm/mach-zx/Kconfig"
854 source "arch/arm/mach-zynq/Kconfig"
856 # ARMv7-M architecture
858 bool "Energy Micro efm32"
859 depends on ARM_SINGLE_ARMV7M
862 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
866 bool "NXP LPC18xx/LPC43xx"
867 depends on ARM_SINGLE_ARMV7M
868 select ARCH_HAS_RESET_CONTROLLER
870 select CLKSRC_LPC32XX
873 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
874 high performance microcontrollers.
877 bool "ARM MPS2 platform"
878 depends on ARM_SINGLE_ARMV7M
882 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
883 with a range of available cores like Cortex-M3/M4/M7.
885 Please, note that depends which Application Note is used memory map
886 for the platform may vary, so adjustment of RAM base might be needed.
888 # Definitions to make life easier
894 select GENERIC_CLOCKEVENTS
900 select GENERIC_IRQ_CHIP
903 config PLAT_ORION_LEGACY
910 config PLAT_VERSATILE
913 source "arch/arm/firmware/Kconfig"
915 source arch/arm/mm/Kconfig
918 bool "Enable iWMMXt support"
919 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
920 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
922 Enable support for iWMMXt context switching at run time if
923 running on a CPU that supports it.
925 config MULTI_IRQ_HANDLER
928 Allow each machine to specify it's own IRQ handler at run time.
931 source "arch/arm/Kconfig-nommu"
934 config PJ4B_ERRATA_4742
935 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
936 depends on CPU_PJ4B && MACH_ARMADA_370
939 When coming out of either a Wait for Interrupt (WFI) or a Wait for
940 Event (WFE) IDLE states, a specific timing sensitivity exists between
941 the retiring WFI/WFE instructions and the newly issued subsequent
942 instructions. This sensitivity can result in a CPU hang scenario.
944 The software must insert either a Data Synchronization Barrier (DSB)
945 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
948 config ARM_ERRATA_326103
949 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
952 Executing a SWP instruction to read-only memory does not set bit 11
953 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
954 treat the access as a read, preventing a COW from occurring and
955 causing the faulting task to livelock.
957 config ARM_ERRATA_411920
958 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
959 depends on CPU_V6 || CPU_V6K
961 Invalidation of the Instruction Cache operation can
962 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
963 It does not affect the MPCore. This option enables the ARM Ltd.
964 recommended workaround.
966 config ARM_ERRATA_430973
967 bool "ARM errata: Stale prediction on replaced interworking branch"
970 This option enables the workaround for the 430973 Cortex-A8
971 r1p* erratum. If a code sequence containing an ARM/Thumb
972 interworking branch is replaced with another code sequence at the
973 same virtual address, whether due to self-modifying code or virtual
974 to physical address re-mapping, Cortex-A8 does not recover from the
975 stale interworking branch prediction. This results in Cortex-A8
976 executing the new code sequence in the incorrect ARM or Thumb state.
977 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
978 and also flushes the branch target cache at every context switch.
979 Note that setting specific bits in the ACTLR register may not be
980 available in non-secure mode.
982 config ARM_ERRATA_458693
983 bool "ARM errata: Processor deadlock when a false hazard is created"
985 depends on !ARCH_MULTIPLATFORM
987 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
988 erratum. For very specific sequences of memory operations, it is
989 possible for a hazard condition intended for a cache line to instead
990 be incorrectly associated with a different cache line. This false
991 hazard might then cause a processor deadlock. The workaround enables
992 the L1 caching of the NEON accesses and disables the PLD instruction
993 in the ACTLR register. Note that setting specific bits in the ACTLR
994 register may not be available in non-secure mode.
996 config ARM_ERRATA_460075
997 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
999 depends on !ARCH_MULTIPLATFORM
1001 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1002 erratum. Any asynchronous access to the L2 cache may encounter a
1003 situation in which recent store transactions to the L2 cache are lost
1004 and overwritten with stale memory contents from external memory. The
1005 workaround disables the write-allocate mode for the L2 cache via the
1006 ACTLR register. Note that setting specific bits in the ACTLR register
1007 may not be available in non-secure mode.
1009 config ARM_ERRATA_742230
1010 bool "ARM errata: DMB operation may be faulty"
1011 depends on CPU_V7 && SMP
1012 depends on !ARCH_MULTIPLATFORM
1014 This option enables the workaround for the 742230 Cortex-A9
1015 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1016 between two write operations may not ensure the correct visibility
1017 ordering of the two writes. This workaround sets a specific bit in
1018 the diagnostic register of the Cortex-A9 which causes the DMB
1019 instruction to behave as a DSB, ensuring the correct behaviour of
1022 config ARM_ERRATA_742231
1023 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1024 depends on CPU_V7 && SMP
1025 depends on !ARCH_MULTIPLATFORM
1027 This option enables the workaround for the 742231 Cortex-A9
1028 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1029 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1030 accessing some data located in the same cache line, may get corrupted
1031 data due to bad handling of the address hazard when the line gets
1032 replaced from one of the CPUs at the same time as another CPU is
1033 accessing it. This workaround sets specific bits in the diagnostic
1034 register of the Cortex-A9 which reduces the linefill issuing
1035 capabilities of the processor.
1037 config ARM_ERRATA_643719
1038 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1039 depends on CPU_V7 && SMP
1042 This option enables the workaround for the 643719 Cortex-A9 (prior to
1043 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1044 register returns zero when it should return one. The workaround
1045 corrects this value, ensuring cache maintenance operations which use
1046 it behave as intended and avoiding data corruption.
1048 config ARM_ERRATA_720789
1049 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1052 This option enables the workaround for the 720789 Cortex-A9 (prior to
1053 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1054 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1055 As a consequence of this erratum, some TLB entries which should be
1056 invalidated are not, resulting in an incoherency in the system page
1057 tables. The workaround changes the TLB flushing routines to invalidate
1058 entries regardless of the ASID.
1060 config ARM_ERRATA_743622
1061 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1063 depends on !ARCH_MULTIPLATFORM
1065 This option enables the workaround for the 743622 Cortex-A9
1066 (r2p*) erratum. Under very rare conditions, a faulty
1067 optimisation in the Cortex-A9 Store Buffer may lead to data
1068 corruption. This workaround sets a specific bit in the diagnostic
1069 register of the Cortex-A9 which disables the Store Buffer
1070 optimisation, preventing the defect from occurring. This has no
1071 visible impact on the overall performance or power consumption of the
1074 config ARM_ERRATA_751472
1075 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1077 depends on !ARCH_MULTIPLATFORM
1079 This option enables the workaround for the 751472 Cortex-A9 (prior
1080 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1081 completion of a following broadcasted operation if the second
1082 operation is received by a CPU before the ICIALLUIS has completed,
1083 potentially leading to corrupted entries in the cache or TLB.
1085 config ARM_ERRATA_754322
1086 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1089 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1090 r3p*) erratum. A speculative memory access may cause a page table walk
1091 which starts prior to an ASID switch but completes afterwards. This
1092 can populate the micro-TLB with a stale entry which may be hit with
1093 the new ASID. This workaround places two dsb instructions in the mm
1094 switching code so that no page table walks can cross the ASID switch.
1096 config ARM_ERRATA_754327
1097 bool "ARM errata: no automatic Store Buffer drain"
1098 depends on CPU_V7 && SMP
1100 This option enables the workaround for the 754327 Cortex-A9 (prior to
1101 r2p0) erratum. The Store Buffer does not have any automatic draining
1102 mechanism and therefore a livelock may occur if an external agent
1103 continuously polls a memory location waiting to observe an update.
1104 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1105 written polling loops from denying visibility of updates to memory.
1107 config ARM_ERRATA_364296
1108 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1111 This options enables the workaround for the 364296 ARM1136
1112 r0p2 erratum (possible cache data corruption with
1113 hit-under-miss enabled). It sets the undocumented bit 31 in
1114 the auxiliary control register and the FI bit in the control
1115 register, thus disabling hit-under-miss without putting the
1116 processor into full low interrupt latency mode. ARM11MPCore
1119 config ARM_ERRATA_764369
1120 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1121 depends on CPU_V7 && SMP
1123 This option enables the workaround for erratum 764369
1124 affecting Cortex-A9 MPCore with two or more processors (all
1125 current revisions). Under certain timing circumstances, a data
1126 cache line maintenance operation by MVA targeting an Inner
1127 Shareable memory region may fail to proceed up to either the
1128 Point of Coherency or to the Point of Unification of the
1129 system. This workaround adds a DSB instruction before the
1130 relevant cache maintenance functions and sets a specific bit
1131 in the diagnostic control register of the SCU.
1133 config ARM_ERRATA_775420
1134 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1137 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1138 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1139 operation aborts with MMU exception, it might cause the processor
1140 to deadlock. This workaround puts DSB before executing ISB if
1141 an abort may occur on cache maintenance.
1143 config ARM_ERRATA_798181
1144 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1145 depends on CPU_V7 && SMP
1147 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1148 adequately shooting down all use of the old entries. This
1149 option enables the Linux kernel workaround for this erratum
1150 which sends an IPI to the CPUs that are running the same ASID
1151 as the one being invalidated.
1153 config ARM_ERRATA_773022
1154 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1157 This option enables the workaround for the 773022 Cortex-A15
1158 (up to r0p4) erratum. In certain rare sequences of code, the
1159 loop buffer may deliver incorrect instructions. This
1160 workaround disables the loop buffer to avoid the erratum.
1162 config ARM_ERRATA_818325_852422
1163 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1166 This option enables the workaround for:
1167 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1168 instruction might deadlock. Fixed in r0p1.
1169 - Cortex-A12 852422: Execution of a sequence of instructions might
1170 lead to either a data corruption or a CPU deadlock. Not fixed in
1171 any Cortex-A12 cores yet.
1172 This workaround for all both errata involves setting bit[12] of the
1173 Feature Register. This bit disables an optimisation applied to a
1174 sequence of 2 instructions that use opposing condition codes.
1176 config ARM_ERRATA_821420
1177 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1180 This option enables the workaround for the 821420 Cortex-A12
1181 (all revs) erratum. In very rare timing conditions, a sequence
1182 of VMOV to Core registers instructions, for which the second
1183 one is in the shadow of a branch or abort, can lead to a
1184 deadlock when the VMOV instructions are issued out-of-order.
1186 config ARM_ERRATA_825619
1187 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1190 This option enables the workaround for the 825619 Cortex-A12
1191 (all revs) erratum. Within rare timing constraints, executing a
1192 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1193 and Device/Strongly-Ordered loads and stores might cause deadlock
1195 config ARM_ERRATA_852421
1196 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1199 This option enables the workaround for the 852421 Cortex-A17
1200 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1201 execution of a DMB ST instruction might fail to properly order
1202 stores from GroupA and stores from GroupB.
1204 config ARM_ERRATA_852423
1205 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1208 This option enables the workaround for:
1209 - Cortex-A17 852423: Execution of a sequence of instructions might
1210 lead to either a data corruption or a CPU deadlock. Not fixed in
1211 any Cortex-A17 cores yet.
1212 This is identical to Cortex-A12 erratum 852422. It is a separate
1213 config option from the A12 erratum due to the way errata are checked
1218 source "arch/arm/common/Kconfig"
1225 Find out whether you have ISA slots on your motherboard. ISA is the
1226 name of a bus system, i.e. the way the CPU talks to the other stuff
1227 inside your box. Other bus systems are PCI, EISA, MicroChannel
1228 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1229 newer boards don't support it. If you have ISA, say Y, otherwise N.
1231 # Select ISA DMA controller support
1236 # Select ISA DMA interface
1241 bool "PCI support" if MIGHT_HAVE_PCI
1243 Find out whether you have a PCI motherboard. PCI is the name of a
1244 bus system, i.e. the way the CPU talks to the other stuff inside
1245 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1246 VESA. If you have PCI, say Y, otherwise N.
1252 config PCI_DOMAINS_GENERIC
1253 def_bool PCI_DOMAINS
1255 config PCI_NANOENGINE
1256 bool "BSE nanoEngine PCI support"
1257 depends on SA1100_NANOENGINE
1259 Enable PCI on the BSE nanoEngine board.
1264 config PCI_HOST_ITE8152
1266 depends on PCI && MACH_ARMCORE
1270 source "drivers/pci/Kconfig"
1272 source "drivers/pcmcia/Kconfig"
1276 menu "Kernel Features"
1281 This option should be selected by machines which have an SMP-
1284 The only effect of this option is to make the SMP-related
1285 options available to the user for configuration.
1288 bool "Symmetric Multi-Processing"
1289 depends on CPU_V6K || CPU_V7
1290 depends on GENERIC_CLOCKEVENTS
1292 depends on MMU || ARM_MPU
1295 This enables support for systems with more than one CPU. If you have
1296 a system with only one CPU, say N. If you have a system with more
1297 than one CPU, say Y.
1299 If you say N here, the kernel will run on uni- and multiprocessor
1300 machines, but will use only one CPU of a multiprocessor machine. If
1301 you say Y here, the kernel will run on many, but not all,
1302 uniprocessor machines. On a uniprocessor machine, the kernel
1303 will run faster if you say N here.
1305 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1306 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1307 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1309 If you don't know what to do here, say N.
1312 bool "Allow booting SMP kernel on uniprocessor systems"
1313 depends on SMP && !XIP_KERNEL && MMU
1316 SMP kernels contain instructions which fail on non-SMP processors.
1317 Enabling this option allows the kernel to modify itself to make
1318 these instructions safe. Disabling it allows about 1K of space
1321 If you don't know what to do here, say Y.
1323 config ARM_CPU_TOPOLOGY
1324 bool "Support cpu topology definition"
1325 depends on SMP && CPU_V7
1328 Support ARM cpu topology definition. The MPIDR register defines
1329 affinity between processors which is then used to describe the cpu
1330 topology of an ARM System.
1333 bool "Multi-core scheduler support"
1334 depends on ARM_CPU_TOPOLOGY
1336 Multi-core scheduler support improves the CPU scheduler's decision
1337 making when dealing with multi-core CPU chips at a cost of slightly
1338 increased overhead in some places. If unsure say N here.
1341 bool "SMT scheduler support"
1342 depends on ARM_CPU_TOPOLOGY
1344 Improves the CPU scheduler's decision making when dealing with
1345 MultiThreading at a cost of slightly increased overhead in some
1346 places. If unsure say N here.
1351 This option enables support for the ARM system coherency unit
1353 config HAVE_ARM_ARCH_TIMER
1354 bool "Architected timer support"
1356 select ARM_ARCH_TIMER
1357 select GENERIC_CLOCKEVENTS
1359 This option enables support for the ARM architected timer
1363 select TIMER_OF if OF
1365 This options enables support for the ARM timer and watchdog unit
1368 bool "Multi-Cluster Power Management"
1369 depends on CPU_V7 && SMP
1371 This option provides the common power management infrastructure
1372 for (multi-)cluster based systems, such as big.LITTLE based
1375 config MCPM_QUAD_CLUSTER
1379 To avoid wasting resources unnecessarily, MCPM only supports up
1380 to 2 clusters by default.
1381 Platforms with 3 or 4 clusters that use MCPM must select this
1382 option to allow the additional clusters to be managed.
1385 bool "big.LITTLE support (Experimental)"
1386 depends on CPU_V7 && SMP
1389 This option enables support selections for the big.LITTLE
1390 system architecture.
1393 bool "big.LITTLE switcher support"
1394 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1397 The big.LITTLE "switcher" provides the core functionality to
1398 transparently handle transition between a cluster of A15's
1399 and a cluster of A7's in a big.LITTLE system.
1401 config BL_SWITCHER_DUMMY_IF
1402 tristate "Simple big.LITTLE switcher user interface"
1403 depends on BL_SWITCHER && DEBUG_KERNEL
1405 This is a simple and dummy char dev interface to control
1406 the big.LITTLE switcher core code. It is meant for
1407 debugging purposes only.
1410 prompt "Memory split"
1414 Select the desired split between kernel and user memory.
1416 If you are not absolutely sure what you are doing, leave this
1420 bool "3G/1G user/kernel split"
1421 config VMSPLIT_3G_OPT
1422 depends on !ARM_LPAE
1423 bool "3G/1G user/kernel split (for full 1G low memory)"
1425 bool "2G/2G user/kernel split"
1427 bool "1G/3G user/kernel split"
1432 default PHYS_OFFSET if !MMU
1433 default 0x40000000 if VMSPLIT_1G
1434 default 0x80000000 if VMSPLIT_2G
1435 default 0xB0000000 if VMSPLIT_3G_OPT
1439 int "Maximum number of CPUs (2-32)"
1445 bool "Support for hot-pluggable CPUs"
1448 Say Y here to experiment with turning CPUs off and on. CPUs
1449 can be controlled through /sys/devices/system/cpu.
1452 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1453 depends on HAVE_ARM_SMCCC
1456 Say Y here if you want Linux to communicate with system firmware
1457 implementing the PSCI specification for CPU-centric power
1458 management operations described in ARM document number ARM DEN
1459 0022A ("Power State Coordination Interface System Software on
1462 # The GPIO number here must be sorted by descending number. In case of
1463 # a multiplatform kernel, we just want the highest value required by the
1464 # selected platforms.
1467 default 2048 if ARCH_SOCFPGA
1468 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1470 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1471 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1472 default 416 if ARCH_SUNXI
1473 default 392 if ARCH_U8500
1474 default 352 if ARCH_VT8500
1475 default 288 if ARCH_ROCKCHIP
1476 default 264 if MACH_H4700
1479 Maximum number of GPIOs in the system.
1481 If unsure, leave the default value.
1483 source kernel/Kconfig.preempt
1487 default 200 if ARCH_EBSA110
1488 default 128 if SOC_AT91RM9200
1492 depends on HZ_FIXED = 0
1493 prompt "Timer frequency"
1517 default HZ_FIXED if HZ_FIXED != 0
1518 default 100 if HZ_100
1519 default 200 if HZ_200
1520 default 250 if HZ_250
1521 default 300 if HZ_300
1522 default 500 if HZ_500
1526 def_bool HIGH_RES_TIMERS
1528 config THUMB2_KERNEL
1529 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1530 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1531 default y if CPU_THUMBONLY
1533 select ARM_ASM_UNIFIED
1536 By enabling this option, the kernel will be compiled in
1537 Thumb-2 mode. A compiler/assembler that understand the unified
1538 ARM-Thumb syntax is needed.
1542 config THUMB2_AVOID_R_ARM_THM_JUMP11
1543 bool "Work around buggy Thumb-2 short branch relocations in gas"
1544 depends on THUMB2_KERNEL && MODULES
1547 Various binutils versions can resolve Thumb-2 branches to
1548 locally-defined, preemptible global symbols as short-range "b.n"
1549 branch instructions.
1551 This is a problem, because there's no guarantee the final
1552 destination of the symbol, or any candidate locations for a
1553 trampoline, are within range of the branch. For this reason, the
1554 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1555 relocation in modules at all, and it makes little sense to add
1558 The symptom is that the kernel fails with an "unsupported
1559 relocation" error when loading some modules.
1561 Until fixed tools are available, passing
1562 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1563 code which hits this problem, at the cost of a bit of extra runtime
1564 stack usage in some cases.
1566 The problem is described in more detail at:
1567 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1569 Only Thumb-2 kernels are affected.
1571 Unless you are sure your tools don't have this problem, say Y.
1573 config ARM_ASM_UNIFIED
1576 config ARM_PATCH_IDIV
1577 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1578 depends on CPU_32v7 && !XIP_KERNEL
1581 The ARM compiler inserts calls to __aeabi_idiv() and
1582 __aeabi_uidiv() when it needs to perform division on signed
1583 and unsigned integers. Some v7 CPUs have support for the sdiv
1584 and udiv instructions that can be used to implement those
1587 Enabling this option allows the kernel to modify itself to
1588 replace the first two instructions of these library functions
1589 with the sdiv or udiv plus "bx lr" instructions when the CPU
1590 it is running on supports them. Typically this will be faster
1591 and less power intensive than running the original library
1592 code to do integer division.
1595 bool "Use the ARM EABI to compile the kernel"
1597 This option allows for the kernel to be compiled using the latest
1598 ARM ABI (aka EABI). This is only useful if you are using a user
1599 space environment that is also compiled with EABI.
1601 Since there are major incompatibilities between the legacy ABI and
1602 EABI, especially with regard to structure member alignment, this
1603 option also changes the kernel syscall calling convention to
1604 disambiguate both ABIs and allow for backward compatibility support
1605 (selected with CONFIG_OABI_COMPAT).
1607 To use this you need GCC version 4.0.0 or later.
1610 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1611 depends on AEABI && !THUMB2_KERNEL
1613 This option preserves the old syscall interface along with the
1614 new (ARM EABI) one. It also provides a compatibility layer to
1615 intercept syscalls that have structure arguments which layout
1616 in memory differs between the legacy ABI and the new ARM EABI
1617 (only for non "thumb" binaries). This option adds a tiny
1618 overhead to all syscalls and produces a slightly larger kernel.
1620 The seccomp filter system will not be available when this is
1621 selected, since there is no way yet to sensibly distinguish
1622 between calling conventions during filtering.
1624 If you know you'll be using only pure EABI user space then you
1625 can say N here. If this option is not selected and you attempt
1626 to execute a legacy ABI binary then the result will be
1627 UNPREDICTABLE (in fact it can be predicted that it won't work
1628 at all). If in doubt say N.
1630 config ARCH_HAS_HOLES_MEMORYMODEL
1633 config ARCH_SPARSEMEM_ENABLE
1636 config ARCH_SPARSEMEM_DEFAULT
1637 def_bool ARCH_SPARSEMEM_ENABLE
1639 config ARCH_SELECT_MEMORY_MODEL
1640 def_bool ARCH_SPARSEMEM_ENABLE
1642 config HAVE_ARCH_PFN_VALID
1643 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1645 config HAVE_GENERIC_GUP
1650 bool "High Memory Support"
1653 The address space of ARM processors is only 4 Gigabytes large
1654 and it has to accommodate user address space, kernel address
1655 space as well as some memory mapped IO. That means that, if you
1656 have a large amount of physical memory and/or IO, not all of the
1657 memory can be "permanently mapped" by the kernel. The physical
1658 memory that is not permanently mapped is called "high memory".
1660 Depending on the selected kernel/user memory split, minimum
1661 vmalloc space and actual amount of RAM, you may not need this
1662 option which should result in a slightly faster kernel.
1667 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1671 The VM uses one page of physical memory for each page table.
1672 For systems with a lot of processes, this can use a lot of
1673 precious low memory, eventually leading to low memory being
1674 consumed by page tables. Setting this option will allow
1675 user-space 2nd level page tables to reside in high memory.
1677 config CPU_SW_DOMAIN_PAN
1678 bool "Enable use of CPU domains to implement privileged no-access"
1679 depends on MMU && !ARM_LPAE
1682 Increase kernel security by ensuring that normal kernel accesses
1683 are unable to access userspace addresses. This can help prevent
1684 use-after-free bugs becoming an exploitable privilege escalation
1685 by ensuring that magic values (such as LIST_POISON) will always
1686 fault when dereferenced.
1688 CPUs with low-vector mappings use a best-efforts implementation.
1689 Their lower 1MB needs to remain accessible for the vectors, but
1690 the remainder of userspace will become appropriately inaccessible.
1692 config HW_PERF_EVENTS
1696 config SYS_SUPPORTS_HUGETLBFS
1700 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1704 config ARCH_WANT_GENERAL_HUGETLB
1707 config ARM_MODULE_PLTS
1708 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1711 Allocate PLTs when loading modules so that jumps and calls whose
1712 targets are too far away for their relative offsets to be encoded
1713 in the instructions themselves can be bounced via veneers in the
1714 module's PLT. This allows modules to be allocated in the generic
1715 vmalloc area after the dedicated module memory area has been
1716 exhausted. The modules will use slightly more memory, but after
1717 rounding up to page size, the actual memory footprint is usually
1720 Say y if you are getting out of memory errors while loading modules
1724 config FORCE_MAX_ZONEORDER
1725 int "Maximum zone order"
1726 default "12" if SOC_AM33XX
1727 default "9" if SA1111 || ARCH_EFM32
1730 The kernel memory allocator divides physically contiguous memory
1731 blocks into "zones", where each zone is a power of two number of
1732 pages. This option selects the largest power of two that the kernel
1733 keeps in the memory allocator. If you need to allocate very large
1734 blocks of physically contiguous memory, then you may need to
1735 increase this value.
1737 This config option is actually maximum order plus one. For example,
1738 a value of 11 means that the largest free memory block is 2^10 pages.
1740 config ALIGNMENT_TRAP
1742 depends on CPU_CP15_MMU
1743 default y if !ARCH_EBSA110
1744 select HAVE_PROC_CPU if PROC_FS
1746 ARM processors cannot fetch/store information which is not
1747 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1748 address divisible by 4. On 32-bit ARM processors, these non-aligned
1749 fetch/store instructions will be emulated in software if you say
1750 here, which has a severe performance impact. This is necessary for
1751 correct operation of some network protocols. With an IP-only
1752 configuration it is safe to say N, otherwise say Y.
1754 config UACCESS_WITH_MEMCPY
1755 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1757 default y if CPU_FEROCEON
1759 Implement faster copy_to_user and clear_user methods for CPU
1760 cores where a 8-word STM instruction give significantly higher
1761 memory write throughput than a sequence of individual 32bit stores.
1763 A possible side effect is a slight increase in scheduling latency
1764 between threads sharing the same address space if they invoke
1765 such copy operations with large buffers.
1767 However, if the CPU data cache is using a write-allocate mode,
1768 this option is unlikely to provide any performance gain.
1772 prompt "Enable seccomp to safely compute untrusted bytecode"
1774 This kernel feature is useful for number crunching applications
1775 that may need to compute untrusted bytecode during their
1776 execution. By using pipes or other transports made available to
1777 the process as file descriptors supporting the read/write
1778 syscalls, it's possible to isolate those applications in
1779 their own address space using seccomp. Once seccomp is
1780 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1781 and the task is only allowed to execute a few safe syscalls
1782 defined by each seccomp mode.
1791 bool "Enable paravirtualization code"
1793 This changes the kernel so it can modify itself when it is run
1794 under a hypervisor, potentially improving performance significantly
1795 over full virtualization.
1797 config PARAVIRT_TIME_ACCOUNTING
1798 bool "Paravirtual steal time accounting"
1802 Select this option to enable fine granularity task steal time
1803 accounting. Time spent executing other tasks in parallel with
1804 the current vCPU is discounted from the vCPU power. To account for
1805 that, there can be a small performance impact.
1807 If in doubt, say N here.
1814 bool "Xen guest support on ARM"
1815 depends on ARM && AEABI && OF
1816 depends on CPU_V7 && !CPU_V6
1817 depends on !GENERIC_ATOMIC64
1819 select ARCH_DMA_ADDR_T_64BIT
1824 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1831 bool "Flattened Device Tree support"
1835 Include support for flattened device tree machine descriptions.
1838 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1841 This is the traditional way of passing data to the kernel at boot
1842 time. If you are solely relying on the flattened device tree (or
1843 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1844 to remove ATAGS support from your kernel binary. If unsure,
1847 config DEPRECATED_PARAM_STRUCT
1848 bool "Provide old way to pass kernel parameters"
1851 This was deprecated in 2001 and announced to live on for 5 years.
1852 Some old boot loaders still use this way.
1854 # Compressed boot loader in ROM. Yes, we really want to ask about
1855 # TEXT and BSS so we preserve their values in the config files.
1856 config ZBOOT_ROM_TEXT
1857 hex "Compressed ROM boot loader base address"
1860 The physical address at which the ROM-able zImage is to be
1861 placed in the target. Platforms which normally make use of
1862 ROM-able zImage formats normally set this to a suitable
1863 value in their defconfig file.
1865 If ZBOOT_ROM is not enabled, this has no effect.
1867 config ZBOOT_ROM_BSS
1868 hex "Compressed ROM boot loader BSS address"
1871 The base address of an area of read/write memory in the target
1872 for the ROM-able zImage which must be available while the
1873 decompressor is running. It must be large enough to hold the
1874 entire decompressed kernel plus an additional 128 KiB.
1875 Platforms which normally make use of ROM-able zImage formats
1876 normally set this to a suitable value in their defconfig file.
1878 If ZBOOT_ROM is not enabled, this has no effect.
1881 bool "Compressed boot loader in ROM/flash"
1882 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1883 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1885 Say Y here if you intend to execute your compressed kernel image
1886 (zImage) directly from ROM or flash. If unsure, say N.
1888 config ARM_APPENDED_DTB
1889 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1892 With this option, the boot code will look for a device tree binary
1893 (DTB) appended to zImage
1894 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1896 This is meant as a backward compatibility convenience for those
1897 systems with a bootloader that can't be upgraded to accommodate
1898 the documented boot protocol using a device tree.
1900 Beware that there is very little in terms of protection against
1901 this option being confused by leftover garbage in memory that might
1902 look like a DTB header after a reboot if no actual DTB is appended
1903 to zImage. Do not leave this option active in a production kernel
1904 if you don't intend to always append a DTB. Proper passing of the
1905 location into r2 of a bootloader provided DTB is always preferable
1908 config ARM_ATAG_DTB_COMPAT
1909 bool "Supplement the appended DTB with traditional ATAG information"
1910 depends on ARM_APPENDED_DTB
1912 Some old bootloaders can't be updated to a DTB capable one, yet
1913 they provide ATAGs with memory configuration, the ramdisk address,
1914 the kernel cmdline string, etc. Such information is dynamically
1915 provided by the bootloader and can't always be stored in a static
1916 DTB. To allow a device tree enabled kernel to be used with such
1917 bootloaders, this option allows zImage to extract the information
1918 from the ATAG list and store it at run time into the appended DTB.
1921 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1922 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1924 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1925 bool "Use bootloader kernel arguments if available"
1927 Uses the command-line options passed by the boot loader instead of
1928 the device tree bootargs property. If the boot loader doesn't provide
1929 any, the device tree bootargs property will be used.
1931 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1932 bool "Extend with bootloader kernel arguments"
1934 The command-line arguments provided by the boot loader will be
1935 appended to the the device tree bootargs property.
1940 string "Default kernel command string"
1943 On some architectures (EBSA110 and CATS), there is currently no way
1944 for the boot loader to pass arguments to the kernel. For these
1945 architectures, you should supply some command-line options at build
1946 time by entering them here. As a minimum, you should specify the
1947 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1950 prompt "Kernel command line type" if CMDLINE != ""
1951 default CMDLINE_FROM_BOOTLOADER
1954 config CMDLINE_FROM_BOOTLOADER
1955 bool "Use bootloader kernel arguments if available"
1957 Uses the command-line options passed by the boot loader. If
1958 the boot loader doesn't provide any, the default kernel command
1959 string provided in CMDLINE will be used.
1961 config CMDLINE_EXTEND
1962 bool "Extend bootloader kernel arguments"
1964 The command-line arguments provided by the boot loader will be
1965 appended to the default kernel command string.
1967 config CMDLINE_FORCE
1968 bool "Always use the default kernel command string"
1970 Always use the default kernel command string, even if the boot
1971 loader passes other arguments to the kernel.
1972 This is useful if you cannot or don't want to change the
1973 command-line options your boot loader passes to the kernel.
1977 bool "Kernel Execute-In-Place from ROM"
1978 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1980 Execute-In-Place allows the kernel to run from non-volatile storage
1981 directly addressable by the CPU, such as NOR flash. This saves RAM
1982 space since the text section of the kernel is not loaded from flash
1983 to RAM. Read-write sections, such as the data section and stack,
1984 are still copied to RAM. The XIP kernel is not compressed since
1985 it has to run directly from flash, so it will take more space to
1986 store it. The flash address used to link the kernel object files,
1987 and for storing it, is configuration dependent. Therefore, if you
1988 say Y here, you must know the proper physical address where to
1989 store the kernel image depending on your own flash memory usage.
1991 Also note that the make target becomes "make xipImage" rather than
1992 "make zImage" or "make Image". The final kernel binary to put in
1993 ROM memory will be arch/arm/boot/xipImage.
1997 config XIP_PHYS_ADDR
1998 hex "XIP Kernel Physical Location"
1999 depends on XIP_KERNEL
2000 default "0x00080000"
2002 This is the physical address in your flash memory the kernel will
2003 be linked for and stored to. This address is dependent on your
2007 bool "Kexec system call (EXPERIMENTAL)"
2008 depends on (!SMP || PM_SLEEP_SMP)
2012 kexec is a system call that implements the ability to shutdown your
2013 current kernel, and to start another kernel. It is like a reboot
2014 but it is independent of the system firmware. And like a reboot
2015 you can start any kernel with it, not just Linux.
2017 It is an ongoing process to be certain the hardware in a machine
2018 is properly shutdown, so do not be surprised if this code does not
2019 initially work for you.
2022 bool "Export atags in procfs"
2023 depends on ATAGS && KEXEC
2026 Should the atags used to boot the kernel be exported in an "atags"
2027 file in procfs. Useful with kexec.
2030 bool "Build kdump crash kernel (EXPERIMENTAL)"
2032 Generate crash dump after being started by kexec. This should
2033 be normally only set in special crash dump kernels which are
2034 loaded in the main kernel with kexec-tools into a specially
2035 reserved region and then later executed after a crash by
2036 kdump/kexec. The crash dump kernel must be compiled to a
2037 memory address not used by the main kernel
2039 For more details see Documentation/kdump/kdump.txt
2041 config AUTO_ZRELADDR
2042 bool "Auto calculation of the decompressed kernel image address"
2044 ZRELADDR is the physical address where the decompressed kernel
2045 image will be placed. If AUTO_ZRELADDR is selected, the address
2046 will be determined at run-time by masking the current IP with
2047 0xf8000000. This assumes the zImage being placed in the first 128MB
2048 from start of memory.
2054 bool "UEFI runtime support"
2055 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2057 select EFI_PARAMS_FROM_FDT
2060 select EFI_RUNTIME_WRAPPERS
2062 This option provides support for runtime services provided
2063 by UEFI firmware (such as non-volatile variables, realtime
2064 clock, and platform reset). A UEFI stub is also provided to
2065 allow the kernel to be booted as an EFI application. This
2066 is only useful for kernels that may run on systems that have
2070 bool "Enable support for SMBIOS (DMI) tables"
2074 This enables SMBIOS/DMI feature for systems.
2076 This option is only useful on systems that have UEFI firmware.
2077 However, even with this option, the resultant kernel should
2078 continue to boot on existing non-UEFI platforms.
2080 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2081 i.e., the the practice of identifying the platform via DMI to
2082 decide whether certain workarounds for buggy hardware and/or
2083 firmware need to be enabled. This would require the DMI subsystem
2084 to be enabled much earlier than we do on ARM, which is non-trivial.
2088 menu "CPU Power Management"
2090 source "drivers/cpufreq/Kconfig"
2092 source "drivers/cpuidle/Kconfig"
2096 menu "Floating point emulation"
2098 comment "At least one emulation must be selected"
2101 bool "NWFPE math emulation"
2102 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2104 Say Y to include the NWFPE floating point emulator in the kernel.
2105 This is necessary to run most binaries. Linux does not currently
2106 support floating point hardware so you need to say Y here even if
2107 your machine has an FPA or floating point co-processor podule.
2109 You may say N here if you are going to load the Acorn FPEmulator
2110 early in the bootup.
2113 bool "Support extended precision"
2114 depends on FPE_NWFPE
2116 Say Y to include 80-bit support in the kernel floating-point
2117 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2118 Note that gcc does not generate 80-bit operations by default,
2119 so in most cases this option only enlarges the size of the
2120 floating point emulator without any good reason.
2122 You almost surely want to say N here.
2125 bool "FastFPE math emulation (EXPERIMENTAL)"
2126 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2128 Say Y here to include the FAST floating point emulator in the kernel.
2129 This is an experimental much faster emulator which now also has full
2130 precision for the mantissa. It does not support any exceptions.
2131 It is very simple, and approximately 3-6 times faster than NWFPE.
2133 It should be sufficient for most programs. It may be not suitable
2134 for scientific calculations, but you have to check this for yourself.
2135 If you do not feel you need a faster FP emulation you should better
2139 bool "VFP-format floating point maths"
2140 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2142 Say Y to include VFP support code in the kernel. This is needed
2143 if your hardware includes a VFP unit.
2145 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2146 release notes and additional status information.
2148 Say N if your target does not have VFP hardware.
2156 bool "Advanced SIMD (NEON) Extension support"
2157 depends on VFPv3 && CPU_V7
2159 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2162 config KERNEL_MODE_NEON
2163 bool "Support for NEON in kernel mode"
2164 depends on NEON && AEABI
2166 Say Y to include support for NEON in kernel mode.
2170 menu "Userspace binary formats"
2172 source "fs/Kconfig.binfmt"
2176 menu "Power management options"
2178 source "kernel/power/Kconfig"
2180 config ARCH_SUSPEND_POSSIBLE
2181 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2182 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2185 config ARM_CPU_SUSPEND
2186 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2187 depends on ARCH_SUSPEND_POSSIBLE
2189 config ARCH_HIBERNATION_POSSIBLE
2192 default y if ARCH_SUSPEND_POSSIBLE
2196 source "net/Kconfig"
2198 source "drivers/Kconfig"
2200 source "drivers/firmware/Kconfig"
2204 source "arch/arm/Kconfig.debug"
2206 source "security/Kconfig"
2208 source "crypto/Kconfig"
2210 source "arch/arm/crypto/Kconfig"
2213 source "lib/Kconfig"
2215 source "arch/arm/kvm/Kconfig"