4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
41 select HAVE_KERNEL_GZIP
42 select HAVE_KERNEL_LZMA
43 select HAVE_KERNEL_LZO
45 select HAVE_KPROBES if !XIP_KERNEL
46 select HAVE_KRETPROBES if (HAVE_KPROBES)
48 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
49 select HAVE_PERF_EVENTS
50 select HAVE_REGS_AND_STACK_ACCESS_API
51 select HAVE_SYSCALL_TRACEPOINTS
54 select PERF_USE_VMALLOC
56 select SYS_SUPPORTS_APM_EMULATION
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select MODULES_USE_ELF_REL
59 select CLONE_BACKWARDS
60 select OLD_SIGSUSPEND3
62 select HAVE_CONTEXT_TRACKING
64 The ARM series is a line of low-power-consumption RISC chip designs
65 licensed by ARM Ltd and targeted at embedded applications and
66 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
67 manufactured, but legacy ARM-based PC hardware remains popular in
68 Europe. There is an ARM Linux project with a web page at
69 <http://www.arm.linux.org.uk/>.
71 config ARM_HAS_SG_CHAIN
74 config NEED_SG_DMA_LENGTH
77 config ARM_DMA_USE_IOMMU
79 select ARM_HAS_SG_CHAIN
80 select NEED_SG_DMA_LENGTH
84 config ARM_DMA_IOMMU_ALIGNMENT
85 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
89 DMA mapping framework by default aligns all buffers to the smallest
90 PAGE_SIZE order which is greater than or equal to the requested buffer
91 size. This works well for buffers up to a few hundreds kilobytes, but
92 for larger buffers it just a waste of address space. Drivers which has
93 relatively small addressing window (like 64Mib) might run out of
94 virtual space with just a few allocations.
96 With this parameter you can specify the maximum PAGE_SIZE order for
97 DMA IOMMU buffers. Larger buffers will be aligned only to this
98 specified order. The order is expressed as a power of two multiplied
106 config MIGHT_HAVE_PCI
109 config SYS_SUPPORTS_APM_EMULATION
117 select GENERIC_ALLOCATOR
128 The Extended Industry Standard Architecture (EISA) bus was
129 developed as an open alternative to the IBM MicroChannel bus.
131 The EISA bus provided some of the features of the IBM MicroChannel
132 bus while maintaining backward compatibility with cards made for
133 the older ISA bus. The EISA bus saw limited use between 1988 and
134 1995 when it was made obsolete by the PCI bus.
136 Say Y here if you are building a kernel for an EISA-based machine.
143 config STACKTRACE_SUPPORT
147 config HAVE_LATENCYTOP_SUPPORT
152 config LOCKDEP_SUPPORT
156 config TRACE_IRQFLAGS_SUPPORT
160 config RWSEM_GENERIC_SPINLOCK
164 config RWSEM_XCHGADD_ALGORITHM
167 config ARCH_HAS_ILOG2_U32
170 config ARCH_HAS_ILOG2_U64
173 config ARCH_HAS_CPUFREQ
176 Internal node to signify that the ARCH has CPUFREQ support
177 and that the relevant menu configurations are displayed for
180 config GENERIC_HWEIGHT
184 config GENERIC_CALIBRATE_DELAY
188 config ARCH_MAY_HAVE_PC_FDC
194 config NEED_DMA_MAP_STATE
197 config ARCH_HAS_DMA_SET_COHERENT_MASK
200 config GENERIC_ISA_DMA
206 config NEED_RET_TO_USER
214 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
215 default DRAM_BASE if REMAP_VECTORS_TO_RAM
218 The base address of exception vectors.
220 config ARM_PATCH_PHYS_VIRT
221 bool "Patch physical to virtual translations at runtime" if EMBEDDED
223 depends on !XIP_KERNEL && MMU
224 depends on !ARCH_REALVIEW || !SPARSEMEM
226 Patch phys-to-virt and virt-to-phys translation functions at
227 boot and module load time according to the position of the
228 kernel in system memory.
230 This can only be used with non-XIP MMU kernels where the base
231 of physical memory is at a 16MB boundary.
233 Only disable this option if you know that you do not require
234 this feature (eg, building a kernel for a single machine) and
235 you need to shrink the kernel to the minimal size.
237 config NEED_MACH_GPIO_H
240 Select this when mach/gpio.h is required to provide special
241 definitions for this platform. The need for mach/gpio.h should
242 be avoided when possible.
244 config NEED_MACH_IO_H
247 Select this when mach/io.h is required to provide special
248 definitions for this platform. The need for mach/io.h should
249 be avoided when possible.
251 config NEED_MACH_MEMORY_H
254 Select this when mach/memory.h is required to provide special
255 definitions for this platform. The need for mach/memory.h should
256 be avoided when possible.
259 hex "Physical address of main memory" if MMU
260 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
261 default DRAM_BASE if !MMU
263 Please provide the physical address corresponding to the
264 location of main memory in your system.
270 source "init/Kconfig"
272 source "kernel/Kconfig.freezer"
277 bool "MMU-based Paged Memory Management Support"
280 Select if you want MMU-based virtualised addressing space
281 support by paged memory management. If unsure, say 'Y'.
284 # The "ARM system type" choice list is ordered alphabetically by option
285 # text. Please add new entries in the option alphabetic order.
288 prompt "ARM system type"
289 default ARCH_VERSATILE if !MMU
290 default ARCH_MULTIPLATFORM if MMU
292 config ARCH_MULTIPLATFORM
293 bool "Allow multiple platforms to be selected"
295 select ARM_PATCH_PHYS_VIRT
298 select MULTI_IRQ_HANDLER
302 config ARCH_INTEGRATOR
303 bool "ARM Ltd. Integrator family"
304 select ARCH_HAS_CPUFREQ
307 select COMMON_CLK_VERSATILE
308 select GENERIC_CLOCKEVENTS
311 select MULTI_IRQ_HANDLER
312 select NEED_MACH_MEMORY_H
313 select PLAT_VERSATILE
315 select VERSATILE_FPGA_IRQ
317 Support for ARM's Integrator platform.
320 bool "ARM Ltd. RealView family"
321 select ARCH_WANT_OPTIONAL_GPIOLIB
323 select ARM_TIMER_SP804
325 select COMMON_CLK_VERSATILE
326 select GENERIC_CLOCKEVENTS
327 select GPIO_PL061 if GPIOLIB
329 select NEED_MACH_MEMORY_H
330 select PLAT_VERSATILE
331 select PLAT_VERSATILE_CLCD
333 This enables support for ARM Ltd RealView boards.
335 config ARCH_VERSATILE
336 bool "ARM Ltd. Versatile family"
337 select ARCH_WANT_OPTIONAL_GPIOLIB
339 select ARM_TIMER_SP804
342 select GENERIC_CLOCKEVENTS
343 select HAVE_MACH_CLKDEV
345 select PLAT_VERSATILE
346 select PLAT_VERSATILE_CLCD
347 select PLAT_VERSATILE_CLOCK
348 select VERSATILE_FPGA_IRQ
350 This enables support for ARM Ltd Versatile board.
354 select ARCH_REQUIRE_GPIOLIB
358 select NEED_MACH_GPIO_H
359 select NEED_MACH_IO_H if PCCARD
361 select PINCTRL_AT91 if USE_OF
363 This enables support for systems based on Atmel
364 AT91RM9200 and AT91SAM9* processors.
367 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
368 select ARCH_REQUIRE_GPIOLIB
373 select GENERIC_CLOCKEVENTS
374 select MULTI_IRQ_HANDLER
375 select NEED_MACH_MEMORY_H
378 Support for Cirrus Logic 711x/721x/731x based boards.
381 bool "Cortina Systems Gemini"
382 select ARCH_REQUIRE_GPIOLIB
383 select ARCH_USES_GETTIMEOFFSET
384 select NEED_MACH_GPIO_H
387 Support for the Cortina Systems Gemini family SoCs
391 select ARCH_USES_GETTIMEOFFSET
394 select NEED_MACH_IO_H
395 select NEED_MACH_MEMORY_H
398 This is an evaluation board for the StrongARM processor available
399 from Digital. It has limited hardware on-board, including an
400 Ethernet interface, two PCMCIA sockets, two serial ports and a
405 select ARCH_HAS_HOLES_MEMORYMODEL
406 select ARCH_REQUIRE_GPIOLIB
407 select ARCH_USES_GETTIMEOFFSET
412 select NEED_MACH_MEMORY_H
414 This enables support for the Cirrus EP93xx series of CPUs.
416 config ARCH_FOOTBRIDGE
420 select GENERIC_CLOCKEVENTS
422 select NEED_MACH_IO_H if !MMU
423 select NEED_MACH_MEMORY_H
425 Support for systems based on the DC21285 companion chip
426 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
429 bool "Hilscher NetX based"
433 select GENERIC_CLOCKEVENTS
435 This enables support for systems based on the Hilscher NetX Soc
440 select ARCH_SUPPORTS_MSI
442 select NEED_MACH_MEMORY_H
443 select NEED_RET_TO_USER
448 Support for Intel's IOP13XX (XScale) family of processors.
453 select ARCH_REQUIRE_GPIOLIB
455 select NEED_MACH_GPIO_H
456 select NEED_RET_TO_USER
460 Support for Intel's 80219 and IOP32X (XScale) family of
466 select ARCH_REQUIRE_GPIOLIB
468 select NEED_MACH_GPIO_H
469 select NEED_RET_TO_USER
473 Support for Intel's IOP33X (XScale) family of processors.
478 select ARCH_HAS_DMA_SET_COHERENT_MASK
479 select ARCH_REQUIRE_GPIOLIB
482 select DMABOUNCE if PCI
483 select GENERIC_CLOCKEVENTS
484 select MIGHT_HAVE_PCI
485 select NEED_MACH_IO_H
486 select USB_EHCI_BIG_ENDIAN_MMIO
487 select USB_EHCI_BIG_ENDIAN_DESC
489 Support for Intel's IXP4XX (XScale) family of processors.
493 select ARCH_REQUIRE_GPIOLIB
495 select GENERIC_CLOCKEVENTS
496 select MIGHT_HAVE_PCI
499 select PLAT_ORION_LEGACY
500 select USB_ARCH_HAS_EHCI
503 Support for the Marvell Dove SoC 88AP510
506 bool "Marvell Kirkwood"
507 select ARCH_REQUIRE_GPIOLIB
509 select GENERIC_CLOCKEVENTS
513 select PINCTRL_KIRKWOOD
514 select PLAT_ORION_LEGACY
517 Support for the following Marvell Kirkwood series SoCs:
518 88F6180, 88F6192 and 88F6281.
521 bool "Marvell MV78xx0"
522 select ARCH_REQUIRE_GPIOLIB
524 select GENERIC_CLOCKEVENTS
526 select PLAT_ORION_LEGACY
529 Support for the following Marvell MV78xx0 series SoCs:
535 select ARCH_REQUIRE_GPIOLIB
537 select GENERIC_CLOCKEVENTS
539 select PLAT_ORION_LEGACY
542 Support for the following Marvell Orion 5x series SoCs:
543 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
544 Orion-2 (5281), Orion-1-90 (6183).
547 bool "Marvell PXA168/910/MMP2"
549 select ARCH_REQUIRE_GPIOLIB
551 select GENERIC_ALLOCATOR
552 select GENERIC_CLOCKEVENTS
555 select NEED_MACH_GPIO_H
560 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
563 bool "Micrel/Kendin KS8695"
564 select ARCH_REQUIRE_GPIOLIB
567 select GENERIC_CLOCKEVENTS
568 select NEED_MACH_MEMORY_H
570 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
571 System-on-Chip devices.
574 bool "Nuvoton W90X900 CPU"
575 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
581 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
582 At present, the w90x900 has been renamed nuc900, regarding
583 the ARM series product line, you can login the following
584 link address to know more.
586 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
587 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
591 select ARCH_REQUIRE_GPIOLIB
596 select GENERIC_CLOCKEVENTS
599 select USB_ARCH_HAS_OHCI
602 Support for the NXP LPC32XX family of processors
605 bool "PXA2xx/PXA3xx-based"
607 select ARCH_HAS_CPUFREQ
609 select ARCH_REQUIRE_GPIOLIB
610 select ARM_CPU_SUSPEND if PM
614 select GENERIC_CLOCKEVENTS
617 select MULTI_IRQ_HANDLER
618 select NEED_MACH_GPIO_H
622 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
626 select ARCH_REQUIRE_GPIOLIB
628 select GENERIC_CLOCKEVENTS
631 Support for Qualcomm MSM/QSD based systems. This runs on the
632 apps processor of the MSM/QSD and depends on a shared memory
633 interface to the modem processor which runs the baseband
634 stack and controls some vital subsystems
635 (clock and power control, etc).
638 bool "Renesas SH-Mobile / R-Mobile"
640 select GENERIC_CLOCKEVENTS
641 select HAVE_ARM_SCU if SMP
642 select HAVE_ARM_TWD if LOCAL_TIMERS
644 select HAVE_MACH_CLKDEV
646 select MIGHT_HAVE_CACHE_L2X0
647 select MULTI_IRQ_HANDLER
648 select NEED_MACH_MEMORY_H
650 select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
651 select PM_GENERIC_DOMAINS if PM
654 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
659 select ARCH_MAY_HAVE_PC_FDC
660 select ARCH_SPARSEMEM_ENABLE
661 select ARCH_USES_GETTIMEOFFSET
664 select HAVE_PATA_PLATFORM
666 select NEED_MACH_IO_H
667 select NEED_MACH_MEMORY_H
671 On the Acorn Risc-PC, Linux can support the internal IDE disk and
672 CD-ROM interface, serial and parallel port, and the floppy drive.
676 select ARCH_HAS_CPUFREQ
678 select ARCH_REQUIRE_GPIOLIB
679 select ARCH_SPARSEMEM_ENABLE
684 select GENERIC_CLOCKEVENTS
687 select NEED_MACH_GPIO_H
688 select NEED_MACH_MEMORY_H
691 Support for StrongARM 11x0 based boards.
694 bool "Samsung S3C24XX SoCs"
695 select ARCH_HAS_CPUFREQ
696 select ARCH_REQUIRE_GPIOLIB
699 select GENERIC_CLOCKEVENTS
701 select HAVE_S3C2410_I2C if I2C
702 select HAVE_S3C2410_WATCHDOG if WATCHDOG
703 select HAVE_S3C_RTC if RTC_CLASS
704 select MULTI_IRQ_HANDLER
705 select NEED_MACH_GPIO_H
706 select NEED_MACH_IO_H
708 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
709 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
710 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
711 Samsung SMDK2410 development board (and derivatives).
714 bool "Samsung S3C64XX"
715 select ARCH_HAS_CPUFREQ
716 select ARCH_REQUIRE_GPIOLIB
721 select GENERIC_CLOCKEVENTS
723 select HAVE_S3C2410_I2C if I2C
724 select HAVE_S3C2410_WATCHDOG if WATCHDOG
726 select NEED_MACH_GPIO_H
730 select S3C_GPIO_TRACK
731 select SAMSUNG_CLKSRC
732 select SAMSUNG_GPIOLIB_4BIT
733 select SAMSUNG_IRQ_VIC_TIMER
734 select USB_ARCH_HAS_OHCI
736 Samsung S3C64XX series based systems
739 bool "Samsung S5P6440 S5P6450"
743 select GENERIC_CLOCKEVENTS
745 select HAVE_S3C2410_I2C if I2C
746 select HAVE_S3C2410_WATCHDOG if WATCHDOG
747 select HAVE_S3C_RTC if RTC_CLASS
748 select NEED_MACH_GPIO_H
750 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
754 bool "Samsung S5PC100"
755 select ARCH_REQUIRE_GPIOLIB
759 select GENERIC_CLOCKEVENTS
761 select HAVE_S3C2410_I2C if I2C
762 select HAVE_S3C2410_WATCHDOG if WATCHDOG
763 select HAVE_S3C_RTC if RTC_CLASS
764 select NEED_MACH_GPIO_H
766 Samsung S5PC100 series based systems
769 bool "Samsung S5PV210/S5PC110"
770 select ARCH_HAS_CPUFREQ
771 select ARCH_HAS_HOLES_MEMORYMODEL
772 select ARCH_SPARSEMEM_ENABLE
776 select GENERIC_CLOCKEVENTS
778 select HAVE_S3C2410_I2C if I2C
779 select HAVE_S3C2410_WATCHDOG if WATCHDOG
780 select HAVE_S3C_RTC if RTC_CLASS
781 select NEED_MACH_GPIO_H
782 select NEED_MACH_MEMORY_H
784 Samsung S5PV210/S5PC110 series based systems
787 bool "Samsung EXYNOS"
788 select ARCH_HAS_CPUFREQ
789 select ARCH_HAS_HOLES_MEMORYMODEL
790 select ARCH_SPARSEMEM_ENABLE
794 select GENERIC_CLOCKEVENTS
796 select HAVE_S3C2410_I2C if I2C
797 select HAVE_S3C2410_WATCHDOG if WATCHDOG
798 select HAVE_S3C_RTC if RTC_CLASS
799 select NEED_MACH_GPIO_H
800 select NEED_MACH_MEMORY_H
802 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
806 select ARCH_USES_GETTIMEOFFSET
810 select NEED_MACH_MEMORY_H
815 Support for the StrongARM based Digital DNARD machine, also known
816 as "Shark" (<http://www.shark-linux.de/shark.html>).
819 bool "ST-Ericsson U300 Series"
821 select ARCH_REQUIRE_GPIOLIB
823 select ARM_PATCH_PHYS_VIRT
829 select GENERIC_CLOCKEVENTS
833 Support for ST-Ericsson U300 series mobile platforms.
837 select ARCH_HAS_HOLES_MEMORYMODEL
838 select ARCH_REQUIRE_GPIOLIB
840 select GENERIC_ALLOCATOR
841 select GENERIC_CLOCKEVENTS
842 select GENERIC_IRQ_CHIP
844 select NEED_MACH_GPIO_H
848 Support for TI's DaVinci platform.
853 select ARCH_HAS_CPUFREQ
854 select ARCH_HAS_HOLES_MEMORYMODEL
856 select ARCH_REQUIRE_GPIOLIB
859 select GENERIC_CLOCKEVENTS
860 select GENERIC_IRQ_CHIP
864 select NEED_MACH_IO_H if PCCARD
865 select NEED_MACH_MEMORY_H
867 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
871 menu "Multiple platform selection"
872 depends on ARCH_MULTIPLATFORM
874 comment "CPU Core family selection"
877 bool "ARMv4 based platforms (FA526, StrongARM)"
878 depends on !ARCH_MULTI_V6_V7
879 select ARCH_MULTI_V4_V5
881 config ARCH_MULTI_V4T
882 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
883 depends on !ARCH_MULTI_V6_V7
884 select ARCH_MULTI_V4_V5
887 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
888 depends on !ARCH_MULTI_V6_V7
889 select ARCH_MULTI_V4_V5
891 config ARCH_MULTI_V4_V5
895 bool "ARMv6 based platforms (ARM11)"
896 select ARCH_MULTI_V6_V7
900 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
902 select ARCH_MULTI_V6_V7
906 config ARCH_MULTI_V6_V7
909 config ARCH_MULTI_CPU_AUTO
910 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
916 # This is sorted alphabetically by mach-* pathname. However, plat-*
917 # Kconfigs may be included either alphabetically (according to the
918 # plat- suffix) or along side the corresponding mach-* source.
920 source "arch/arm/mach-mvebu/Kconfig"
922 source "arch/arm/mach-at91/Kconfig"
924 source "arch/arm/mach-bcm/Kconfig"
926 source "arch/arm/mach-bcm2835/Kconfig"
928 source "arch/arm/mach-clps711x/Kconfig"
930 source "arch/arm/mach-cns3xxx/Kconfig"
932 source "arch/arm/mach-davinci/Kconfig"
934 source "arch/arm/mach-dove/Kconfig"
936 source "arch/arm/mach-ep93xx/Kconfig"
938 source "arch/arm/mach-footbridge/Kconfig"
940 source "arch/arm/mach-gemini/Kconfig"
942 source "arch/arm/mach-highbank/Kconfig"
944 source "arch/arm/mach-integrator/Kconfig"
946 source "arch/arm/mach-iop32x/Kconfig"
948 source "arch/arm/mach-iop33x/Kconfig"
950 source "arch/arm/mach-iop13xx/Kconfig"
952 source "arch/arm/mach-ixp4xx/Kconfig"
954 source "arch/arm/mach-kirkwood/Kconfig"
956 source "arch/arm/mach-ks8695/Kconfig"
958 source "arch/arm/mach-msm/Kconfig"
960 source "arch/arm/mach-mv78xx0/Kconfig"
962 source "arch/arm/mach-imx/Kconfig"
964 source "arch/arm/mach-mxs/Kconfig"
966 source "arch/arm/mach-netx/Kconfig"
968 source "arch/arm/mach-nomadik/Kconfig"
970 source "arch/arm/plat-omap/Kconfig"
972 source "arch/arm/mach-omap1/Kconfig"
974 source "arch/arm/mach-omap2/Kconfig"
976 source "arch/arm/mach-orion5x/Kconfig"
978 source "arch/arm/mach-picoxcell/Kconfig"
980 source "arch/arm/mach-pxa/Kconfig"
981 source "arch/arm/plat-pxa/Kconfig"
983 source "arch/arm/mach-mmp/Kconfig"
985 source "arch/arm/mach-realview/Kconfig"
987 source "arch/arm/mach-sa1100/Kconfig"
989 source "arch/arm/plat-samsung/Kconfig"
991 source "arch/arm/mach-socfpga/Kconfig"
993 source "arch/arm/mach-spear/Kconfig"
995 source "arch/arm/mach-s3c24xx/Kconfig"
998 source "arch/arm/mach-s3c64xx/Kconfig"
1001 source "arch/arm/mach-s5p64x0/Kconfig"
1003 source "arch/arm/mach-s5pc100/Kconfig"
1005 source "arch/arm/mach-s5pv210/Kconfig"
1007 source "arch/arm/mach-exynos/Kconfig"
1009 source "arch/arm/mach-shmobile/Kconfig"
1011 source "arch/arm/mach-sunxi/Kconfig"
1013 source "arch/arm/mach-prima2/Kconfig"
1015 source "arch/arm/mach-tegra/Kconfig"
1017 source "arch/arm/mach-u300/Kconfig"
1019 source "arch/arm/mach-ux500/Kconfig"
1021 source "arch/arm/mach-versatile/Kconfig"
1023 source "arch/arm/mach-vexpress/Kconfig"
1024 source "arch/arm/plat-versatile/Kconfig"
1026 source "arch/arm/mach-virt/Kconfig"
1028 source "arch/arm/mach-vt8500/Kconfig"
1030 source "arch/arm/mach-w90x900/Kconfig"
1032 source "arch/arm/mach-zynq/Kconfig"
1034 # Definitions to make life easier
1040 select GENERIC_CLOCKEVENTS
1046 select GENERIC_IRQ_CHIP
1049 config PLAT_ORION_LEGACY
1056 config PLAT_VERSATILE
1059 config ARM_TIMER_SP804
1062 select CLKSRC_OF if OF
1064 source arch/arm/mm/Kconfig
1068 default 16 if ARCH_EP93XX
1072 bool "Enable iWMMXt support" if !CPU_PJ4
1073 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1074 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1076 Enable support for iWMMXt context switching at run time if
1077 running on a CPU that supports it.
1081 depends on CPU_XSCALE
1084 config MULTI_IRQ_HANDLER
1087 Allow each machine to specify it's own IRQ handler at run time.
1090 source "arch/arm/Kconfig-nommu"
1093 config ARM_ERRATA_326103
1094 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1097 Executing a SWP instruction to read-only memory does not set bit 11
1098 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1099 treat the access as a read, preventing a COW from occurring and
1100 causing the faulting task to livelock.
1102 config ARM_ERRATA_411920
1103 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1104 depends on CPU_V6 || CPU_V6K
1106 Invalidation of the Instruction Cache operation can
1107 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1108 It does not affect the MPCore. This option enables the ARM Ltd.
1109 recommended workaround.
1111 config ARM_ERRATA_430973
1112 bool "ARM errata: Stale prediction on replaced interworking branch"
1115 This option enables the workaround for the 430973 Cortex-A8
1116 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1117 interworking branch is replaced with another code sequence at the
1118 same virtual address, whether due to self-modifying code or virtual
1119 to physical address re-mapping, Cortex-A8 does not recover from the
1120 stale interworking branch prediction. This results in Cortex-A8
1121 executing the new code sequence in the incorrect ARM or Thumb state.
1122 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1123 and also flushes the branch target cache at every context switch.
1124 Note that setting specific bits in the ACTLR register may not be
1125 available in non-secure mode.
1127 config ARM_ERRATA_458693
1128 bool "ARM errata: Processor deadlock when a false hazard is created"
1130 depends on !ARCH_MULTIPLATFORM
1132 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1133 erratum. For very specific sequences of memory operations, it is
1134 possible for a hazard condition intended for a cache line to instead
1135 be incorrectly associated with a different cache line. This false
1136 hazard might then cause a processor deadlock. The workaround enables
1137 the L1 caching of the NEON accesses and disables the PLD instruction
1138 in the ACTLR register. Note that setting specific bits in the ACTLR
1139 register may not be available in non-secure mode.
1141 config ARM_ERRATA_460075
1142 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1144 depends on !ARCH_MULTIPLATFORM
1146 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1147 erratum. Any asynchronous access to the L2 cache may encounter a
1148 situation in which recent store transactions to the L2 cache are lost
1149 and overwritten with stale memory contents from external memory. The
1150 workaround disables the write-allocate mode for the L2 cache via the
1151 ACTLR register. Note that setting specific bits in the ACTLR register
1152 may not be available in non-secure mode.
1154 config ARM_ERRATA_742230
1155 bool "ARM errata: DMB operation may be faulty"
1156 depends on CPU_V7 && SMP
1157 depends on !ARCH_MULTIPLATFORM
1159 This option enables the workaround for the 742230 Cortex-A9
1160 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1161 between two write operations may not ensure the correct visibility
1162 ordering of the two writes. This workaround sets a specific bit in
1163 the diagnostic register of the Cortex-A9 which causes the DMB
1164 instruction to behave as a DSB, ensuring the correct behaviour of
1167 config ARM_ERRATA_742231
1168 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1169 depends on CPU_V7 && SMP
1170 depends on !ARCH_MULTIPLATFORM
1172 This option enables the workaround for the 742231 Cortex-A9
1173 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1174 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1175 accessing some data located in the same cache line, may get corrupted
1176 data due to bad handling of the address hazard when the line gets
1177 replaced from one of the CPUs at the same time as another CPU is
1178 accessing it. This workaround sets specific bits in the diagnostic
1179 register of the Cortex-A9 which reduces the linefill issuing
1180 capabilities of the processor.
1182 config PL310_ERRATA_588369
1183 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1184 depends on CACHE_L2X0
1186 The PL310 L2 cache controller implements three types of Clean &
1187 Invalidate maintenance operations: by Physical Address
1188 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1189 They are architecturally defined to behave as the execution of a
1190 clean operation followed immediately by an invalidate operation,
1191 both performing to the same memory location. This functionality
1192 is not correctly implemented in PL310 as clean lines are not
1193 invalidated as a result of these operations.
1195 config ARM_ERRATA_720789
1196 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1199 This option enables the workaround for the 720789 Cortex-A9 (prior to
1200 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1201 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1202 As a consequence of this erratum, some TLB entries which should be
1203 invalidated are not, resulting in an incoherency in the system page
1204 tables. The workaround changes the TLB flushing routines to invalidate
1205 entries regardless of the ASID.
1207 config PL310_ERRATA_727915
1208 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1209 depends on CACHE_L2X0
1211 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1212 operation (offset 0x7FC). This operation runs in background so that
1213 PL310 can handle normal accesses while it is in progress. Under very
1214 rare circumstances, due to this erratum, write data can be lost when
1215 PL310 treats a cacheable write transaction during a Clean &
1216 Invalidate by Way operation.
1218 config ARM_ERRATA_743622
1219 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1221 depends on !ARCH_MULTIPLATFORM
1223 This option enables the workaround for the 743622 Cortex-A9
1224 (r2p*) erratum. Under very rare conditions, a faulty
1225 optimisation in the Cortex-A9 Store Buffer may lead to data
1226 corruption. This workaround sets a specific bit in the diagnostic
1227 register of the Cortex-A9 which disables the Store Buffer
1228 optimisation, preventing the defect from occurring. This has no
1229 visible impact on the overall performance or power consumption of the
1232 config ARM_ERRATA_751472
1233 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1235 depends on !ARCH_MULTIPLATFORM
1237 This option enables the workaround for the 751472 Cortex-A9 (prior
1238 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1239 completion of a following broadcasted operation if the second
1240 operation is received by a CPU before the ICIALLUIS has completed,
1241 potentially leading to corrupted entries in the cache or TLB.
1243 config PL310_ERRATA_753970
1244 bool "PL310 errata: cache sync operation may be faulty"
1245 depends on CACHE_PL310
1247 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1249 Under some condition the effect of cache sync operation on
1250 the store buffer still remains when the operation completes.
1251 This means that the store buffer is always asked to drain and
1252 this prevents it from merging any further writes. The workaround
1253 is to replace the normal offset of cache sync operation (0x730)
1254 by another offset targeting an unmapped PL310 register 0x740.
1255 This has the same effect as the cache sync operation: store buffer
1256 drain and waiting for all buffers empty.
1258 config ARM_ERRATA_754322
1259 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1262 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1263 r3p*) erratum. A speculative memory access may cause a page table walk
1264 which starts prior to an ASID switch but completes afterwards. This
1265 can populate the micro-TLB with a stale entry which may be hit with
1266 the new ASID. This workaround places two dsb instructions in the mm
1267 switching code so that no page table walks can cross the ASID switch.
1269 config ARM_ERRATA_754327
1270 bool "ARM errata: no automatic Store Buffer drain"
1271 depends on CPU_V7 && SMP
1273 This option enables the workaround for the 754327 Cortex-A9 (prior to
1274 r2p0) erratum. The Store Buffer does not have any automatic draining
1275 mechanism and therefore a livelock may occur if an external agent
1276 continuously polls a memory location waiting to observe an update.
1277 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1278 written polling loops from denying visibility of updates to memory.
1280 config ARM_ERRATA_364296
1281 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1282 depends on CPU_V6 && !SMP
1284 This options enables the workaround for the 364296 ARM1136
1285 r0p2 erratum (possible cache data corruption with
1286 hit-under-miss enabled). It sets the undocumented bit 31 in
1287 the auxiliary control register and the FI bit in the control
1288 register, thus disabling hit-under-miss without putting the
1289 processor into full low interrupt latency mode. ARM11MPCore
1292 config ARM_ERRATA_764369
1293 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1294 depends on CPU_V7 && SMP
1296 This option enables the workaround for erratum 764369
1297 affecting Cortex-A9 MPCore with two or more processors (all
1298 current revisions). Under certain timing circumstances, a data
1299 cache line maintenance operation by MVA targeting an Inner
1300 Shareable memory region may fail to proceed up to either the
1301 Point of Coherency or to the Point of Unification of the
1302 system. This workaround adds a DSB instruction before the
1303 relevant cache maintenance functions and sets a specific bit
1304 in the diagnostic control register of the SCU.
1306 config PL310_ERRATA_769419
1307 bool "PL310 errata: no automatic Store Buffer drain"
1308 depends on CACHE_L2X0
1310 On revisions of the PL310 prior to r3p2, the Store Buffer does
1311 not automatically drain. This can cause normal, non-cacheable
1312 writes to be retained when the memory system is idle, leading
1313 to suboptimal I/O performance for drivers using coherent DMA.
1314 This option adds a write barrier to the cpu_idle loop so that,
1315 on systems with an outer cache, the store buffer is drained
1318 config ARM_ERRATA_775420
1319 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1322 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1323 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1324 operation aborts with MMU exception, it might cause the processor
1325 to deadlock. This workaround puts DSB before executing ISB if
1326 an abort may occur on cache maintenance.
1328 config ARM_ERRATA_798181
1329 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1330 depends on CPU_V7 && SMP
1332 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1333 adequately shooting down all use of the old entries. This
1334 option enables the Linux kernel workaround for this erratum
1335 which sends an IPI to the CPUs that are running the same ASID
1336 as the one being invalidated.
1340 source "arch/arm/common/Kconfig"
1350 Find out whether you have ISA slots on your motherboard. ISA is the
1351 name of a bus system, i.e. the way the CPU talks to the other stuff
1352 inside your box. Other bus systems are PCI, EISA, MicroChannel
1353 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1354 newer boards don't support it. If you have ISA, say Y, otherwise N.
1356 # Select ISA DMA controller support
1361 # Select ISA DMA interface
1366 bool "PCI support" if MIGHT_HAVE_PCI
1368 Find out whether you have a PCI motherboard. PCI is the name of a
1369 bus system, i.e. the way the CPU talks to the other stuff inside
1370 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1371 VESA. If you have PCI, say Y, otherwise N.
1377 config PCI_NANOENGINE
1378 bool "BSE nanoEngine PCI support"
1379 depends on SA1100_NANOENGINE
1381 Enable PCI on the BSE nanoEngine board.
1386 # Select the host bridge type
1387 config PCI_HOST_VIA82C505
1389 depends on PCI && ARCH_SHARK
1392 config PCI_HOST_ITE8152
1394 depends on PCI && MACH_ARMCORE
1398 source "drivers/pci/Kconfig"
1400 source "drivers/pcmcia/Kconfig"
1404 menu "Kernel Features"
1409 This option should be selected by machines which have an SMP-
1412 The only effect of this option is to make the SMP-related
1413 options available to the user for configuration.
1416 bool "Symmetric Multi-Processing"
1417 depends on CPU_V6K || CPU_V7
1418 depends on GENERIC_CLOCKEVENTS
1421 select USE_GENERIC_SMP_HELPERS
1423 This enables support for systems with more than one CPU. If you have
1424 a system with only one CPU, like most personal computers, say N. If
1425 you have a system with more than one CPU, say Y.
1427 If you say N here, the kernel will run on single and multiprocessor
1428 machines, but will use only one CPU of a multiprocessor machine. If
1429 you say Y here, the kernel will run on many, but not all, single
1430 processor machines. On a single processor machine, the kernel will
1431 run faster if you say N here.
1433 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1434 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1435 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1437 If you don't know what to do here, say N.
1440 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1441 depends on SMP && !XIP_KERNEL
1444 SMP kernels contain instructions which fail on non-SMP processors.
1445 Enabling this option allows the kernel to modify itself to make
1446 these instructions safe. Disabling it allows about 1K of space
1449 If you don't know what to do here, say Y.
1451 config ARM_CPU_TOPOLOGY
1452 bool "Support cpu topology definition"
1453 depends on SMP && CPU_V7
1456 Support ARM cpu topology definition. The MPIDR register defines
1457 affinity between processors which is then used to describe the cpu
1458 topology of an ARM System.
1461 bool "Multi-core scheduler support"
1462 depends on ARM_CPU_TOPOLOGY
1464 Multi-core scheduler support improves the CPU scheduler's decision
1465 making when dealing with multi-core CPU chips at a cost of slightly
1466 increased overhead in some places. If unsure say N here.
1469 bool "SMT scheduler support"
1470 depends on ARM_CPU_TOPOLOGY
1472 Improves the CPU scheduler's decision making when dealing with
1473 MultiThreading at a cost of slightly increased overhead in some
1474 places. If unsure say N here.
1479 This option enables support for the ARM system coherency unit
1481 config HAVE_ARM_ARCH_TIMER
1482 bool "Architected timer support"
1484 select ARM_ARCH_TIMER
1486 This option enables support for the ARM architected timer
1491 select CLKSRC_OF if OF
1493 This options enables support for the ARM timer and watchdog unit
1496 bool "Multi-Cluster Power Management"
1497 depends on CPU_V7 && SMP
1499 This option provides the common power management infrastructure
1500 for (multi-)cluster based systems, such as big.LITTLE based
1504 prompt "Memory split"
1507 Select the desired split between kernel and user memory.
1509 If you are not absolutely sure what you are doing, leave this
1513 bool "3G/1G user/kernel split"
1515 bool "2G/2G user/kernel split"
1517 bool "1G/3G user/kernel split"
1522 default 0x40000000 if VMSPLIT_1G
1523 default 0x80000000 if VMSPLIT_2G
1527 int "Maximum number of CPUs (2-32)"
1533 bool "Support for hot-pluggable CPUs"
1534 depends on SMP && HOTPLUG
1536 Say Y here to experiment with turning CPUs off and on. CPUs
1537 can be controlled through /sys/devices/system/cpu.
1540 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1543 Say Y here if you want Linux to communicate with system firmware
1544 implementing the PSCI specification for CPU-centric power
1545 management operations described in ARM document number ARM DEN
1546 0022A ("Power State Coordination Interface System Software on
1550 bool "Use local timer interrupts"
1554 Enable support for local timers on SMP platforms, rather then the
1555 legacy IPI broadcast method. Local timers allows the system
1556 accounting to be spread across the timer interval, preventing a
1557 "thundering herd" at every timer tick.
1559 # The GPIO number here must be sorted by descending number. In case of
1560 # a multiplatform kernel, we just want the highest value required by the
1561 # selected platforms.
1564 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1565 default 512 if SOC_OMAP5
1566 default 392 if ARCH_U8500
1567 default 352 if ARCH_VT8500
1568 default 288 if ARCH_SUNXI
1569 default 264 if MACH_H4700
1572 Maximum number of GPIOs in the system.
1574 If unsure, leave the default value.
1576 source kernel/Kconfig.preempt
1580 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1581 ARCH_S5PV210 || ARCH_EXYNOS4
1582 default AT91_TIMER_HZ if ARCH_AT91
1583 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1587 def_bool HIGH_RES_TIMERS
1589 config THUMB2_KERNEL
1590 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1591 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1592 default y if CPU_THUMBONLY
1594 select ARM_ASM_UNIFIED
1597 By enabling this option, the kernel will be compiled in
1598 Thumb-2 mode. A compiler/assembler that understand the unified
1599 ARM-Thumb syntax is needed.
1603 config THUMB2_AVOID_R_ARM_THM_JUMP11
1604 bool "Work around buggy Thumb-2 short branch relocations in gas"
1605 depends on THUMB2_KERNEL && MODULES
1608 Various binutils versions can resolve Thumb-2 branches to
1609 locally-defined, preemptible global symbols as short-range "b.n"
1610 branch instructions.
1612 This is a problem, because there's no guarantee the final
1613 destination of the symbol, or any candidate locations for a
1614 trampoline, are within range of the branch. For this reason, the
1615 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1616 relocation in modules at all, and it makes little sense to add
1619 The symptom is that the kernel fails with an "unsupported
1620 relocation" error when loading some modules.
1622 Until fixed tools are available, passing
1623 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1624 code which hits this problem, at the cost of a bit of extra runtime
1625 stack usage in some cases.
1627 The problem is described in more detail at:
1628 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1630 Only Thumb-2 kernels are affected.
1632 Unless you are sure your tools don't have this problem, say Y.
1634 config ARM_ASM_UNIFIED
1638 bool "Use the ARM EABI to compile the kernel"
1640 This option allows for the kernel to be compiled using the latest
1641 ARM ABI (aka EABI). This is only useful if you are using a user
1642 space environment that is also compiled with EABI.
1644 Since there are major incompatibilities between the legacy ABI and
1645 EABI, especially with regard to structure member alignment, this
1646 option also changes the kernel syscall calling convention to
1647 disambiguate both ABIs and allow for backward compatibility support
1648 (selected with CONFIG_OABI_COMPAT).
1650 To use this you need GCC version 4.0.0 or later.
1653 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1654 depends on AEABI && !THUMB2_KERNEL
1657 This option preserves the old syscall interface along with the
1658 new (ARM EABI) one. It also provides a compatibility layer to
1659 intercept syscalls that have structure arguments which layout
1660 in memory differs between the legacy ABI and the new ARM EABI
1661 (only for non "thumb" binaries). This option adds a tiny
1662 overhead to all syscalls and produces a slightly larger kernel.
1663 If you know you'll be using only pure EABI user space then you
1664 can say N here. If this option is not selected and you attempt
1665 to execute a legacy ABI binary then the result will be
1666 UNPREDICTABLE (in fact it can be predicted that it won't work
1667 at all). If in doubt say Y.
1669 config ARCH_HAS_HOLES_MEMORYMODEL
1672 config ARCH_SPARSEMEM_ENABLE
1675 config ARCH_SPARSEMEM_DEFAULT
1676 def_bool ARCH_SPARSEMEM_ENABLE
1678 config ARCH_SELECT_MEMORY_MODEL
1679 def_bool ARCH_SPARSEMEM_ENABLE
1681 config HAVE_ARCH_PFN_VALID
1682 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1685 bool "High Memory Support"
1688 The address space of ARM processors is only 4 Gigabytes large
1689 and it has to accommodate user address space, kernel address
1690 space as well as some memory mapped IO. That means that, if you
1691 have a large amount of physical memory and/or IO, not all of the
1692 memory can be "permanently mapped" by the kernel. The physical
1693 memory that is not permanently mapped is called "high memory".
1695 Depending on the selected kernel/user memory split, minimum
1696 vmalloc space and actual amount of RAM, you may not need this
1697 option which should result in a slightly faster kernel.
1702 bool "Allocate 2nd-level pagetables from highmem"
1705 config HW_PERF_EVENTS
1706 bool "Enable hardware performance counter support for perf events"
1707 depends on PERF_EVENTS
1710 Enable hardware performance counter support for perf events. If
1711 disabled, perf events will use software events only.
1715 config FORCE_MAX_ZONEORDER
1716 int "Maximum zone order" if ARCH_SHMOBILE
1717 range 11 64 if ARCH_SHMOBILE
1718 default "12" if SOC_AM33XX
1719 default "9" if SA1111
1722 The kernel memory allocator divides physically contiguous memory
1723 blocks into "zones", where each zone is a power of two number of
1724 pages. This option selects the largest power of two that the kernel
1725 keeps in the memory allocator. If you need to allocate very large
1726 blocks of physically contiguous memory, then you may need to
1727 increase this value.
1729 This config option is actually maximum order plus one. For example,
1730 a value of 11 means that the largest free memory block is 2^10 pages.
1732 config ALIGNMENT_TRAP
1734 depends on CPU_CP15_MMU
1735 default y if !ARCH_EBSA110
1736 select HAVE_PROC_CPU if PROC_FS
1738 ARM processors cannot fetch/store information which is not
1739 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1740 address divisible by 4. On 32-bit ARM processors, these non-aligned
1741 fetch/store instructions will be emulated in software if you say
1742 here, which has a severe performance impact. This is necessary for
1743 correct operation of some network protocols. With an IP-only
1744 configuration it is safe to say N, otherwise say Y.
1746 config UACCESS_WITH_MEMCPY
1747 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1749 default y if CPU_FEROCEON
1751 Implement faster copy_to_user and clear_user methods for CPU
1752 cores where a 8-word STM instruction give significantly higher
1753 memory write throughput than a sequence of individual 32bit stores.
1755 A possible side effect is a slight increase in scheduling latency
1756 between threads sharing the same address space if they invoke
1757 such copy operations with large buffers.
1759 However, if the CPU data cache is using a write-allocate mode,
1760 this option is unlikely to provide any performance gain.
1764 prompt "Enable seccomp to safely compute untrusted bytecode"
1766 This kernel feature is useful for number crunching applications
1767 that may need to compute untrusted bytecode during their
1768 execution. By using pipes or other transports made available to
1769 the process as file descriptors supporting the read/write
1770 syscalls, it's possible to isolate those applications in
1771 their own address space using seccomp. Once seccomp is
1772 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1773 and the task is only allowed to execute a few safe syscalls
1774 defined by each seccomp mode.
1776 config CC_STACKPROTECTOR
1777 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1779 This option turns on the -fstack-protector GCC feature. This
1780 feature puts, at the beginning of functions, a canary value on
1781 the stack just before the return address, and validates
1782 the value just before actually returning. Stack based buffer
1783 overflows (that need to overwrite this return address) now also
1784 overwrite the canary, which gets detected and the attack is then
1785 neutralized via a kernel panic.
1786 This feature requires gcc version 4.2 or above.
1793 bool "Xen guest support on ARM (EXPERIMENTAL)"
1794 depends on ARM && AEABI && OF
1795 depends on CPU_V7 && !CPU_V6
1796 depends on !GENERIC_ATOMIC64
1798 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1805 bool "Flattened Device Tree support"
1808 select OF_EARLY_FLATTREE
1810 Include support for flattened device tree machine descriptions.
1813 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1816 This is the traditional way of passing data to the kernel at boot
1817 time. If you are solely relying on the flattened device tree (or
1818 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1819 to remove ATAGS support from your kernel binary. If unsure,
1822 config DEPRECATED_PARAM_STRUCT
1823 bool "Provide old way to pass kernel parameters"
1826 This was deprecated in 2001 and announced to live on for 5 years.
1827 Some old boot loaders still use this way.
1829 # Compressed boot loader in ROM. Yes, we really want to ask about
1830 # TEXT and BSS so we preserve their values in the config files.
1831 config ZBOOT_ROM_TEXT
1832 hex "Compressed ROM boot loader base address"
1835 The physical address at which the ROM-able zImage is to be
1836 placed in the target. Platforms which normally make use of
1837 ROM-able zImage formats normally set this to a suitable
1838 value in their defconfig file.
1840 If ZBOOT_ROM is not enabled, this has no effect.
1842 config ZBOOT_ROM_BSS
1843 hex "Compressed ROM boot loader BSS address"
1846 The base address of an area of read/write memory in the target
1847 for the ROM-able zImage which must be available while the
1848 decompressor is running. It must be large enough to hold the
1849 entire decompressed kernel plus an additional 128 KiB.
1850 Platforms which normally make use of ROM-able zImage formats
1851 normally set this to a suitable value in their defconfig file.
1853 If ZBOOT_ROM is not enabled, this has no effect.
1856 bool "Compressed boot loader in ROM/flash"
1857 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1859 Say Y here if you intend to execute your compressed kernel image
1860 (zImage) directly from ROM or flash. If unsure, say N.
1863 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1864 depends on ZBOOT_ROM && ARCH_SH7372
1865 default ZBOOT_ROM_NONE
1867 Include experimental SD/MMC loading code in the ROM-able zImage.
1868 With this enabled it is possible to write the ROM-able zImage
1869 kernel image to an MMC or SD card and boot the kernel straight
1870 from the reset vector. At reset the processor Mask ROM will load
1871 the first part of the ROM-able zImage which in turn loads the
1872 rest the kernel image to RAM.
1874 config ZBOOT_ROM_NONE
1875 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1877 Do not load image from SD or MMC
1879 config ZBOOT_ROM_MMCIF
1880 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1882 Load image from MMCIF hardware block.
1884 config ZBOOT_ROM_SH_MOBILE_SDHI
1885 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1887 Load image from SDHI hardware block
1891 config ARM_APPENDED_DTB
1892 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1893 depends on OF && !ZBOOT_ROM
1895 With this option, the boot code will look for a device tree binary
1896 (DTB) appended to zImage
1897 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1899 This is meant as a backward compatibility convenience for those
1900 systems with a bootloader that can't be upgraded to accommodate
1901 the documented boot protocol using a device tree.
1903 Beware that there is very little in terms of protection against
1904 this option being confused by leftover garbage in memory that might
1905 look like a DTB header after a reboot if no actual DTB is appended
1906 to zImage. Do not leave this option active in a production kernel
1907 if you don't intend to always append a DTB. Proper passing of the
1908 location into r2 of a bootloader provided DTB is always preferable
1911 config ARM_ATAG_DTB_COMPAT
1912 bool "Supplement the appended DTB with traditional ATAG information"
1913 depends on ARM_APPENDED_DTB
1915 Some old bootloaders can't be updated to a DTB capable one, yet
1916 they provide ATAGs with memory configuration, the ramdisk address,
1917 the kernel cmdline string, etc. Such information is dynamically
1918 provided by the bootloader and can't always be stored in a static
1919 DTB. To allow a device tree enabled kernel to be used with such
1920 bootloaders, this option allows zImage to extract the information
1921 from the ATAG list and store it at run time into the appended DTB.
1924 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1925 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1927 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1928 bool "Use bootloader kernel arguments if available"
1930 Uses the command-line options passed by the boot loader instead of
1931 the device tree bootargs property. If the boot loader doesn't provide
1932 any, the device tree bootargs property will be used.
1934 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1935 bool "Extend with bootloader kernel arguments"
1937 The command-line arguments provided by the boot loader will be
1938 appended to the the device tree bootargs property.
1943 string "Default kernel command string"
1946 On some architectures (EBSA110 and CATS), there is currently no way
1947 for the boot loader to pass arguments to the kernel. For these
1948 architectures, you should supply some command-line options at build
1949 time by entering them here. As a minimum, you should specify the
1950 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1953 prompt "Kernel command line type" if CMDLINE != ""
1954 default CMDLINE_FROM_BOOTLOADER
1957 config CMDLINE_FROM_BOOTLOADER
1958 bool "Use bootloader kernel arguments if available"
1960 Uses the command-line options passed by the boot loader. If
1961 the boot loader doesn't provide any, the default kernel command
1962 string provided in CMDLINE will be used.
1964 config CMDLINE_EXTEND
1965 bool "Extend bootloader kernel arguments"
1967 The command-line arguments provided by the boot loader will be
1968 appended to the default kernel command string.
1970 config CMDLINE_FORCE
1971 bool "Always use the default kernel command string"
1973 Always use the default kernel command string, even if the boot
1974 loader passes other arguments to the kernel.
1975 This is useful if you cannot or don't want to change the
1976 command-line options your boot loader passes to the kernel.
1980 bool "Kernel Execute-In-Place from ROM"
1981 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
1983 Execute-In-Place allows the kernel to run from non-volatile storage
1984 directly addressable by the CPU, such as NOR flash. This saves RAM
1985 space since the text section of the kernel is not loaded from flash
1986 to RAM. Read-write sections, such as the data section and stack,
1987 are still copied to RAM. The XIP kernel is not compressed since
1988 it has to run directly from flash, so it will take more space to
1989 store it. The flash address used to link the kernel object files,
1990 and for storing it, is configuration dependent. Therefore, if you
1991 say Y here, you must know the proper physical address where to
1992 store the kernel image depending on your own flash memory usage.
1994 Also note that the make target becomes "make xipImage" rather than
1995 "make zImage" or "make Image". The final kernel binary to put in
1996 ROM memory will be arch/arm/boot/xipImage.
2000 config XIP_PHYS_ADDR
2001 hex "XIP Kernel Physical Location"
2002 depends on XIP_KERNEL
2003 default "0x00080000"
2005 This is the physical address in your flash memory the kernel will
2006 be linked for and stored to. This address is dependent on your
2010 bool "Kexec system call (EXPERIMENTAL)"
2011 depends on (!SMP || HOTPLUG_CPU)
2013 kexec is a system call that implements the ability to shutdown your
2014 current kernel, and to start another kernel. It is like a reboot
2015 but it is independent of the system firmware. And like a reboot
2016 you can start any kernel with it, not just Linux.
2018 It is an ongoing process to be certain the hardware in a machine
2019 is properly shutdown, so do not be surprised if this code does not
2020 initially work for you. It may help to enable device hotplugging
2024 bool "Export atags in procfs"
2025 depends on ATAGS && KEXEC
2028 Should the atags used to boot the kernel be exported in an "atags"
2029 file in procfs. Useful with kexec.
2032 bool "Build kdump crash kernel (EXPERIMENTAL)"
2034 Generate crash dump after being started by kexec. This should
2035 be normally only set in special crash dump kernels which are
2036 loaded in the main kernel with kexec-tools into a specially
2037 reserved region and then later executed after a crash by
2038 kdump/kexec. The crash dump kernel must be compiled to a
2039 memory address not used by the main kernel
2041 For more details see Documentation/kdump/kdump.txt
2043 config AUTO_ZRELADDR
2044 bool "Auto calculation of the decompressed kernel image address"
2045 depends on !ZBOOT_ROM && !ARCH_U300
2047 ZRELADDR is the physical address where the decompressed kernel
2048 image will be placed. If AUTO_ZRELADDR is selected, the address
2049 will be determined at run-time by masking the current IP with
2050 0xf8000000. This assumes the zImage being placed in the first 128MB
2051 from start of memory.
2055 menu "CPU Power Management"
2058 source "drivers/cpufreq/Kconfig"
2063 Internal configuration node for common cpufreq on Samsung SoC
2065 config CPU_FREQ_S3C24XX
2066 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2067 depends on ARCH_S3C24XX && CPU_FREQ
2070 This enables the CPUfreq driver for the Samsung S3C24XX family
2073 For details, take a look at <file:Documentation/cpu-freq>.
2077 config CPU_FREQ_S3C24XX_PLL
2078 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2079 depends on CPU_FREQ_S3C24XX
2081 Compile in support for changing the PLL frequency from the
2082 S3C24XX series CPUfreq driver. The PLL takes time to settle
2083 after a frequency change, so by default it is not enabled.
2085 This also means that the PLL tables for the selected CPU(s) will
2086 be built which may increase the size of the kernel image.
2088 config CPU_FREQ_S3C24XX_DEBUG
2089 bool "Debug CPUfreq Samsung driver core"
2090 depends on CPU_FREQ_S3C24XX
2092 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2094 config CPU_FREQ_S3C24XX_IODEBUG
2095 bool "Debug CPUfreq Samsung driver IO timing"
2096 depends on CPU_FREQ_S3C24XX
2098 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2100 config CPU_FREQ_S3C24XX_DEBUGFS
2101 bool "Export debugfs for CPUFreq"
2102 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2104 Export status information via debugfs.
2108 source "drivers/cpuidle/Kconfig"
2112 menu "Floating point emulation"
2114 comment "At least one emulation must be selected"
2117 bool "NWFPE math emulation"
2118 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2120 Say Y to include the NWFPE floating point emulator in the kernel.
2121 This is necessary to run most binaries. Linux does not currently
2122 support floating point hardware so you need to say Y here even if
2123 your machine has an FPA or floating point co-processor podule.
2125 You may say N here if you are going to load the Acorn FPEmulator
2126 early in the bootup.
2129 bool "Support extended precision"
2130 depends on FPE_NWFPE
2132 Say Y to include 80-bit support in the kernel floating-point
2133 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2134 Note that gcc does not generate 80-bit operations by default,
2135 so in most cases this option only enlarges the size of the
2136 floating point emulator without any good reason.
2138 You almost surely want to say N here.
2141 bool "FastFPE math emulation (EXPERIMENTAL)"
2142 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2144 Say Y here to include the FAST floating point emulator in the kernel.
2145 This is an experimental much faster emulator which now also has full
2146 precision for the mantissa. It does not support any exceptions.
2147 It is very simple, and approximately 3-6 times faster than NWFPE.
2149 It should be sufficient for most programs. It may be not suitable
2150 for scientific calculations, but you have to check this for yourself.
2151 If you do not feel you need a faster FP emulation you should better
2155 bool "VFP-format floating point maths"
2156 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2158 Say Y to include VFP support code in the kernel. This is needed
2159 if your hardware includes a VFP unit.
2161 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2162 release notes and additional status information.
2164 Say N if your target does not have VFP hardware.
2172 bool "Advanced SIMD (NEON) Extension support"
2173 depends on VFPv3 && CPU_V7
2175 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2180 menu "Userspace binary formats"
2182 source "fs/Kconfig.binfmt"
2185 tristate "RISC OS personality"
2188 Say Y here to include the kernel code necessary if you want to run
2189 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2190 experimental; if this sounds frightening, say N and sleep in peace.
2191 You can also say M here to compile this support as a module (which
2192 will be called arthur).
2196 menu "Power management options"
2198 source "kernel/power/Kconfig"
2200 config ARCH_SUSPEND_POSSIBLE
2201 depends on !ARCH_S5PC100
2202 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2203 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2206 config ARM_CPU_SUSPEND
2211 source "net/Kconfig"
2213 source "drivers/Kconfig"
2217 source "arch/arm/Kconfig.debug"
2219 source "security/Kconfig"
2221 source "crypto/Kconfig"
2223 source "lib/Kconfig"
2225 source "arch/arm/kvm/Kconfig"