1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_CLOCKSOURCE_DATA
6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DEVMEM_IS_ALLOWED
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_FORTIFY_SOURCE
12 select ARCH_HAS_MEMBARRIER_SYNC_CORE
13 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
14 select ARCH_HAS_PHYS_TO_DMA
15 select ARCH_HAS_SET_MEMORY
16 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
17 select ARCH_HAS_STRICT_MODULE_RWX if MMU
18 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
19 select ARCH_HAVE_CUSTOM_GPIO_H
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_MIGHT_HAVE_PC_PARPORT
22 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
23 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
24 select ARCH_SUPPORTS_ATOMIC_RMW
25 select ARCH_USE_BUILTIN_BSWAP
26 select ARCH_USE_CMPXCHG_LOCKREF
27 select ARCH_WANT_IPC_PARSE_VERSION
28 select BUILDTIME_EXTABLE_SORT if MMU
29 select CLONE_BACKWARDS
30 select CPU_PM if (SUSPEND || CPU_IDLE)
31 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
32 select DMA_DIRECT_OPS if !MMU
34 select EDAC_ATOMIC_SCRUB
35 select GENERIC_ALLOCATOR
36 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
37 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
38 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
39 select GENERIC_CPU_AUTOPROBE
40 select GENERIC_EARLY_IOREMAP
41 select GENERIC_IDLE_POLL_SETUP
42 select GENERIC_IRQ_PROBE
43 select GENERIC_IRQ_SHOW
44 select GENERIC_IRQ_SHOW_LEVEL
45 select GENERIC_PCI_IOMAP
46 select GENERIC_SCHED_CLOCK
47 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_STRNCPY_FROM_USER
49 select GENERIC_STRNLEN_USER
50 select HANDLE_DOMAIN_IRQ
51 select HARDIRQS_SW_RESEND
52 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
53 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
54 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
55 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
56 select HAVE_ARCH_MMAP_RND_BITS if MMU
57 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
58 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
59 select HAVE_ARCH_TRACEHOOK
60 select HAVE_ARM_SMCCC if CPU_V7
61 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
62 select HAVE_CONTEXT_TRACKING
63 select HAVE_C_RECORDMCOUNT
64 select HAVE_DEBUG_KMEMLEAK
65 select HAVE_DMA_CONTIGUOUS if MMU
66 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
67 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
68 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
69 select HAVE_EXIT_THREAD
70 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
71 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
72 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
73 select HAVE_GCC_PLUGINS
74 select HAVE_GENERIC_DMA_COHERENT
75 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
76 select HAVE_IDE if PCI || ISA || PCMCIA
77 select HAVE_IRQ_TIME_ACCOUNTING
78 select HAVE_KERNEL_GZIP
79 select HAVE_KERNEL_LZ4
80 select HAVE_KERNEL_LZMA
81 select HAVE_KERNEL_LZO
83 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
84 select HAVE_KRETPROBES if (HAVE_KPROBES)
85 select HAVE_MOD_ARCH_SPECIFIC
87 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
88 select HAVE_OPTPROBES if !THUMB2_KERNEL
89 select HAVE_PERF_EVENTS
91 select HAVE_PERF_USER_STACK_DUMP
92 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
93 select HAVE_REGS_AND_STACK_ACCESS_API
95 select HAVE_STACKPROTECTOR
96 select HAVE_SYSCALL_TRACEPOINTS
98 select HAVE_VIRT_CPU_ACCOUNTING_GEN
99 select IRQ_FORCED_THREADING
100 select MODULES_USE_ELF_REL
101 select NEED_DMA_MAP_STATE
102 select OF_EARLY_FLATTREE if OF
103 select OF_RESERVED_MEM if OF
105 select OLD_SIGSUSPEND3
106 select PCI_SYSCALL if PCI
107 select PERF_USE_VMALLOC
110 select SYS_SUPPORTS_APM_EMULATION
111 # Above selects are sorted alphabetically; please add new ones
112 # according to that. Thanks.
114 The ARM series is a line of low-power-consumption RISC chip designs
115 licensed by ARM Ltd and targeted at embedded applications and
116 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
117 manufactured, but legacy ARM-based PC hardware remains popular in
118 Europe. There is an ARM Linux project with a web page at
119 <http://www.arm.linux.org.uk/>.
121 config ARM_HAS_SG_CHAIN
122 select ARCH_HAS_SG_CHAIN
125 config ARM_DMA_USE_IOMMU
127 select ARM_HAS_SG_CHAIN
128 select NEED_SG_DMA_LENGTH
132 config ARM_DMA_IOMMU_ALIGNMENT
133 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
137 DMA mapping framework by default aligns all buffers to the smallest
138 PAGE_SIZE order which is greater than or equal to the requested buffer
139 size. This works well for buffers up to a few hundreds kilobytes, but
140 for larger buffers it just a waste of address space. Drivers which has
141 relatively small addressing window (like 64Mib) might run out of
142 virtual space with just a few allocations.
144 With this parameter you can specify the maximum PAGE_SIZE order for
145 DMA IOMMU buffers. Larger buffers will be aligned only to this
146 specified order. The order is expressed as a power of two multiplied
151 config SYS_SUPPORTS_APM_EMULATION
156 select GENERIC_ALLOCATOR
167 The Extended Industry Standard Architecture (EISA) bus was
168 developed as an open alternative to the IBM MicroChannel bus.
170 The EISA bus provided some of the features of the IBM MicroChannel
171 bus while maintaining backward compatibility with cards made for
172 the older ISA bus. The EISA bus saw limited use between 1988 and
173 1995 when it was made obsolete by the PCI bus.
175 Say Y here if you are building a kernel for an EISA-based machine.
182 config STACKTRACE_SUPPORT
186 config LOCKDEP_SUPPORT
190 config TRACE_IRQFLAGS_SUPPORT
194 config RWSEM_XCHGADD_ALGORITHM
198 config ARCH_HAS_ILOG2_U32
201 config ARCH_HAS_ILOG2_U64
204 config ARCH_HAS_BANDGAP
207 config FIX_EARLYCON_MEM
210 config GENERIC_HWEIGHT
214 config GENERIC_CALIBRATE_DELAY
218 config ARCH_MAY_HAVE_PC_FDC
224 config ARCH_SUPPORTS_UPROBES
227 config ARCH_HAS_DMA_SET_COHERENT_MASK
230 config GENERIC_ISA_DMA
236 config NEED_RET_TO_USER
242 config ARM_PATCH_PHYS_VIRT
243 bool "Patch physical to virtual translations at runtime" if EMBEDDED
245 depends on !XIP_KERNEL && MMU
247 Patch phys-to-virt and virt-to-phys translation functions at
248 boot and module load time according to the position of the
249 kernel in system memory.
251 This can only be used with non-XIP MMU kernels where the base
252 of physical memory is at a 16MB boundary.
254 Only disable this option if you know that you do not require
255 this feature (eg, building a kernel for a single machine) and
256 you need to shrink the kernel to the minimal size.
258 config NEED_MACH_IO_H
261 Select this when mach/io.h is required to provide special
262 definitions for this platform. The need for mach/io.h should
263 be avoided when possible.
265 config NEED_MACH_MEMORY_H
268 Select this when mach/memory.h is required to provide special
269 definitions for this platform. The need for mach/memory.h should
270 be avoided when possible.
273 hex "Physical address of main memory" if MMU
274 depends on !ARM_PATCH_PHYS_VIRT
275 default DRAM_BASE if !MMU
276 default 0x00000000 if ARCH_EBSA110 || \
282 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
283 default 0x20000000 if ARCH_S5PV210
284 default 0xc0000000 if ARCH_SA1100
286 Please provide the physical address corresponding to the
287 location of main memory in your system.
293 config PGTABLE_LEVELS
295 default 3 if ARM_LPAE
301 bool "MMU-based Paged Memory Management Support"
304 Select if you want MMU-based virtualised addressing space
305 support by paged memory management. If unsure, say 'Y'.
307 config ARCH_MMAP_RND_BITS_MIN
310 config ARCH_MMAP_RND_BITS_MAX
311 default 14 if PAGE_OFFSET=0x40000000
312 default 15 if PAGE_OFFSET=0x80000000
316 # The "ARM system type" choice list is ordered alphabetically by option
317 # text. Please add new entries in the option alphabetic order.
320 prompt "ARM system type"
321 default ARM_SINGLE_ARMV7M if !MMU
322 default ARCH_MULTIPLATFORM if MMU
324 config ARCH_MULTIPLATFORM
325 bool "Allow multiple platforms to be selected"
327 select ARM_HAS_SG_CHAIN
328 select ARM_PATCH_PHYS_VIRT
332 select GENERIC_CLOCKEVENTS
333 select GENERIC_IRQ_MULTI_HANDLER
335 select PCI_DOMAINS_GENERIC if PCI
339 config ARM_SINGLE_ARMV7M
340 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
347 select GENERIC_CLOCKEVENTS
354 select ARCH_USES_GETTIMEOFFSET
357 select NEED_MACH_IO_H
358 select NEED_MACH_MEMORY_H
361 This is an evaluation board for the StrongARM processor available
362 from Digital. It has limited hardware on-board, including an
363 Ethernet interface, two PCMCIA sockets, two serial ports and a
368 select ARCH_SPARSEMEM_ENABLE
370 imply ARM_PATCH_PHYS_VIRT
376 select GENERIC_CLOCKEVENTS
379 This enables support for the Cirrus EP93xx series of CPUs.
381 config ARCH_FOOTBRIDGE
385 select GENERIC_CLOCKEVENTS
387 select NEED_MACH_IO_H if !MMU
388 select NEED_MACH_MEMORY_H
390 Support for systems based on the DC21285 companion chip
391 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
394 bool "Hilscher NetX based"
398 select GENERIC_CLOCKEVENTS
400 This enables support for systems based on the Hilscher NetX Soc
406 select NEED_MACH_MEMORY_H
407 select NEED_RET_TO_USER
413 Support for Intel's IOP13XX (XScale) family of processors.
421 select NEED_RET_TO_USER
425 Support for Intel's 80219 and IOP32X (XScale) family of
434 select NEED_RET_TO_USER
438 Support for Intel's IOP33X (XScale) family of processors.
443 select ARCH_HAS_DMA_SET_COHERENT_MASK
444 select ARCH_SUPPORTS_BIG_ENDIAN
447 select DMABOUNCE if PCI
448 select GENERIC_CLOCKEVENTS
451 select NEED_MACH_IO_H
452 select USB_EHCI_BIG_ENDIAN_DESC
453 select USB_EHCI_BIG_ENDIAN_MMIO
455 Support for Intel's IXP4XX (XScale) family of processors.
460 select GENERIC_CLOCKEVENTS
461 select GENERIC_IRQ_MULTI_HANDLER
467 select PLAT_ORION_LEGACY
469 select PM_GENERIC_DOMAINS if PM
471 Support for the Marvell Dove SoC 88AP510
474 bool "Micrel/Kendin KS8695"
477 select GENERIC_CLOCKEVENTS
479 select NEED_MACH_MEMORY_H
481 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
482 System-on-Chip devices.
485 bool "Nuvoton W90X900 CPU"
489 select GENERIC_CLOCKEVENTS
492 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
493 At present, the w90x900 has been renamed nuc900, regarding
494 the ARM series product line, you can login the following
495 link address to know more.
497 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
498 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
504 select CLKSRC_LPC32XX
507 select GENERIC_CLOCKEVENTS
508 select GENERIC_IRQ_MULTI_HANDLER
513 Support for the NXP LPC32XX family of processors
516 bool "PXA2xx/PXA3xx-based"
519 select ARM_CPU_SUSPEND if PM
526 select CPU_XSCALE if !CPU_XSC3
527 select GENERIC_CLOCKEVENTS
528 select GENERIC_IRQ_MULTI_HANDLER
536 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
542 select ARCH_MAY_HAVE_PC_FDC
543 select ARCH_SPARSEMEM_ENABLE
544 select ARCH_USES_GETTIMEOFFSET
548 select HAVE_PATA_PLATFORM
550 select NEED_MACH_IO_H
551 select NEED_MACH_MEMORY_H
554 On the Acorn Risc-PC, Linux can support the internal IDE disk and
555 CD-ROM interface, serial and parallel port, and the floppy drive.
560 select ARCH_SPARSEMEM_ENABLE
564 select TIMER_OF if OF
567 select GENERIC_CLOCKEVENTS
568 select GENERIC_IRQ_MULTI_HANDLER
573 select NEED_MACH_MEMORY_H
576 Support for StrongARM 11x0 based boards.
579 bool "Samsung S3C24XX SoCs"
582 select CLKSRC_SAMSUNG_PWM
583 select GENERIC_CLOCKEVENTS
586 select GENERIC_IRQ_MULTI_HANDLER
587 select HAVE_S3C2410_I2C if I2C
588 select HAVE_S3C2410_WATCHDOG if WATCHDOG
589 select HAVE_S3C_RTC if RTC_CLASS
590 select NEED_MACH_IO_H
594 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
595 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
596 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
597 Samsung SMDK2410 development board (and derivatives).
601 select ARCH_HAS_HOLES_MEMORYMODEL
604 select GENERIC_ALLOCATOR
605 select GENERIC_CLOCKEVENTS
606 select GENERIC_IRQ_CHIP
609 select PM_GENERIC_DOMAINS if PM
610 select PM_GENERIC_DOMAINS_OF if PM && OF
611 select RESET_CONTROLLER
615 Support for TI's DaVinci platform.
620 select ARCH_HAS_HOLES_MEMORYMODEL
624 select GENERIC_CLOCKEVENTS
625 select GENERIC_IRQ_CHIP
626 select GENERIC_IRQ_MULTI_HANDLER
630 select NEED_MACH_IO_H if PCCARD
631 select NEED_MACH_MEMORY_H
634 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
638 menu "Multiple platform selection"
639 depends on ARCH_MULTIPLATFORM
641 comment "CPU Core family selection"
644 bool "ARMv4 based platforms (FA526)"
645 depends on !ARCH_MULTI_V6_V7
646 select ARCH_MULTI_V4_V5
649 config ARCH_MULTI_V4T
650 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
651 depends on !ARCH_MULTI_V6_V7
652 select ARCH_MULTI_V4_V5
653 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
654 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
655 CPU_ARM925T || CPU_ARM940T)
658 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
659 depends on !ARCH_MULTI_V6_V7
660 select ARCH_MULTI_V4_V5
661 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
662 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
663 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
665 config ARCH_MULTI_V4_V5
669 bool "ARMv6 based platforms (ARM11)"
670 select ARCH_MULTI_V6_V7
674 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
676 select ARCH_MULTI_V6_V7
680 config ARCH_MULTI_V6_V7
682 select MIGHT_HAVE_CACHE_L2X0
684 config ARCH_MULTI_CPU_AUTO
685 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
691 bool "Dummy Virtual Machine"
692 depends on ARCH_MULTI_V7
695 select ARM_GIC_V2M if PCI
697 select ARM_GIC_V3_ITS if PCI
699 select HAVE_ARM_ARCH_TIMER
700 select ARCH_SUPPORTS_BIG_ENDIAN
703 # This is sorted alphabetically by mach-* pathname. However, plat-*
704 # Kconfigs may be included either alphabetically (according to the
705 # plat- suffix) or along side the corresponding mach-* source.
707 source "arch/arm/mach-actions/Kconfig"
709 source "arch/arm/mach-alpine/Kconfig"
711 source "arch/arm/mach-artpec/Kconfig"
713 source "arch/arm/mach-asm9260/Kconfig"
715 source "arch/arm/mach-aspeed/Kconfig"
717 source "arch/arm/mach-at91/Kconfig"
719 source "arch/arm/mach-axxia/Kconfig"
721 source "arch/arm/mach-bcm/Kconfig"
723 source "arch/arm/mach-berlin/Kconfig"
725 source "arch/arm/mach-clps711x/Kconfig"
727 source "arch/arm/mach-cns3xxx/Kconfig"
729 source "arch/arm/mach-davinci/Kconfig"
731 source "arch/arm/mach-digicolor/Kconfig"
733 source "arch/arm/mach-dove/Kconfig"
735 source "arch/arm/mach-ep93xx/Kconfig"
737 source "arch/arm/mach-exynos/Kconfig"
738 source "arch/arm/plat-samsung/Kconfig"
740 source "arch/arm/mach-footbridge/Kconfig"
742 source "arch/arm/mach-gemini/Kconfig"
744 source "arch/arm/mach-highbank/Kconfig"
746 source "arch/arm/mach-hisi/Kconfig"
748 source "arch/arm/mach-imx/Kconfig"
750 source "arch/arm/mach-integrator/Kconfig"
752 source "arch/arm/mach-iop13xx/Kconfig"
754 source "arch/arm/mach-iop32x/Kconfig"
756 source "arch/arm/mach-iop33x/Kconfig"
758 source "arch/arm/mach-ixp4xx/Kconfig"
760 source "arch/arm/mach-keystone/Kconfig"
762 source "arch/arm/mach-ks8695/Kconfig"
764 source "arch/arm/mach-mediatek/Kconfig"
766 source "arch/arm/mach-meson/Kconfig"
768 source "arch/arm/mach-mmp/Kconfig"
770 source "arch/arm/mach-moxart/Kconfig"
772 source "arch/arm/mach-mv78xx0/Kconfig"
774 source "arch/arm/mach-mvebu/Kconfig"
776 source "arch/arm/mach-mxs/Kconfig"
778 source "arch/arm/mach-netx/Kconfig"
780 source "arch/arm/mach-nomadik/Kconfig"
782 source "arch/arm/mach-npcm/Kconfig"
784 source "arch/arm/mach-nspire/Kconfig"
786 source "arch/arm/plat-omap/Kconfig"
788 source "arch/arm/mach-omap1/Kconfig"
790 source "arch/arm/mach-omap2/Kconfig"
792 source "arch/arm/mach-orion5x/Kconfig"
794 source "arch/arm/mach-oxnas/Kconfig"
796 source "arch/arm/mach-picoxcell/Kconfig"
798 source "arch/arm/mach-prima2/Kconfig"
800 source "arch/arm/mach-pxa/Kconfig"
801 source "arch/arm/plat-pxa/Kconfig"
803 source "arch/arm/mach-qcom/Kconfig"
805 source "arch/arm/mach-realview/Kconfig"
807 source "arch/arm/mach-rockchip/Kconfig"
809 source "arch/arm/mach-s3c24xx/Kconfig"
811 source "arch/arm/mach-s3c64xx/Kconfig"
813 source "arch/arm/mach-s5pv210/Kconfig"
815 source "arch/arm/mach-sa1100/Kconfig"
817 source "arch/arm/mach-shmobile/Kconfig"
819 source "arch/arm/mach-socfpga/Kconfig"
821 source "arch/arm/mach-spear/Kconfig"
823 source "arch/arm/mach-sti/Kconfig"
825 source "arch/arm/mach-stm32/Kconfig"
827 source "arch/arm/mach-sunxi/Kconfig"
829 source "arch/arm/mach-tango/Kconfig"
831 source "arch/arm/mach-tegra/Kconfig"
833 source "arch/arm/mach-u300/Kconfig"
835 source "arch/arm/mach-uniphier/Kconfig"
837 source "arch/arm/mach-ux500/Kconfig"
839 source "arch/arm/mach-versatile/Kconfig"
841 source "arch/arm/mach-vexpress/Kconfig"
842 source "arch/arm/plat-versatile/Kconfig"
844 source "arch/arm/mach-vt8500/Kconfig"
846 source "arch/arm/mach-w90x900/Kconfig"
848 source "arch/arm/mach-zx/Kconfig"
850 source "arch/arm/mach-zynq/Kconfig"
852 # ARMv7-M architecture
854 bool "Energy Micro efm32"
855 depends on ARM_SINGLE_ARMV7M
858 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
862 bool "NXP LPC18xx/LPC43xx"
863 depends on ARM_SINGLE_ARMV7M
864 select ARCH_HAS_RESET_CONTROLLER
866 select CLKSRC_LPC32XX
869 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
870 high performance microcontrollers.
873 bool "ARM MPS2 platform"
874 depends on ARM_SINGLE_ARMV7M
878 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
879 with a range of available cores like Cortex-M3/M4/M7.
881 Please, note that depends which Application Note is used memory map
882 for the platform may vary, so adjustment of RAM base might be needed.
884 # Definitions to make life easier
890 select GENERIC_CLOCKEVENTS
896 select GENERIC_IRQ_CHIP
899 config PLAT_ORION_LEGACY
906 config PLAT_VERSATILE
909 source "arch/arm/firmware/Kconfig"
911 source arch/arm/mm/Kconfig
914 bool "Enable iWMMXt support"
915 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
916 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
918 Enable support for iWMMXt context switching at run time if
919 running on a CPU that supports it.
922 source "arch/arm/Kconfig-nommu"
925 config PJ4B_ERRATA_4742
926 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
927 depends on CPU_PJ4B && MACH_ARMADA_370
930 When coming out of either a Wait for Interrupt (WFI) or a Wait for
931 Event (WFE) IDLE states, a specific timing sensitivity exists between
932 the retiring WFI/WFE instructions and the newly issued subsequent
933 instructions. This sensitivity can result in a CPU hang scenario.
935 The software must insert either a Data Synchronization Barrier (DSB)
936 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
939 config ARM_ERRATA_326103
940 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
943 Executing a SWP instruction to read-only memory does not set bit 11
944 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
945 treat the access as a read, preventing a COW from occurring and
946 causing the faulting task to livelock.
948 config ARM_ERRATA_411920
949 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
950 depends on CPU_V6 || CPU_V6K
952 Invalidation of the Instruction Cache operation can
953 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
954 It does not affect the MPCore. This option enables the ARM Ltd.
955 recommended workaround.
957 config ARM_ERRATA_430973
958 bool "ARM errata: Stale prediction on replaced interworking branch"
961 This option enables the workaround for the 430973 Cortex-A8
962 r1p* erratum. If a code sequence containing an ARM/Thumb
963 interworking branch is replaced with another code sequence at the
964 same virtual address, whether due to self-modifying code or virtual
965 to physical address re-mapping, Cortex-A8 does not recover from the
966 stale interworking branch prediction. This results in Cortex-A8
967 executing the new code sequence in the incorrect ARM or Thumb state.
968 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
969 and also flushes the branch target cache at every context switch.
970 Note that setting specific bits in the ACTLR register may not be
971 available in non-secure mode.
973 config ARM_ERRATA_458693
974 bool "ARM errata: Processor deadlock when a false hazard is created"
976 depends on !ARCH_MULTIPLATFORM
978 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
979 erratum. For very specific sequences of memory operations, it is
980 possible for a hazard condition intended for a cache line to instead
981 be incorrectly associated with a different cache line. This false
982 hazard might then cause a processor deadlock. The workaround enables
983 the L1 caching of the NEON accesses and disables the PLD instruction
984 in the ACTLR register. Note that setting specific bits in the ACTLR
985 register may not be available in non-secure mode.
987 config ARM_ERRATA_460075
988 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
990 depends on !ARCH_MULTIPLATFORM
992 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
993 erratum. Any asynchronous access to the L2 cache may encounter a
994 situation in which recent store transactions to the L2 cache are lost
995 and overwritten with stale memory contents from external memory. The
996 workaround disables the write-allocate mode for the L2 cache via the
997 ACTLR register. Note that setting specific bits in the ACTLR register
998 may not be available in non-secure mode.
1000 config ARM_ERRATA_742230
1001 bool "ARM errata: DMB operation may be faulty"
1002 depends on CPU_V7 && SMP
1003 depends on !ARCH_MULTIPLATFORM
1005 This option enables the workaround for the 742230 Cortex-A9
1006 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1007 between two write operations may not ensure the correct visibility
1008 ordering of the two writes. This workaround sets a specific bit in
1009 the diagnostic register of the Cortex-A9 which causes the DMB
1010 instruction to behave as a DSB, ensuring the correct behaviour of
1013 config ARM_ERRATA_742231
1014 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1015 depends on CPU_V7 && SMP
1016 depends on !ARCH_MULTIPLATFORM
1018 This option enables the workaround for the 742231 Cortex-A9
1019 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1020 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1021 accessing some data located in the same cache line, may get corrupted
1022 data due to bad handling of the address hazard when the line gets
1023 replaced from one of the CPUs at the same time as another CPU is
1024 accessing it. This workaround sets specific bits in the diagnostic
1025 register of the Cortex-A9 which reduces the linefill issuing
1026 capabilities of the processor.
1028 config ARM_ERRATA_643719
1029 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1030 depends on CPU_V7 && SMP
1033 This option enables the workaround for the 643719 Cortex-A9 (prior to
1034 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1035 register returns zero when it should return one. The workaround
1036 corrects this value, ensuring cache maintenance operations which use
1037 it behave as intended and avoiding data corruption.
1039 config ARM_ERRATA_720789
1040 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1043 This option enables the workaround for the 720789 Cortex-A9 (prior to
1044 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1045 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1046 As a consequence of this erratum, some TLB entries which should be
1047 invalidated are not, resulting in an incoherency in the system page
1048 tables. The workaround changes the TLB flushing routines to invalidate
1049 entries regardless of the ASID.
1051 config ARM_ERRATA_743622
1052 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1054 depends on !ARCH_MULTIPLATFORM
1056 This option enables the workaround for the 743622 Cortex-A9
1057 (r2p*) erratum. Under very rare conditions, a faulty
1058 optimisation in the Cortex-A9 Store Buffer may lead to data
1059 corruption. This workaround sets a specific bit in the diagnostic
1060 register of the Cortex-A9 which disables the Store Buffer
1061 optimisation, preventing the defect from occurring. This has no
1062 visible impact on the overall performance or power consumption of the
1065 config ARM_ERRATA_751472
1066 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1068 depends on !ARCH_MULTIPLATFORM
1070 This option enables the workaround for the 751472 Cortex-A9 (prior
1071 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1072 completion of a following broadcasted operation if the second
1073 operation is received by a CPU before the ICIALLUIS has completed,
1074 potentially leading to corrupted entries in the cache or TLB.
1076 config ARM_ERRATA_754322
1077 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1080 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1081 r3p*) erratum. A speculative memory access may cause a page table walk
1082 which starts prior to an ASID switch but completes afterwards. This
1083 can populate the micro-TLB with a stale entry which may be hit with
1084 the new ASID. This workaround places two dsb instructions in the mm
1085 switching code so that no page table walks can cross the ASID switch.
1087 config ARM_ERRATA_754327
1088 bool "ARM errata: no automatic Store Buffer drain"
1089 depends on CPU_V7 && SMP
1091 This option enables the workaround for the 754327 Cortex-A9 (prior to
1092 r2p0) erratum. The Store Buffer does not have any automatic draining
1093 mechanism and therefore a livelock may occur if an external agent
1094 continuously polls a memory location waiting to observe an update.
1095 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1096 written polling loops from denying visibility of updates to memory.
1098 config ARM_ERRATA_364296
1099 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1102 This options enables the workaround for the 364296 ARM1136
1103 r0p2 erratum (possible cache data corruption with
1104 hit-under-miss enabled). It sets the undocumented bit 31 in
1105 the auxiliary control register and the FI bit in the control
1106 register, thus disabling hit-under-miss without putting the
1107 processor into full low interrupt latency mode. ARM11MPCore
1110 config ARM_ERRATA_764369
1111 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1112 depends on CPU_V7 && SMP
1114 This option enables the workaround for erratum 764369
1115 affecting Cortex-A9 MPCore with two or more processors (all
1116 current revisions). Under certain timing circumstances, a data
1117 cache line maintenance operation by MVA targeting an Inner
1118 Shareable memory region may fail to proceed up to either the
1119 Point of Coherency or to the Point of Unification of the
1120 system. This workaround adds a DSB instruction before the
1121 relevant cache maintenance functions and sets a specific bit
1122 in the diagnostic control register of the SCU.
1124 config ARM_ERRATA_775420
1125 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1128 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1129 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1130 operation aborts with MMU exception, it might cause the processor
1131 to deadlock. This workaround puts DSB before executing ISB if
1132 an abort may occur on cache maintenance.
1134 config ARM_ERRATA_798181
1135 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1136 depends on CPU_V7 && SMP
1138 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1139 adequately shooting down all use of the old entries. This
1140 option enables the Linux kernel workaround for this erratum
1141 which sends an IPI to the CPUs that are running the same ASID
1142 as the one being invalidated.
1144 config ARM_ERRATA_773022
1145 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1148 This option enables the workaround for the 773022 Cortex-A15
1149 (up to r0p4) erratum. In certain rare sequences of code, the
1150 loop buffer may deliver incorrect instructions. This
1151 workaround disables the loop buffer to avoid the erratum.
1153 config ARM_ERRATA_818325_852422
1154 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1157 This option enables the workaround for:
1158 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1159 instruction might deadlock. Fixed in r0p1.
1160 - Cortex-A12 852422: Execution of a sequence of instructions might
1161 lead to either a data corruption or a CPU deadlock. Not fixed in
1162 any Cortex-A12 cores yet.
1163 This workaround for all both errata involves setting bit[12] of the
1164 Feature Register. This bit disables an optimisation applied to a
1165 sequence of 2 instructions that use opposing condition codes.
1167 config ARM_ERRATA_821420
1168 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1171 This option enables the workaround for the 821420 Cortex-A12
1172 (all revs) erratum. In very rare timing conditions, a sequence
1173 of VMOV to Core registers instructions, for which the second
1174 one is in the shadow of a branch or abort, can lead to a
1175 deadlock when the VMOV instructions are issued out-of-order.
1177 config ARM_ERRATA_825619
1178 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1181 This option enables the workaround for the 825619 Cortex-A12
1182 (all revs) erratum. Within rare timing constraints, executing a
1183 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1184 and Device/Strongly-Ordered loads and stores might cause deadlock
1186 config ARM_ERRATA_852421
1187 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1190 This option enables the workaround for the 852421 Cortex-A17
1191 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1192 execution of a DMB ST instruction might fail to properly order
1193 stores from GroupA and stores from GroupB.
1195 config ARM_ERRATA_852423
1196 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1199 This option enables the workaround for:
1200 - Cortex-A17 852423: Execution of a sequence of instructions might
1201 lead to either a data corruption or a CPU deadlock. Not fixed in
1202 any Cortex-A17 cores yet.
1203 This is identical to Cortex-A12 erratum 852422. It is a separate
1204 config option from the A12 erratum due to the way errata are checked
1209 source "arch/arm/common/Kconfig"
1216 Find out whether you have ISA slots on your motherboard. ISA is the
1217 name of a bus system, i.e. the way the CPU talks to the other stuff
1218 inside your box. Other bus systems are PCI, EISA, MicroChannel
1219 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1220 newer boards don't support it. If you have ISA, say Y, otherwise N.
1222 # Select ISA DMA controller support
1227 # Select ISA DMA interface
1231 config PCI_NANOENGINE
1232 bool "BSE nanoEngine PCI support"
1233 depends on SA1100_NANOENGINE
1235 Enable PCI on the BSE nanoEngine board.
1237 config PCI_HOST_ITE8152
1239 depends on PCI && MACH_ARMCORE
1245 menu "Kernel Features"
1250 This option should be selected by machines which have an SMP-
1253 The only effect of this option is to make the SMP-related
1254 options available to the user for configuration.
1257 bool "Symmetric Multi-Processing"
1258 depends on CPU_V6K || CPU_V7
1259 depends on GENERIC_CLOCKEVENTS
1261 depends on MMU || ARM_MPU
1264 This enables support for systems with more than one CPU. If you have
1265 a system with only one CPU, say N. If you have a system with more
1266 than one CPU, say Y.
1268 If you say N here, the kernel will run on uni- and multiprocessor
1269 machines, but will use only one CPU of a multiprocessor machine. If
1270 you say Y here, the kernel will run on many, but not all,
1271 uniprocessor machines. On a uniprocessor machine, the kernel
1272 will run faster if you say N here.
1274 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1275 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at
1276 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1278 If you don't know what to do here, say N.
1281 bool "Allow booting SMP kernel on uniprocessor systems"
1282 depends on SMP && !XIP_KERNEL && MMU
1285 SMP kernels contain instructions which fail on non-SMP processors.
1286 Enabling this option allows the kernel to modify itself to make
1287 these instructions safe. Disabling it allows about 1K of space
1290 If you don't know what to do here, say Y.
1292 config ARM_CPU_TOPOLOGY
1293 bool "Support cpu topology definition"
1294 depends on SMP && CPU_V7
1297 Support ARM cpu topology definition. The MPIDR register defines
1298 affinity between processors which is then used to describe the cpu
1299 topology of an ARM System.
1302 bool "Multi-core scheduler support"
1303 depends on ARM_CPU_TOPOLOGY
1305 Multi-core scheduler support improves the CPU scheduler's decision
1306 making when dealing with multi-core CPU chips at a cost of slightly
1307 increased overhead in some places. If unsure say N here.
1310 bool "SMT scheduler support"
1311 depends on ARM_CPU_TOPOLOGY
1313 Improves the CPU scheduler's decision making when dealing with
1314 MultiThreading at a cost of slightly increased overhead in some
1315 places. If unsure say N here.
1320 This option enables support for the ARM system coherency unit
1322 config HAVE_ARM_ARCH_TIMER
1323 bool "Architected timer support"
1325 select ARM_ARCH_TIMER
1326 select GENERIC_CLOCKEVENTS
1328 This option enables support for the ARM architected timer
1332 select TIMER_OF if OF
1334 This options enables support for the ARM timer and watchdog unit
1337 bool "Multi-Cluster Power Management"
1338 depends on CPU_V7 && SMP
1340 This option provides the common power management infrastructure
1341 for (multi-)cluster based systems, such as big.LITTLE based
1344 config MCPM_QUAD_CLUSTER
1348 To avoid wasting resources unnecessarily, MCPM only supports up
1349 to 2 clusters by default.
1350 Platforms with 3 or 4 clusters that use MCPM must select this
1351 option to allow the additional clusters to be managed.
1354 bool "big.LITTLE support (Experimental)"
1355 depends on CPU_V7 && SMP
1358 This option enables support selections for the big.LITTLE
1359 system architecture.
1362 bool "big.LITTLE switcher support"
1363 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1366 The big.LITTLE "switcher" provides the core functionality to
1367 transparently handle transition between a cluster of A15's
1368 and a cluster of A7's in a big.LITTLE system.
1370 config BL_SWITCHER_DUMMY_IF
1371 tristate "Simple big.LITTLE switcher user interface"
1372 depends on BL_SWITCHER && DEBUG_KERNEL
1374 This is a simple and dummy char dev interface to control
1375 the big.LITTLE switcher core code. It is meant for
1376 debugging purposes only.
1379 prompt "Memory split"
1383 Select the desired split between kernel and user memory.
1385 If you are not absolutely sure what you are doing, leave this
1389 bool "3G/1G user/kernel split"
1390 config VMSPLIT_3G_OPT
1391 depends on !ARM_LPAE
1392 bool "3G/1G user/kernel split (for full 1G low memory)"
1394 bool "2G/2G user/kernel split"
1396 bool "1G/3G user/kernel split"
1401 default PHYS_OFFSET if !MMU
1402 default 0x40000000 if VMSPLIT_1G
1403 default 0x80000000 if VMSPLIT_2G
1404 default 0xB0000000 if VMSPLIT_3G_OPT
1408 int "Maximum number of CPUs (2-32)"
1414 bool "Support for hot-pluggable CPUs"
1417 Say Y here to experiment with turning CPUs off and on. CPUs
1418 can be controlled through /sys/devices/system/cpu.
1421 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1422 depends on HAVE_ARM_SMCCC
1425 Say Y here if you want Linux to communicate with system firmware
1426 implementing the PSCI specification for CPU-centric power
1427 management operations described in ARM document number ARM DEN
1428 0022A ("Power State Coordination Interface System Software on
1431 # The GPIO number here must be sorted by descending number. In case of
1432 # a multiplatform kernel, we just want the highest value required by the
1433 # selected platforms.
1436 default 2048 if ARCH_SOCFPGA
1437 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1439 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1440 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1441 default 416 if ARCH_SUNXI
1442 default 392 if ARCH_U8500
1443 default 352 if ARCH_VT8500
1444 default 288 if ARCH_ROCKCHIP
1445 default 264 if MACH_H4700
1448 Maximum number of GPIOs in the system.
1450 If unsure, leave the default value.
1454 default 200 if ARCH_EBSA110
1455 default 128 if SOC_AT91RM9200
1459 depends on HZ_FIXED = 0
1460 prompt "Timer frequency"
1484 default HZ_FIXED if HZ_FIXED != 0
1485 default 100 if HZ_100
1486 default 200 if HZ_200
1487 default 250 if HZ_250
1488 default 300 if HZ_300
1489 default 500 if HZ_500
1493 def_bool HIGH_RES_TIMERS
1495 config THUMB2_KERNEL
1496 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1497 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1498 default y if CPU_THUMBONLY
1501 By enabling this option, the kernel will be compiled in
1506 config THUMB2_AVOID_R_ARM_THM_JUMP11
1507 bool "Work around buggy Thumb-2 short branch relocations in gas"
1508 depends on THUMB2_KERNEL && MODULES
1511 Various binutils versions can resolve Thumb-2 branches to
1512 locally-defined, preemptible global symbols as short-range "b.n"
1513 branch instructions.
1515 This is a problem, because there's no guarantee the final
1516 destination of the symbol, or any candidate locations for a
1517 trampoline, are within range of the branch. For this reason, the
1518 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1519 relocation in modules at all, and it makes little sense to add
1522 The symptom is that the kernel fails with an "unsupported
1523 relocation" error when loading some modules.
1525 Until fixed tools are available, passing
1526 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1527 code which hits this problem, at the cost of a bit of extra runtime
1528 stack usage in some cases.
1530 The problem is described in more detail at:
1531 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1533 Only Thumb-2 kernels are affected.
1535 Unless you are sure your tools don't have this problem, say Y.
1537 config ARM_PATCH_IDIV
1538 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1539 depends on CPU_32v7 && !XIP_KERNEL
1542 The ARM compiler inserts calls to __aeabi_idiv() and
1543 __aeabi_uidiv() when it needs to perform division on signed
1544 and unsigned integers. Some v7 CPUs have support for the sdiv
1545 and udiv instructions that can be used to implement those
1548 Enabling this option allows the kernel to modify itself to
1549 replace the first two instructions of these library functions
1550 with the sdiv or udiv plus "bx lr" instructions when the CPU
1551 it is running on supports them. Typically this will be faster
1552 and less power intensive than running the original library
1553 code to do integer division.
1556 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1557 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1559 This option allows for the kernel to be compiled using the latest
1560 ARM ABI (aka EABI). This is only useful if you are using a user
1561 space environment that is also compiled with EABI.
1563 Since there are major incompatibilities between the legacy ABI and
1564 EABI, especially with regard to structure member alignment, this
1565 option also changes the kernel syscall calling convention to
1566 disambiguate both ABIs and allow for backward compatibility support
1567 (selected with CONFIG_OABI_COMPAT).
1569 To use this you need GCC version 4.0.0 or later.
1572 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1573 depends on AEABI && !THUMB2_KERNEL
1575 This option preserves the old syscall interface along with the
1576 new (ARM EABI) one. It also provides a compatibility layer to
1577 intercept syscalls that have structure arguments which layout
1578 in memory differs between the legacy ABI and the new ARM EABI
1579 (only for non "thumb" binaries). This option adds a tiny
1580 overhead to all syscalls and produces a slightly larger kernel.
1582 The seccomp filter system will not be available when this is
1583 selected, since there is no way yet to sensibly distinguish
1584 between calling conventions during filtering.
1586 If you know you'll be using only pure EABI user space then you
1587 can say N here. If this option is not selected and you attempt
1588 to execute a legacy ABI binary then the result will be
1589 UNPREDICTABLE (in fact it can be predicted that it won't work
1590 at all). If in doubt say N.
1592 config ARCH_HAS_HOLES_MEMORYMODEL
1595 config ARCH_SPARSEMEM_ENABLE
1598 config ARCH_SPARSEMEM_DEFAULT
1599 def_bool ARCH_SPARSEMEM_ENABLE
1601 config ARCH_SELECT_MEMORY_MODEL
1602 def_bool ARCH_SPARSEMEM_ENABLE
1604 config HAVE_ARCH_PFN_VALID
1605 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1607 config HAVE_GENERIC_GUP
1612 bool "High Memory Support"
1615 The address space of ARM processors is only 4 Gigabytes large
1616 and it has to accommodate user address space, kernel address
1617 space as well as some memory mapped IO. That means that, if you
1618 have a large amount of physical memory and/or IO, not all of the
1619 memory can be "permanently mapped" by the kernel. The physical
1620 memory that is not permanently mapped is called "high memory".
1622 Depending on the selected kernel/user memory split, minimum
1623 vmalloc space and actual amount of RAM, you may not need this
1624 option which should result in a slightly faster kernel.
1629 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1633 The VM uses one page of physical memory for each page table.
1634 For systems with a lot of processes, this can use a lot of
1635 precious low memory, eventually leading to low memory being
1636 consumed by page tables. Setting this option will allow
1637 user-space 2nd level page tables to reside in high memory.
1639 config CPU_SW_DOMAIN_PAN
1640 bool "Enable use of CPU domains to implement privileged no-access"
1641 depends on MMU && !ARM_LPAE
1644 Increase kernel security by ensuring that normal kernel accesses
1645 are unable to access userspace addresses. This can help prevent
1646 use-after-free bugs becoming an exploitable privilege escalation
1647 by ensuring that magic values (such as LIST_POISON) will always
1648 fault when dereferenced.
1650 CPUs with low-vector mappings use a best-efforts implementation.
1651 Their lower 1MB needs to remain accessible for the vectors, but
1652 the remainder of userspace will become appropriately inaccessible.
1654 config HW_PERF_EVENTS
1658 config SYS_SUPPORTS_HUGETLBFS
1662 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1666 config ARCH_WANT_GENERAL_HUGETLB
1669 config ARM_MODULE_PLTS
1670 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1674 Allocate PLTs when loading modules so that jumps and calls whose
1675 targets are too far away for their relative offsets to be encoded
1676 in the instructions themselves can be bounced via veneers in the
1677 module's PLT. This allows modules to be allocated in the generic
1678 vmalloc area after the dedicated module memory area has been
1679 exhausted. The modules will use slightly more memory, but after
1680 rounding up to page size, the actual memory footprint is usually
1683 Disabling this is usually safe for small single-platform
1684 configurations. If unsure, say y.
1686 config FORCE_MAX_ZONEORDER
1687 int "Maximum zone order"
1688 default "12" if SOC_AM33XX
1689 default "9" if SA1111 || ARCH_EFM32
1692 The kernel memory allocator divides physically contiguous memory
1693 blocks into "zones", where each zone is a power of two number of
1694 pages. This option selects the largest power of two that the kernel
1695 keeps in the memory allocator. If you need to allocate very large
1696 blocks of physically contiguous memory, then you may need to
1697 increase this value.
1699 This config option is actually maximum order plus one. For example,
1700 a value of 11 means that the largest free memory block is 2^10 pages.
1702 config ALIGNMENT_TRAP
1704 depends on CPU_CP15_MMU
1705 default y if !ARCH_EBSA110
1706 select HAVE_PROC_CPU if PROC_FS
1708 ARM processors cannot fetch/store information which is not
1709 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1710 address divisible by 4. On 32-bit ARM processors, these non-aligned
1711 fetch/store instructions will be emulated in software if you say
1712 here, which has a severe performance impact. This is necessary for
1713 correct operation of some network protocols. With an IP-only
1714 configuration it is safe to say N, otherwise say Y.
1716 config UACCESS_WITH_MEMCPY
1717 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1719 default y if CPU_FEROCEON
1721 Implement faster copy_to_user and clear_user methods for CPU
1722 cores where a 8-word STM instruction give significantly higher
1723 memory write throughput than a sequence of individual 32bit stores.
1725 A possible side effect is a slight increase in scheduling latency
1726 between threads sharing the same address space if they invoke
1727 such copy operations with large buffers.
1729 However, if the CPU data cache is using a write-allocate mode,
1730 this option is unlikely to provide any performance gain.
1734 prompt "Enable seccomp to safely compute untrusted bytecode"
1736 This kernel feature is useful for number crunching applications
1737 that may need to compute untrusted bytecode during their
1738 execution. By using pipes or other transports made available to
1739 the process as file descriptors supporting the read/write
1740 syscalls, it's possible to isolate those applications in
1741 their own address space using seccomp. Once seccomp is
1742 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1743 and the task is only allowed to execute a few safe syscalls
1744 defined by each seccomp mode.
1747 bool "Enable paravirtualization code"
1749 This changes the kernel so it can modify itself when it is run
1750 under a hypervisor, potentially improving performance significantly
1751 over full virtualization.
1753 config PARAVIRT_TIME_ACCOUNTING
1754 bool "Paravirtual steal time accounting"
1758 Select this option to enable fine granularity task steal time
1759 accounting. Time spent executing other tasks in parallel with
1760 the current vCPU is discounted from the vCPU power. To account for
1761 that, there can be a small performance impact.
1763 If in doubt, say N here.
1770 bool "Xen guest support on ARM"
1771 depends on ARM && AEABI && OF
1772 depends on CPU_V7 && !CPU_V6
1773 depends on !GENERIC_ATOMIC64
1775 select ARCH_DMA_ADDR_T_64BIT
1781 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1788 bool "Flattened Device Tree support"
1792 Include support for flattened device tree machine descriptions.
1795 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1798 This is the traditional way of passing data to the kernel at boot
1799 time. If you are solely relying on the flattened device tree (or
1800 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1801 to remove ATAGS support from your kernel binary. If unsure,
1804 config DEPRECATED_PARAM_STRUCT
1805 bool "Provide old way to pass kernel parameters"
1808 This was deprecated in 2001 and announced to live on for 5 years.
1809 Some old boot loaders still use this way.
1811 # Compressed boot loader in ROM. Yes, we really want to ask about
1812 # TEXT and BSS so we preserve their values in the config files.
1813 config ZBOOT_ROM_TEXT
1814 hex "Compressed ROM boot loader base address"
1817 The physical address at which the ROM-able zImage is to be
1818 placed in the target. Platforms which normally make use of
1819 ROM-able zImage formats normally set this to a suitable
1820 value in their defconfig file.
1822 If ZBOOT_ROM is not enabled, this has no effect.
1824 config ZBOOT_ROM_BSS
1825 hex "Compressed ROM boot loader BSS address"
1828 The base address of an area of read/write memory in the target
1829 for the ROM-able zImage which must be available while the
1830 decompressor is running. It must be large enough to hold the
1831 entire decompressed kernel plus an additional 128 KiB.
1832 Platforms which normally make use of ROM-able zImage formats
1833 normally set this to a suitable value in their defconfig file.
1835 If ZBOOT_ROM is not enabled, this has no effect.
1838 bool "Compressed boot loader in ROM/flash"
1839 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1840 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1842 Say Y here if you intend to execute your compressed kernel image
1843 (zImage) directly from ROM or flash. If unsure, say N.
1845 config ARM_APPENDED_DTB
1846 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1849 With this option, the boot code will look for a device tree binary
1850 (DTB) appended to zImage
1851 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1853 This is meant as a backward compatibility convenience for those
1854 systems with a bootloader that can't be upgraded to accommodate
1855 the documented boot protocol using a device tree.
1857 Beware that there is very little in terms of protection against
1858 this option being confused by leftover garbage in memory that might
1859 look like a DTB header after a reboot if no actual DTB is appended
1860 to zImage. Do not leave this option active in a production kernel
1861 if you don't intend to always append a DTB. Proper passing of the
1862 location into r2 of a bootloader provided DTB is always preferable
1865 config ARM_ATAG_DTB_COMPAT
1866 bool "Supplement the appended DTB with traditional ATAG information"
1867 depends on ARM_APPENDED_DTB
1869 Some old bootloaders can't be updated to a DTB capable one, yet
1870 they provide ATAGs with memory configuration, the ramdisk address,
1871 the kernel cmdline string, etc. Such information is dynamically
1872 provided by the bootloader and can't always be stored in a static
1873 DTB. To allow a device tree enabled kernel to be used with such
1874 bootloaders, this option allows zImage to extract the information
1875 from the ATAG list and store it at run time into the appended DTB.
1878 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1879 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1881 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1882 bool "Use bootloader kernel arguments if available"
1884 Uses the command-line options passed by the boot loader instead of
1885 the device tree bootargs property. If the boot loader doesn't provide
1886 any, the device tree bootargs property will be used.
1888 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1889 bool "Extend with bootloader kernel arguments"
1891 The command-line arguments provided by the boot loader will be
1892 appended to the the device tree bootargs property.
1897 string "Default kernel command string"
1900 On some architectures (EBSA110 and CATS), there is currently no way
1901 for the boot loader to pass arguments to the kernel. For these
1902 architectures, you should supply some command-line options at build
1903 time by entering them here. As a minimum, you should specify the
1904 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1907 prompt "Kernel command line type" if CMDLINE != ""
1908 default CMDLINE_FROM_BOOTLOADER
1911 config CMDLINE_FROM_BOOTLOADER
1912 bool "Use bootloader kernel arguments if available"
1914 Uses the command-line options passed by the boot loader. If
1915 the boot loader doesn't provide any, the default kernel command
1916 string provided in CMDLINE will be used.
1918 config CMDLINE_EXTEND
1919 bool "Extend bootloader kernel arguments"
1921 The command-line arguments provided by the boot loader will be
1922 appended to the default kernel command string.
1924 config CMDLINE_FORCE
1925 bool "Always use the default kernel command string"
1927 Always use the default kernel command string, even if the boot
1928 loader passes other arguments to the kernel.
1929 This is useful if you cannot or don't want to change the
1930 command-line options your boot loader passes to the kernel.
1934 bool "Kernel Execute-In-Place from ROM"
1935 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1937 Execute-In-Place allows the kernel to run from non-volatile storage
1938 directly addressable by the CPU, such as NOR flash. This saves RAM
1939 space since the text section of the kernel is not loaded from flash
1940 to RAM. Read-write sections, such as the data section and stack,
1941 are still copied to RAM. The XIP kernel is not compressed since
1942 it has to run directly from flash, so it will take more space to
1943 store it. The flash address used to link the kernel object files,
1944 and for storing it, is configuration dependent. Therefore, if you
1945 say Y here, you must know the proper physical address where to
1946 store the kernel image depending on your own flash memory usage.
1948 Also note that the make target becomes "make xipImage" rather than
1949 "make zImage" or "make Image". The final kernel binary to put in
1950 ROM memory will be arch/arm/boot/xipImage.
1954 config XIP_PHYS_ADDR
1955 hex "XIP Kernel Physical Location"
1956 depends on XIP_KERNEL
1957 default "0x00080000"
1959 This is the physical address in your flash memory the kernel will
1960 be linked for and stored to. This address is dependent on your
1963 config XIP_DEFLATED_DATA
1964 bool "Store kernel .data section compressed in ROM"
1965 depends on XIP_KERNEL
1968 Before the kernel is actually executed, its .data section has to be
1969 copied to RAM from ROM. This option allows for storing that data
1970 in compressed form and decompressed to RAM rather than merely being
1971 copied, saving some precious ROM space. A possible drawback is a
1972 slightly longer boot delay.
1975 bool "Kexec system call (EXPERIMENTAL)"
1976 depends on (!SMP || PM_SLEEP_SMP)
1980 kexec is a system call that implements the ability to shutdown your
1981 current kernel, and to start another kernel. It is like a reboot
1982 but it is independent of the system firmware. And like a reboot
1983 you can start any kernel with it, not just Linux.
1985 It is an ongoing process to be certain the hardware in a machine
1986 is properly shutdown, so do not be surprised if this code does not
1987 initially work for you.
1990 bool "Export atags in procfs"
1991 depends on ATAGS && KEXEC
1994 Should the atags used to boot the kernel be exported in an "atags"
1995 file in procfs. Useful with kexec.
1998 bool "Build kdump crash kernel (EXPERIMENTAL)"
2000 Generate crash dump after being started by kexec. This should
2001 be normally only set in special crash dump kernels which are
2002 loaded in the main kernel with kexec-tools into a specially
2003 reserved region and then later executed after a crash by
2004 kdump/kexec. The crash dump kernel must be compiled to a
2005 memory address not used by the main kernel
2007 For more details see Documentation/kdump/kdump.txt
2009 config AUTO_ZRELADDR
2010 bool "Auto calculation of the decompressed kernel image address"
2012 ZRELADDR is the physical address where the decompressed kernel
2013 image will be placed. If AUTO_ZRELADDR is selected, the address
2014 will be determined at run-time by masking the current IP with
2015 0xf8000000. This assumes the zImage being placed in the first 128MB
2016 from start of memory.
2022 bool "UEFI runtime support"
2023 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2025 select EFI_PARAMS_FROM_FDT
2028 select EFI_RUNTIME_WRAPPERS
2030 This option provides support for runtime services provided
2031 by UEFI firmware (such as non-volatile variables, realtime
2032 clock, and platform reset). A UEFI stub is also provided to
2033 allow the kernel to be booted as an EFI application. This
2034 is only useful for kernels that may run on systems that have
2038 bool "Enable support for SMBIOS (DMI) tables"
2042 This enables SMBIOS/DMI feature for systems.
2044 This option is only useful on systems that have UEFI firmware.
2045 However, even with this option, the resultant kernel should
2046 continue to boot on existing non-UEFI platforms.
2048 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2049 i.e., the the practice of identifying the platform via DMI to
2050 decide whether certain workarounds for buggy hardware and/or
2051 firmware need to be enabled. This would require the DMI subsystem
2052 to be enabled much earlier than we do on ARM, which is non-trivial.
2056 menu "CPU Power Management"
2058 source "drivers/cpufreq/Kconfig"
2060 source "drivers/cpuidle/Kconfig"
2064 menu "Floating point emulation"
2066 comment "At least one emulation must be selected"
2069 bool "NWFPE math emulation"
2070 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2072 Say Y to include the NWFPE floating point emulator in the kernel.
2073 This is necessary to run most binaries. Linux does not currently
2074 support floating point hardware so you need to say Y here even if
2075 your machine has an FPA or floating point co-processor podule.
2077 You may say N here if you are going to load the Acorn FPEmulator
2078 early in the bootup.
2081 bool "Support extended precision"
2082 depends on FPE_NWFPE
2084 Say Y to include 80-bit support in the kernel floating-point
2085 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2086 Note that gcc does not generate 80-bit operations by default,
2087 so in most cases this option only enlarges the size of the
2088 floating point emulator without any good reason.
2090 You almost surely want to say N here.
2093 bool "FastFPE math emulation (EXPERIMENTAL)"
2094 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2096 Say Y here to include the FAST floating point emulator in the kernel.
2097 This is an experimental much faster emulator which now also has full
2098 precision for the mantissa. It does not support any exceptions.
2099 It is very simple, and approximately 3-6 times faster than NWFPE.
2101 It should be sufficient for most programs. It may be not suitable
2102 for scientific calculations, but you have to check this for yourself.
2103 If you do not feel you need a faster FP emulation you should better
2107 bool "VFP-format floating point maths"
2108 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2110 Say Y to include VFP support code in the kernel. This is needed
2111 if your hardware includes a VFP unit.
2113 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2114 release notes and additional status information.
2116 Say N if your target does not have VFP hardware.
2124 bool "Advanced SIMD (NEON) Extension support"
2125 depends on VFPv3 && CPU_V7
2127 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2130 config KERNEL_MODE_NEON
2131 bool "Support for NEON in kernel mode"
2132 depends on NEON && AEABI
2134 Say Y to include support for NEON in kernel mode.
2138 menu "Power management options"
2140 source "kernel/power/Kconfig"
2142 config ARCH_SUSPEND_POSSIBLE
2143 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2144 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2147 config ARM_CPU_SUSPEND
2148 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2149 depends on ARCH_SUSPEND_POSSIBLE
2151 config ARCH_HIBERNATION_POSSIBLE
2154 default y if ARCH_SUSPEND_POSSIBLE
2158 source "drivers/firmware/Kconfig"
2161 source "arch/arm/crypto/Kconfig"
2164 source "arch/arm/kvm/Kconfig"