1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CLOCKSOURCE_DATA
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_DEBUG_VIRTUAL if MMU
9 select ARCH_HAS_DEVMEM_IS_ALLOWED
10 select ARCH_HAS_DMA_COHERENT_TO_PFN if SWIOTLB
11 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
12 select ARCH_HAS_ELF_RANDOMIZE
13 select ARCH_HAS_FORTIFY_SOURCE
14 select ARCH_HAS_KEEPINITRD
16 select ARCH_HAS_MEMBARRIER_SYNC_CORE
17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
18 select ARCH_HAS_PHYS_TO_DMA
19 select ARCH_HAS_SETUP_DMA_OPS
20 select ARCH_HAS_SET_MEMORY
21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
22 select ARCH_HAS_STRICT_MODULE_RWX if MMU
23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
27 select ARCH_HAVE_CUSTOM_GPIO_H
28 select ARCH_HAS_GCOV_PROFILE_ALL
29 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC
30 select ARCH_MIGHT_HAVE_PC_PARPORT
31 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
32 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
33 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
34 select ARCH_SUPPORTS_ATOMIC_RMW
35 select ARCH_USE_BUILTIN_BSWAP
36 select ARCH_USE_CMPXCHG_LOCKREF
37 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
38 select ARCH_WANT_IPC_PARSE_VERSION
39 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
40 select BUILDTIME_EXTABLE_SORT if MMU
41 select CLONE_BACKWARDS
42 select CPU_PM if SUSPEND || CPU_IDLE
43 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
44 select DMA_DECLARE_COHERENT
45 select DMA_REMAP if MMU
47 select EDAC_ATOMIC_SCRUB
48 select GENERIC_ALLOCATOR
49 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
50 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
52 select GENERIC_CPU_AUTOPROBE
53 select GENERIC_EARLY_IOREMAP
54 select GENERIC_IDLE_POLL_SETUP
55 select GENERIC_IRQ_PROBE
56 select GENERIC_IRQ_SHOW
57 select GENERIC_IRQ_SHOW_LEVEL
58 select GENERIC_PCI_IOMAP
59 select GENERIC_SCHED_CLOCK
60 select GENERIC_SMP_IDLE_THREAD
61 select GENERIC_STRNCPY_FROM_USER
62 select GENERIC_STRNLEN_USER
63 select HANDLE_DOMAIN_IRQ
64 select HARDIRQS_SW_RESEND
65 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
66 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
67 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
68 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
69 select HAVE_ARCH_MMAP_RND_BITS if MMU
70 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
71 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
72 select HAVE_ARCH_TRACEHOOK
73 select HAVE_ARM_SMCCC if CPU_V7
74 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
75 select HAVE_CONTEXT_TRACKING
76 select HAVE_C_RECORDMCOUNT
77 select HAVE_DEBUG_KMEMLEAK
78 select HAVE_DMA_CONTIGUOUS if MMU
79 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
80 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
81 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
82 select HAVE_EXIT_THREAD
83 select HAVE_FAST_GUP if ARM_LPAE
84 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
85 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
86 select HAVE_FUNCTION_TRACER if !XIP_KERNEL && (CC_IS_GCC || CLANG_VERSION >= 100000)
87 select HAVE_GCC_PLUGINS
88 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
89 select HAVE_IDE if PCI || ISA || PCMCIA
90 select HAVE_IRQ_TIME_ACCOUNTING
91 select HAVE_KERNEL_GZIP
92 select HAVE_KERNEL_LZ4
93 select HAVE_KERNEL_LZMA
94 select HAVE_KERNEL_LZO
96 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
97 select HAVE_KRETPROBES if HAVE_KPROBES
98 select HAVE_MOD_ARCH_SPECIFIC
100 select HAVE_OPROFILE if HAVE_PERF_EVENTS
101 select HAVE_OPTPROBES if !THUMB2_KERNEL
102 select HAVE_PERF_EVENTS
103 select HAVE_PERF_REGS
104 select HAVE_PERF_USER_STACK_DUMP
105 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE
106 select HAVE_REGS_AND_STACK_ACCESS_API
108 select HAVE_STACKPROTECTOR
109 select HAVE_SYSCALL_TRACEPOINTS
111 select HAVE_VIRT_CPU_ACCOUNTING_GEN
112 select IRQ_FORCED_THREADING
113 select MODULES_USE_ELF_REL
114 select NEED_DMA_MAP_STATE
115 select OF_EARLY_FLATTREE if OF
117 select OLD_SIGSUSPEND3
118 select PCI_SYSCALL if PCI
119 select PERF_USE_VMALLOC
122 select SYS_SUPPORTS_APM_EMULATION
123 # Above selects are sorted alphabetically; please add new ones
124 # according to that. Thanks.
126 The ARM series is a line of low-power-consumption RISC chip designs
127 licensed by ARM Ltd and targeted at embedded applications and
128 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
129 manufactured, but legacy ARM-based PC hardware remains popular in
130 Europe. There is an ARM Linux project with a web page at
131 <http://www.arm.linux.org.uk/>.
133 config ARM_HAS_SG_CHAIN
136 config ARM_DMA_USE_IOMMU
138 select ARM_HAS_SG_CHAIN
139 select NEED_SG_DMA_LENGTH
143 config ARM_DMA_IOMMU_ALIGNMENT
144 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
148 DMA mapping framework by default aligns all buffers to the smallest
149 PAGE_SIZE order which is greater than or equal to the requested buffer
150 size. This works well for buffers up to a few hundreds kilobytes, but
151 for larger buffers it just a waste of address space. Drivers which has
152 relatively small addressing window (like 64Mib) might run out of
153 virtual space with just a few allocations.
155 With this parameter you can specify the maximum PAGE_SIZE order for
156 DMA IOMMU buffers. Larger buffers will be aligned only to this
157 specified order. The order is expressed as a power of two multiplied
162 config SYS_SUPPORTS_APM_EMULATION
167 select GENERIC_ALLOCATOR
178 config STACKTRACE_SUPPORT
182 config LOCKDEP_SUPPORT
186 config TRACE_IRQFLAGS_SUPPORT
190 config ARCH_HAS_ILOG2_U32
193 config ARCH_HAS_ILOG2_U64
196 config ARCH_HAS_BANDGAP
199 config FIX_EARLYCON_MEM
202 config GENERIC_HWEIGHT
206 config GENERIC_CALIBRATE_DELAY
210 config ARCH_MAY_HAVE_PC_FDC
216 config ARCH_SUPPORTS_UPROBES
219 config ARCH_HAS_DMA_SET_COHERENT_MASK
222 config GENERIC_ISA_DMA
228 config NEED_RET_TO_USER
234 config ARM_PATCH_PHYS_VIRT
235 bool "Patch physical to virtual translations at runtime" if EMBEDDED
237 depends on !XIP_KERNEL && MMU
239 Patch phys-to-virt and virt-to-phys translation functions at
240 boot and module load time according to the position of the
241 kernel in system memory.
243 This can only be used with non-XIP MMU kernels where the base
244 of physical memory is at a 16MB boundary.
246 Only disable this option if you know that you do not require
247 this feature (eg, building a kernel for a single machine) and
248 you need to shrink the kernel to the minimal size.
250 config NEED_MACH_IO_H
253 Select this when mach/io.h is required to provide special
254 definitions for this platform. The need for mach/io.h should
255 be avoided when possible.
257 config NEED_MACH_MEMORY_H
260 Select this when mach/memory.h is required to provide special
261 definitions for this platform. The need for mach/memory.h should
262 be avoided when possible.
265 hex "Physical address of main memory" if MMU
266 depends on !ARM_PATCH_PHYS_VIRT
267 default DRAM_BASE if !MMU
268 default 0x00000000 if ARCH_EBSA110 || \
272 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
273 default 0x20000000 if ARCH_S5PV210
274 default 0xc0000000 if ARCH_SA1100
276 Please provide the physical address corresponding to the
277 location of main memory in your system.
283 config PGTABLE_LEVELS
285 default 3 if ARM_LPAE
291 bool "MMU-based Paged Memory Management Support"
294 Select if you want MMU-based virtualised addressing space
295 support by paged memory management. If unsure, say 'Y'.
297 config ARCH_MMAP_RND_BITS_MIN
300 config ARCH_MMAP_RND_BITS_MAX
301 default 14 if PAGE_OFFSET=0x40000000
302 default 15 if PAGE_OFFSET=0x80000000
306 # The "ARM system type" choice list is ordered alphabetically by option
307 # text. Please add new entries in the option alphabetic order.
310 prompt "ARM system type"
311 default ARM_SINGLE_ARMV7M if !MMU
312 default ARCH_MULTIPLATFORM if MMU
314 config ARCH_MULTIPLATFORM
315 bool "Allow multiple platforms to be selected"
317 select ARM_HAS_SG_CHAIN
318 select ARM_PATCH_PHYS_VIRT
322 select GENERIC_CLOCKEVENTS
323 select GENERIC_IRQ_MULTI_HANDLER
325 select PCI_DOMAINS_GENERIC if PCI
329 config ARM_SINGLE_ARMV7M
330 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
337 select GENERIC_CLOCKEVENTS
344 select ARCH_USES_GETTIMEOFFSET
347 select NEED_MACH_IO_H
348 select NEED_MACH_MEMORY_H
351 This is an evaluation board for the StrongARM processor available
352 from Digital. It has limited hardware on-board, including an
353 Ethernet interface, two PCMCIA sockets, two serial ports and a
358 select ARCH_SPARSEMEM_ENABLE
360 imply ARM_PATCH_PHYS_VIRT
366 select GENERIC_CLOCKEVENTS
369 This enables support for the Cirrus EP93xx series of CPUs.
371 config ARCH_FOOTBRIDGE
375 select GENERIC_CLOCKEVENTS
377 select NEED_MACH_IO_H if !MMU
378 select NEED_MACH_MEMORY_H
380 Support for systems based on the DC21285 companion chip
381 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
389 select NEED_RET_TO_USER
393 Support for Intel's 80219 and IOP32X (XScale) family of
399 select ARCH_HAS_DMA_SET_COHERENT_MASK
400 select ARCH_SUPPORTS_BIG_ENDIAN
402 select DMABOUNCE if PCI
403 select GENERIC_CLOCKEVENTS
404 select GENERIC_IRQ_MULTI_HANDLER
410 select NEED_MACH_IO_H
411 select USB_EHCI_BIG_ENDIAN_DESC
412 select USB_EHCI_BIG_ENDIAN_MMIO
414 Support for Intel's IXP4XX (XScale) family of processors.
419 select GENERIC_CLOCKEVENTS
420 select GENERIC_IRQ_MULTI_HANDLER
426 select PLAT_ORION_LEGACY
428 select PM_GENERIC_DOMAINS if PM
430 Support for the Marvell Dove SoC 88AP510
433 bool "PXA2xx/PXA3xx-based"
436 select ARM_CPU_SUSPEND if PM
443 select CPU_XSCALE if !CPU_XSC3
444 select GENERIC_CLOCKEVENTS
445 select GENERIC_IRQ_MULTI_HANDLER
453 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
459 select ARCH_MAY_HAVE_PC_FDC
460 select ARCH_SPARSEMEM_ENABLE
461 select ARM_HAS_SG_CHAIN
465 select HAVE_PATA_PLATFORM
467 select NEED_MACH_IO_H
468 select NEED_MACH_MEMORY_H
471 On the Acorn Risc-PC, Linux can support the internal IDE disk and
472 CD-ROM interface, serial and parallel port, and the floppy drive.
477 select ARCH_SPARSEMEM_ENABLE
481 select TIMER_OF if OF
485 select GENERIC_CLOCKEVENTS
486 select GENERIC_IRQ_MULTI_HANDLER
491 select NEED_MACH_MEMORY_H
494 Support for StrongARM 11x0 based boards.
497 bool "Samsung S3C24XX SoCs"
500 select CLKSRC_SAMSUNG_PWM
501 select GENERIC_CLOCKEVENTS
504 select GENERIC_IRQ_MULTI_HANDLER
505 select HAVE_S3C2410_I2C if I2C
506 select HAVE_S3C2410_WATCHDOG if WATCHDOG
507 select HAVE_S3C_RTC if RTC_CLASS
508 select NEED_MACH_IO_H
512 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
513 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
514 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
515 Samsung SMDK2410 development board (and derivatives).
520 select ARCH_HAS_HOLES_MEMORYMODEL
524 select GENERIC_CLOCKEVENTS
525 select GENERIC_IRQ_CHIP
526 select GENERIC_IRQ_MULTI_HANDLER
530 select NEED_MACH_IO_H if PCCARD
531 select NEED_MACH_MEMORY_H
534 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
538 menu "Multiple platform selection"
539 depends on ARCH_MULTIPLATFORM
541 comment "CPU Core family selection"
544 bool "ARMv4 based platforms (FA526)"
545 depends on !ARCH_MULTI_V6_V7
546 select ARCH_MULTI_V4_V5
549 config ARCH_MULTI_V4T
550 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
551 depends on !ARCH_MULTI_V6_V7
552 select ARCH_MULTI_V4_V5
553 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
554 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
555 CPU_ARM925T || CPU_ARM940T)
558 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
559 depends on !ARCH_MULTI_V6_V7
560 select ARCH_MULTI_V4_V5
561 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
562 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
563 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
565 config ARCH_MULTI_V4_V5
569 bool "ARMv6 based platforms (ARM11)"
570 select ARCH_MULTI_V6_V7
574 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
576 select ARCH_MULTI_V6_V7
580 config ARCH_MULTI_V6_V7
582 select MIGHT_HAVE_CACHE_L2X0
584 config ARCH_MULTI_CPU_AUTO
585 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
591 bool "Dummy Virtual Machine"
592 depends on ARCH_MULTI_V7
595 select ARM_GIC_V2M if PCI
597 select ARM_GIC_V3_ITS if PCI
599 select HAVE_ARM_ARCH_TIMER
600 select ARCH_SUPPORTS_BIG_ENDIAN
603 # This is sorted alphabetically by mach-* pathname. However, plat-*
604 # Kconfigs may be included either alphabetically (according to the
605 # plat- suffix) or along side the corresponding mach-* source.
607 source "arch/arm/mach-actions/Kconfig"
609 source "arch/arm/mach-alpine/Kconfig"
611 source "arch/arm/mach-artpec/Kconfig"
613 source "arch/arm/mach-asm9260/Kconfig"
615 source "arch/arm/mach-aspeed/Kconfig"
617 source "arch/arm/mach-at91/Kconfig"
619 source "arch/arm/mach-axxia/Kconfig"
621 source "arch/arm/mach-bcm/Kconfig"
623 source "arch/arm/mach-berlin/Kconfig"
625 source "arch/arm/mach-clps711x/Kconfig"
627 source "arch/arm/mach-cns3xxx/Kconfig"
629 source "arch/arm/mach-davinci/Kconfig"
631 source "arch/arm/mach-digicolor/Kconfig"
633 source "arch/arm/mach-dove/Kconfig"
635 source "arch/arm/mach-ep93xx/Kconfig"
637 source "arch/arm/mach-exynos/Kconfig"
638 source "arch/arm/plat-samsung/Kconfig"
640 source "arch/arm/mach-footbridge/Kconfig"
642 source "arch/arm/mach-gemini/Kconfig"
644 source "arch/arm/mach-highbank/Kconfig"
646 source "arch/arm/mach-hisi/Kconfig"
648 source "arch/arm/mach-imx/Kconfig"
650 source "arch/arm/mach-integrator/Kconfig"
652 source "arch/arm/mach-iop32x/Kconfig"
654 source "arch/arm/mach-ixp4xx/Kconfig"
656 source "arch/arm/mach-keystone/Kconfig"
658 source "arch/arm/mach-lpc32xx/Kconfig"
660 source "arch/arm/mach-mediatek/Kconfig"
662 source "arch/arm/mach-meson/Kconfig"
664 source "arch/arm/mach-milbeaut/Kconfig"
666 source "arch/arm/mach-mmp/Kconfig"
668 source "arch/arm/mach-moxart/Kconfig"
670 source "arch/arm/mach-mv78xx0/Kconfig"
672 source "arch/arm/mach-mvebu/Kconfig"
674 source "arch/arm/mach-mxs/Kconfig"
676 source "arch/arm/mach-nomadik/Kconfig"
678 source "arch/arm/mach-npcm/Kconfig"
680 source "arch/arm/mach-nspire/Kconfig"
682 source "arch/arm/plat-omap/Kconfig"
684 source "arch/arm/mach-omap1/Kconfig"
686 source "arch/arm/mach-omap2/Kconfig"
688 source "arch/arm/mach-orion5x/Kconfig"
690 source "arch/arm/mach-oxnas/Kconfig"
692 source "arch/arm/mach-picoxcell/Kconfig"
694 source "arch/arm/mach-prima2/Kconfig"
696 source "arch/arm/mach-pxa/Kconfig"
697 source "arch/arm/plat-pxa/Kconfig"
699 source "arch/arm/mach-qcom/Kconfig"
701 source "arch/arm/mach-rda/Kconfig"
703 source "arch/arm/mach-realview/Kconfig"
705 source "arch/arm/mach-rockchip/Kconfig"
707 source "arch/arm/mach-s3c24xx/Kconfig"
709 source "arch/arm/mach-s3c64xx/Kconfig"
711 source "arch/arm/mach-s5pv210/Kconfig"
713 source "arch/arm/mach-sa1100/Kconfig"
715 source "arch/arm/mach-shmobile/Kconfig"
717 source "arch/arm/mach-socfpga/Kconfig"
719 source "arch/arm/mach-spear/Kconfig"
721 source "arch/arm/mach-sti/Kconfig"
723 source "arch/arm/mach-stm32/Kconfig"
725 source "arch/arm/mach-sunxi/Kconfig"
727 source "arch/arm/mach-tango/Kconfig"
729 source "arch/arm/mach-tegra/Kconfig"
731 source "arch/arm/mach-u300/Kconfig"
733 source "arch/arm/mach-uniphier/Kconfig"
735 source "arch/arm/mach-ux500/Kconfig"
737 source "arch/arm/mach-versatile/Kconfig"
739 source "arch/arm/mach-vexpress/Kconfig"
740 source "arch/arm/plat-versatile/Kconfig"
742 source "arch/arm/mach-vt8500/Kconfig"
744 source "arch/arm/mach-zx/Kconfig"
746 source "arch/arm/mach-zynq/Kconfig"
748 # ARMv7-M architecture
750 bool "Energy Micro efm32"
751 depends on ARM_SINGLE_ARMV7M
754 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
758 bool "NXP LPC18xx/LPC43xx"
759 depends on ARM_SINGLE_ARMV7M
760 select ARCH_HAS_RESET_CONTROLLER
762 select CLKSRC_LPC32XX
765 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
766 high performance microcontrollers.
769 bool "ARM MPS2 platform"
770 depends on ARM_SINGLE_ARMV7M
774 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
775 with a range of available cores like Cortex-M3/M4/M7.
777 Please, note that depends which Application Note is used memory map
778 for the platform may vary, so adjustment of RAM base might be needed.
780 # Definitions to make life easier
786 select GENERIC_CLOCKEVENTS
792 select GENERIC_IRQ_CHIP
795 config PLAT_ORION_LEGACY
802 config PLAT_VERSATILE
805 source "arch/arm/mm/Kconfig"
808 bool "Enable iWMMXt support"
809 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
810 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
812 Enable support for iWMMXt context switching at run time if
813 running on a CPU that supports it.
816 source "arch/arm/Kconfig-nommu"
819 config PJ4B_ERRATA_4742
820 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
821 depends on CPU_PJ4B && MACH_ARMADA_370
824 When coming out of either a Wait for Interrupt (WFI) or a Wait for
825 Event (WFE) IDLE states, a specific timing sensitivity exists between
826 the retiring WFI/WFE instructions and the newly issued subsequent
827 instructions. This sensitivity can result in a CPU hang scenario.
829 The software must insert either a Data Synchronization Barrier (DSB)
830 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
833 config ARM_ERRATA_326103
834 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
837 Executing a SWP instruction to read-only memory does not set bit 11
838 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
839 treat the access as a read, preventing a COW from occurring and
840 causing the faulting task to livelock.
842 config ARM_ERRATA_411920
843 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
844 depends on CPU_V6 || CPU_V6K
846 Invalidation of the Instruction Cache operation can
847 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
848 It does not affect the MPCore. This option enables the ARM Ltd.
849 recommended workaround.
851 config ARM_ERRATA_430973
852 bool "ARM errata: Stale prediction on replaced interworking branch"
855 This option enables the workaround for the 430973 Cortex-A8
856 r1p* erratum. If a code sequence containing an ARM/Thumb
857 interworking branch is replaced with another code sequence at the
858 same virtual address, whether due to self-modifying code or virtual
859 to physical address re-mapping, Cortex-A8 does not recover from the
860 stale interworking branch prediction. This results in Cortex-A8
861 executing the new code sequence in the incorrect ARM or Thumb state.
862 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
863 and also flushes the branch target cache at every context switch.
864 Note that setting specific bits in the ACTLR register may not be
865 available in non-secure mode.
867 config ARM_ERRATA_458693
868 bool "ARM errata: Processor deadlock when a false hazard is created"
870 depends on !ARCH_MULTIPLATFORM
872 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
873 erratum. For very specific sequences of memory operations, it is
874 possible for a hazard condition intended for a cache line to instead
875 be incorrectly associated with a different cache line. This false
876 hazard might then cause a processor deadlock. The workaround enables
877 the L1 caching of the NEON accesses and disables the PLD instruction
878 in the ACTLR register. Note that setting specific bits in the ACTLR
879 register may not be available in non-secure mode.
881 config ARM_ERRATA_460075
882 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
884 depends on !ARCH_MULTIPLATFORM
886 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
887 erratum. Any asynchronous access to the L2 cache may encounter a
888 situation in which recent store transactions to the L2 cache are lost
889 and overwritten with stale memory contents from external memory. The
890 workaround disables the write-allocate mode for the L2 cache via the
891 ACTLR register. Note that setting specific bits in the ACTLR register
892 may not be available in non-secure mode.
894 config ARM_ERRATA_742230
895 bool "ARM errata: DMB operation may be faulty"
896 depends on CPU_V7 && SMP
897 depends on !ARCH_MULTIPLATFORM
899 This option enables the workaround for the 742230 Cortex-A9
900 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
901 between two write operations may not ensure the correct visibility
902 ordering of the two writes. This workaround sets a specific bit in
903 the diagnostic register of the Cortex-A9 which causes the DMB
904 instruction to behave as a DSB, ensuring the correct behaviour of
907 config ARM_ERRATA_742231
908 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
909 depends on CPU_V7 && SMP
910 depends on !ARCH_MULTIPLATFORM
912 This option enables the workaround for the 742231 Cortex-A9
913 (r2p0..r2p2) erratum. Under certain conditions, specific to the
914 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
915 accessing some data located in the same cache line, may get corrupted
916 data due to bad handling of the address hazard when the line gets
917 replaced from one of the CPUs at the same time as another CPU is
918 accessing it. This workaround sets specific bits in the diagnostic
919 register of the Cortex-A9 which reduces the linefill issuing
920 capabilities of the processor.
922 config ARM_ERRATA_643719
923 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
924 depends on CPU_V7 && SMP
927 This option enables the workaround for the 643719 Cortex-A9 (prior to
928 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
929 register returns zero when it should return one. The workaround
930 corrects this value, ensuring cache maintenance operations which use
931 it behave as intended and avoiding data corruption.
933 config ARM_ERRATA_720789
934 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
937 This option enables the workaround for the 720789 Cortex-A9 (prior to
938 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
939 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
940 As a consequence of this erratum, some TLB entries which should be
941 invalidated are not, resulting in an incoherency in the system page
942 tables. The workaround changes the TLB flushing routines to invalidate
943 entries regardless of the ASID.
945 config ARM_ERRATA_743622
946 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
948 depends on !ARCH_MULTIPLATFORM
950 This option enables the workaround for the 743622 Cortex-A9
951 (r2p*) erratum. Under very rare conditions, a faulty
952 optimisation in the Cortex-A9 Store Buffer may lead to data
953 corruption. This workaround sets a specific bit in the diagnostic
954 register of the Cortex-A9 which disables the Store Buffer
955 optimisation, preventing the defect from occurring. This has no
956 visible impact on the overall performance or power consumption of the
959 config ARM_ERRATA_751472
960 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
962 depends on !ARCH_MULTIPLATFORM
964 This option enables the workaround for the 751472 Cortex-A9 (prior
965 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
966 completion of a following broadcasted operation if the second
967 operation is received by a CPU before the ICIALLUIS has completed,
968 potentially leading to corrupted entries in the cache or TLB.
970 config ARM_ERRATA_754322
971 bool "ARM errata: possible faulty MMU translations following an ASID switch"
974 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
975 r3p*) erratum. A speculative memory access may cause a page table walk
976 which starts prior to an ASID switch but completes afterwards. This
977 can populate the micro-TLB with a stale entry which may be hit with
978 the new ASID. This workaround places two dsb instructions in the mm
979 switching code so that no page table walks can cross the ASID switch.
981 config ARM_ERRATA_754327
982 bool "ARM errata: no automatic Store Buffer drain"
983 depends on CPU_V7 && SMP
985 This option enables the workaround for the 754327 Cortex-A9 (prior to
986 r2p0) erratum. The Store Buffer does not have any automatic draining
987 mechanism and therefore a livelock may occur if an external agent
988 continuously polls a memory location waiting to observe an update.
989 This workaround defines cpu_relax() as smp_mb(), preventing correctly
990 written polling loops from denying visibility of updates to memory.
992 config ARM_ERRATA_364296
993 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
996 This options enables the workaround for the 364296 ARM1136
997 r0p2 erratum (possible cache data corruption with
998 hit-under-miss enabled). It sets the undocumented bit 31 in
999 the auxiliary control register and the FI bit in the control
1000 register, thus disabling hit-under-miss without putting the
1001 processor into full low interrupt latency mode. ARM11MPCore
1004 config ARM_ERRATA_764369
1005 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1006 depends on CPU_V7 && SMP
1008 This option enables the workaround for erratum 764369
1009 affecting Cortex-A9 MPCore with two or more processors (all
1010 current revisions). Under certain timing circumstances, a data
1011 cache line maintenance operation by MVA targeting an Inner
1012 Shareable memory region may fail to proceed up to either the
1013 Point of Coherency or to the Point of Unification of the
1014 system. This workaround adds a DSB instruction before the
1015 relevant cache maintenance functions and sets a specific bit
1016 in the diagnostic control register of the SCU.
1018 config ARM_ERRATA_775420
1019 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1022 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1023 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1024 operation aborts with MMU exception, it might cause the processor
1025 to deadlock. This workaround puts DSB before executing ISB if
1026 an abort may occur on cache maintenance.
1028 config ARM_ERRATA_798181
1029 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1030 depends on CPU_V7 && SMP
1032 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1033 adequately shooting down all use of the old entries. This
1034 option enables the Linux kernel workaround for this erratum
1035 which sends an IPI to the CPUs that are running the same ASID
1036 as the one being invalidated.
1038 config ARM_ERRATA_773022
1039 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1042 This option enables the workaround for the 773022 Cortex-A15
1043 (up to r0p4) erratum. In certain rare sequences of code, the
1044 loop buffer may deliver incorrect instructions. This
1045 workaround disables the loop buffer to avoid the erratum.
1047 config ARM_ERRATA_818325_852422
1048 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1051 This option enables the workaround for:
1052 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1053 instruction might deadlock. Fixed in r0p1.
1054 - Cortex-A12 852422: Execution of a sequence of instructions might
1055 lead to either a data corruption or a CPU deadlock. Not fixed in
1056 any Cortex-A12 cores yet.
1057 This workaround for all both errata involves setting bit[12] of the
1058 Feature Register. This bit disables an optimisation applied to a
1059 sequence of 2 instructions that use opposing condition codes.
1061 config ARM_ERRATA_821420
1062 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1065 This option enables the workaround for the 821420 Cortex-A12
1066 (all revs) erratum. In very rare timing conditions, a sequence
1067 of VMOV to Core registers instructions, for which the second
1068 one is in the shadow of a branch or abort, can lead to a
1069 deadlock when the VMOV instructions are issued out-of-order.
1071 config ARM_ERRATA_825619
1072 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1075 This option enables the workaround for the 825619 Cortex-A12
1076 (all revs) erratum. Within rare timing constraints, executing a
1077 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1078 and Device/Strongly-Ordered loads and stores might cause deadlock
1080 config ARM_ERRATA_857271
1081 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1084 This option enables the workaround for the 857271 Cortex-A12
1085 (all revs) erratum. Under very rare timing conditions, the CPU might
1086 hang. The workaround is expected to have a < 1% performance impact.
1088 config ARM_ERRATA_852421
1089 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1092 This option enables the workaround for the 852421 Cortex-A17
1093 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1094 execution of a DMB ST instruction might fail to properly order
1095 stores from GroupA and stores from GroupB.
1097 config ARM_ERRATA_852423
1098 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1101 This option enables the workaround for:
1102 - Cortex-A17 852423: Execution of a sequence of instructions might
1103 lead to either a data corruption or a CPU deadlock. Not fixed in
1104 any Cortex-A17 cores yet.
1105 This is identical to Cortex-A12 erratum 852422. It is a separate
1106 config option from the A12 erratum due to the way errata are checked
1109 config ARM_ERRATA_857272
1110 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1113 This option enables the workaround for the 857272 Cortex-A17 erratum.
1114 This erratum is not known to be fixed in any A17 revision.
1115 This is identical to Cortex-A12 erratum 857271. It is a separate
1116 config option from the A12 erratum due to the way errata are checked
1121 source "arch/arm/common/Kconfig"
1128 Find out whether you have ISA slots on your motherboard. ISA is the
1129 name of a bus system, i.e. the way the CPU talks to the other stuff
1130 inside your box. Other bus systems are PCI, EISA, MicroChannel
1131 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1132 newer boards don't support it. If you have ISA, say Y, otherwise N.
1134 # Select ISA DMA controller support
1139 # Select ISA DMA interface
1143 config PCI_NANOENGINE
1144 bool "BSE nanoEngine PCI support"
1145 depends on SA1100_NANOENGINE
1147 Enable PCI on the BSE nanoEngine board.
1149 config PCI_HOST_ITE8152
1151 depends on PCI && MACH_ARMCORE
1155 config ARM_ERRATA_814220
1156 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1159 The v7 ARM states that all cache and branch predictor maintenance
1160 operations that do not specify an address execute, relative to
1161 each other, in program order.
1162 However, because of this erratum, an L2 set/way cache maintenance
1163 operation can overtake an L1 set/way cache maintenance operation.
1164 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1169 menu "Kernel Features"
1174 This option should be selected by machines which have an SMP-
1177 The only effect of this option is to make the SMP-related
1178 options available to the user for configuration.
1181 bool "Symmetric Multi-Processing"
1182 depends on CPU_V6K || CPU_V7
1183 depends on GENERIC_CLOCKEVENTS
1185 depends on MMU || ARM_MPU
1188 This enables support for systems with more than one CPU. If you have
1189 a system with only one CPU, say N. If you have a system with more
1190 than one CPU, say Y.
1192 If you say N here, the kernel will run on uni- and multiprocessor
1193 machines, but will use only one CPU of a multiprocessor machine. If
1194 you say Y here, the kernel will run on many, but not all,
1195 uniprocessor machines. On a uniprocessor machine, the kernel
1196 will run faster if you say N here.
1198 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1199 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1200 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1202 If you don't know what to do here, say N.
1205 bool "Allow booting SMP kernel on uniprocessor systems"
1206 depends on SMP && !XIP_KERNEL && MMU
1209 SMP kernels contain instructions which fail on non-SMP processors.
1210 Enabling this option allows the kernel to modify itself to make
1211 these instructions safe. Disabling it allows about 1K of space
1214 If you don't know what to do here, say Y.
1216 config ARM_CPU_TOPOLOGY
1217 bool "Support cpu topology definition"
1218 depends on SMP && CPU_V7
1221 Support ARM cpu topology definition. The MPIDR register defines
1222 affinity between processors which is then used to describe the cpu
1223 topology of an ARM System.
1226 bool "Multi-core scheduler support"
1227 depends on ARM_CPU_TOPOLOGY
1229 Multi-core scheduler support improves the CPU scheduler's decision
1230 making when dealing with multi-core CPU chips at a cost of slightly
1231 increased overhead in some places. If unsure say N here.
1234 bool "SMT scheduler support"
1235 depends on ARM_CPU_TOPOLOGY
1237 Improves the CPU scheduler's decision making when dealing with
1238 MultiThreading at a cost of slightly increased overhead in some
1239 places. If unsure say N here.
1244 This option enables support for the ARM snoop control unit
1246 config HAVE_ARM_ARCH_TIMER
1247 bool "Architected timer support"
1249 select ARM_ARCH_TIMER
1250 select GENERIC_CLOCKEVENTS
1252 This option enables support for the ARM architected timer
1257 This options enables support for the ARM timer and watchdog unit
1260 bool "Multi-Cluster Power Management"
1261 depends on CPU_V7 && SMP
1263 This option provides the common power management infrastructure
1264 for (multi-)cluster based systems, such as big.LITTLE based
1267 config MCPM_QUAD_CLUSTER
1271 To avoid wasting resources unnecessarily, MCPM only supports up
1272 to 2 clusters by default.
1273 Platforms with 3 or 4 clusters that use MCPM must select this
1274 option to allow the additional clusters to be managed.
1277 bool "big.LITTLE support (Experimental)"
1278 depends on CPU_V7 && SMP
1281 This option enables support selections for the big.LITTLE
1282 system architecture.
1285 bool "big.LITTLE switcher support"
1286 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1289 The big.LITTLE "switcher" provides the core functionality to
1290 transparently handle transition between a cluster of A15's
1291 and a cluster of A7's in a big.LITTLE system.
1293 config BL_SWITCHER_DUMMY_IF
1294 tristate "Simple big.LITTLE switcher user interface"
1295 depends on BL_SWITCHER && DEBUG_KERNEL
1297 This is a simple and dummy char dev interface to control
1298 the big.LITTLE switcher core code. It is meant for
1299 debugging purposes only.
1302 prompt "Memory split"
1306 Select the desired split between kernel and user memory.
1308 If you are not absolutely sure what you are doing, leave this
1312 bool "3G/1G user/kernel split"
1313 config VMSPLIT_3G_OPT
1314 depends on !ARM_LPAE
1315 bool "3G/1G user/kernel split (for full 1G low memory)"
1317 bool "2G/2G user/kernel split"
1319 bool "1G/3G user/kernel split"
1324 default PHYS_OFFSET if !MMU
1325 default 0x40000000 if VMSPLIT_1G
1326 default 0x80000000 if VMSPLIT_2G
1327 default 0xB0000000 if VMSPLIT_3G_OPT
1331 int "Maximum number of CPUs (2-32)"
1337 bool "Support for hot-pluggable CPUs"
1339 select GENERIC_IRQ_MIGRATION
1341 Say Y here to experiment with turning CPUs off and on. CPUs
1342 can be controlled through /sys/devices/system/cpu.
1345 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1346 depends on HAVE_ARM_SMCCC
1349 Say Y here if you want Linux to communicate with system firmware
1350 implementing the PSCI specification for CPU-centric power
1351 management operations described in ARM document number ARM DEN
1352 0022A ("Power State Coordination Interface System Software on
1355 # The GPIO number here must be sorted by descending number. In case of
1356 # a multiplatform kernel, we just want the highest value required by the
1357 # selected platforms.
1360 default 2048 if ARCH_SOCFPGA
1361 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1363 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1364 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1365 default 416 if ARCH_SUNXI
1366 default 392 if ARCH_U8500
1367 default 352 if ARCH_VT8500
1368 default 288 if ARCH_ROCKCHIP
1369 default 264 if MACH_H4700
1372 Maximum number of GPIOs in the system.
1374 If unsure, leave the default value.
1378 default 200 if ARCH_EBSA110
1379 default 128 if SOC_AT91RM9200
1383 depends on HZ_FIXED = 0
1384 prompt "Timer frequency"
1408 default HZ_FIXED if HZ_FIXED != 0
1409 default 100 if HZ_100
1410 default 200 if HZ_200
1411 default 250 if HZ_250
1412 default 300 if HZ_300
1413 default 500 if HZ_500
1417 def_bool HIGH_RES_TIMERS
1419 config THUMB2_KERNEL
1420 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1421 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1422 default y if CPU_THUMBONLY
1425 By enabling this option, the kernel will be compiled in
1430 config THUMB2_AVOID_R_ARM_THM_JUMP11
1431 bool "Work around buggy Thumb-2 short branch relocations in gas"
1432 depends on THUMB2_KERNEL && MODULES
1435 Various binutils versions can resolve Thumb-2 branches to
1436 locally-defined, preemptible global symbols as short-range "b.n"
1437 branch instructions.
1439 This is a problem, because there's no guarantee the final
1440 destination of the symbol, or any candidate locations for a
1441 trampoline, are within range of the branch. For this reason, the
1442 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1443 relocation in modules at all, and it makes little sense to add
1446 The symptom is that the kernel fails with an "unsupported
1447 relocation" error when loading some modules.
1449 Until fixed tools are available, passing
1450 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1451 code which hits this problem, at the cost of a bit of extra runtime
1452 stack usage in some cases.
1454 The problem is described in more detail at:
1455 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1457 Only Thumb-2 kernels are affected.
1459 Unless you are sure your tools don't have this problem, say Y.
1461 config ARM_PATCH_IDIV
1462 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1463 depends on CPU_32v7 && !XIP_KERNEL
1466 The ARM compiler inserts calls to __aeabi_idiv() and
1467 __aeabi_uidiv() when it needs to perform division on signed
1468 and unsigned integers. Some v7 CPUs have support for the sdiv
1469 and udiv instructions that can be used to implement those
1472 Enabling this option allows the kernel to modify itself to
1473 replace the first two instructions of these library functions
1474 with the sdiv or udiv plus "bx lr" instructions when the CPU
1475 it is running on supports them. Typically this will be faster
1476 and less power intensive than running the original library
1477 code to do integer division.
1480 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1481 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1482 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1484 This option allows for the kernel to be compiled using the latest
1485 ARM ABI (aka EABI). This is only useful if you are using a user
1486 space environment that is also compiled with EABI.
1488 Since there are major incompatibilities between the legacy ABI and
1489 EABI, especially with regard to structure member alignment, this
1490 option also changes the kernel syscall calling convention to
1491 disambiguate both ABIs and allow for backward compatibility support
1492 (selected with CONFIG_OABI_COMPAT).
1494 To use this you need GCC version 4.0.0 or later.
1497 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1498 depends on AEABI && !THUMB2_KERNEL
1500 This option preserves the old syscall interface along with the
1501 new (ARM EABI) one. It also provides a compatibility layer to
1502 intercept syscalls that have structure arguments which layout
1503 in memory differs between the legacy ABI and the new ARM EABI
1504 (only for non "thumb" binaries). This option adds a tiny
1505 overhead to all syscalls and produces a slightly larger kernel.
1507 The seccomp filter system will not be available when this is
1508 selected, since there is no way yet to sensibly distinguish
1509 between calling conventions during filtering.
1511 If you know you'll be using only pure EABI user space then you
1512 can say N here. If this option is not selected and you attempt
1513 to execute a legacy ABI binary then the result will be
1514 UNPREDICTABLE (in fact it can be predicted that it won't work
1515 at all). If in doubt say N.
1517 config ARCH_HAS_HOLES_MEMORYMODEL
1520 config ARCH_SPARSEMEM_ENABLE
1523 config ARCH_SPARSEMEM_DEFAULT
1524 def_bool ARCH_SPARSEMEM_ENABLE
1526 config HAVE_ARCH_PFN_VALID
1527 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1530 bool "High Memory Support"
1533 The address space of ARM processors is only 4 Gigabytes large
1534 and it has to accommodate user address space, kernel address
1535 space as well as some memory mapped IO. That means that, if you
1536 have a large amount of physical memory and/or IO, not all of the
1537 memory can be "permanently mapped" by the kernel. The physical
1538 memory that is not permanently mapped is called "high memory".
1540 Depending on the selected kernel/user memory split, minimum
1541 vmalloc space and actual amount of RAM, you may not need this
1542 option which should result in a slightly faster kernel.
1547 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1551 The VM uses one page of physical memory for each page table.
1552 For systems with a lot of processes, this can use a lot of
1553 precious low memory, eventually leading to low memory being
1554 consumed by page tables. Setting this option will allow
1555 user-space 2nd level page tables to reside in high memory.
1557 config CPU_SW_DOMAIN_PAN
1558 bool "Enable use of CPU domains to implement privileged no-access"
1559 depends on MMU && !ARM_LPAE
1562 Increase kernel security by ensuring that normal kernel accesses
1563 are unable to access userspace addresses. This can help prevent
1564 use-after-free bugs becoming an exploitable privilege escalation
1565 by ensuring that magic values (such as LIST_POISON) will always
1566 fault when dereferenced.
1568 CPUs with low-vector mappings use a best-efforts implementation.
1569 Their lower 1MB needs to remain accessible for the vectors, but
1570 the remainder of userspace will become appropriately inaccessible.
1572 config HW_PERF_EVENTS
1576 config SYS_SUPPORTS_HUGETLBFS
1580 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1584 config ARCH_WANT_GENERAL_HUGETLB
1587 config ARM_MODULE_PLTS
1588 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1592 Allocate PLTs when loading modules so that jumps and calls whose
1593 targets are too far away for their relative offsets to be encoded
1594 in the instructions themselves can be bounced via veneers in the
1595 module's PLT. This allows modules to be allocated in the generic
1596 vmalloc area after the dedicated module memory area has been
1597 exhausted. The modules will use slightly more memory, but after
1598 rounding up to page size, the actual memory footprint is usually
1601 Disabling this is usually safe for small single-platform
1602 configurations. If unsure, say y.
1604 config FORCE_MAX_ZONEORDER
1605 int "Maximum zone order"
1606 default "12" if SOC_AM33XX
1607 default "9" if SA1111 || ARCH_EFM32
1610 The kernel memory allocator divides physically contiguous memory
1611 blocks into "zones", where each zone is a power of two number of
1612 pages. This option selects the largest power of two that the kernel
1613 keeps in the memory allocator. If you need to allocate very large
1614 blocks of physically contiguous memory, then you may need to
1615 increase this value.
1617 This config option is actually maximum order plus one. For example,
1618 a value of 11 means that the largest free memory block is 2^10 pages.
1620 config ALIGNMENT_TRAP
1622 depends on CPU_CP15_MMU
1623 default y if !ARCH_EBSA110
1624 select HAVE_PROC_CPU if PROC_FS
1626 ARM processors cannot fetch/store information which is not
1627 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1628 address divisible by 4. On 32-bit ARM processors, these non-aligned
1629 fetch/store instructions will be emulated in software if you say
1630 here, which has a severe performance impact. This is necessary for
1631 correct operation of some network protocols. With an IP-only
1632 configuration it is safe to say N, otherwise say Y.
1634 config UACCESS_WITH_MEMCPY
1635 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1637 default y if CPU_FEROCEON
1639 Implement faster copy_to_user and clear_user methods for CPU
1640 cores where a 8-word STM instruction give significantly higher
1641 memory write throughput than a sequence of individual 32bit stores.
1643 A possible side effect is a slight increase in scheduling latency
1644 between threads sharing the same address space if they invoke
1645 such copy operations with large buffers.
1647 However, if the CPU data cache is using a write-allocate mode,
1648 this option is unlikely to provide any performance gain.
1652 prompt "Enable seccomp to safely compute untrusted bytecode"
1654 This kernel feature is useful for number crunching applications
1655 that may need to compute untrusted bytecode during their
1656 execution. By using pipes or other transports made available to
1657 the process as file descriptors supporting the read/write
1658 syscalls, it's possible to isolate those applications in
1659 their own address space using seccomp. Once seccomp is
1660 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1661 and the task is only allowed to execute a few safe syscalls
1662 defined by each seccomp mode.
1665 bool "Enable paravirtualization code"
1667 This changes the kernel so it can modify itself when it is run
1668 under a hypervisor, potentially improving performance significantly
1669 over full virtualization.
1671 config PARAVIRT_TIME_ACCOUNTING
1672 bool "Paravirtual steal time accounting"
1675 Select this option to enable fine granularity task steal time
1676 accounting. Time spent executing other tasks in parallel with
1677 the current vCPU is discounted from the vCPU power. To account for
1678 that, there can be a small performance impact.
1680 If in doubt, say N here.
1687 bool "Xen guest support on ARM"
1688 depends on ARM && AEABI && OF
1689 depends on CPU_V7 && !CPU_V6
1690 depends on !GENERIC_ATOMIC64
1692 select ARCH_DMA_ADDR_T_64BIT
1698 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1700 config STACKPROTECTOR_PER_TASK
1701 bool "Use a unique stack canary value for each task"
1702 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1703 select GCC_PLUGIN_ARM_SSP_PER_TASK
1706 Due to the fact that GCC uses an ordinary symbol reference from
1707 which to load the value of the stack canary, this value can only
1708 change at reboot time on SMP systems, and all tasks running in the
1709 kernel's address space are forced to use the same canary value for
1710 the entire duration that the system is up.
1712 Enable this option to switch to a different method that uses a
1713 different canary value for each task.
1720 bool "Flattened Device Tree support"
1724 Include support for flattened device tree machine descriptions.
1727 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1730 This is the traditional way of passing data to the kernel at boot
1731 time. If you are solely relying on the flattened device tree (or
1732 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1733 to remove ATAGS support from your kernel binary. If unsure,
1736 config DEPRECATED_PARAM_STRUCT
1737 bool "Provide old way to pass kernel parameters"
1740 This was deprecated in 2001 and announced to live on for 5 years.
1741 Some old boot loaders still use this way.
1743 # Compressed boot loader in ROM. Yes, we really want to ask about
1744 # TEXT and BSS so we preserve their values in the config files.
1745 config ZBOOT_ROM_TEXT
1746 hex "Compressed ROM boot loader base address"
1749 The physical address at which the ROM-able zImage is to be
1750 placed in the target. Platforms which normally make use of
1751 ROM-able zImage formats normally set this to a suitable
1752 value in their defconfig file.
1754 If ZBOOT_ROM is not enabled, this has no effect.
1756 config ZBOOT_ROM_BSS
1757 hex "Compressed ROM boot loader BSS address"
1760 The base address of an area of read/write memory in the target
1761 for the ROM-able zImage which must be available while the
1762 decompressor is running. It must be large enough to hold the
1763 entire decompressed kernel plus an additional 128 KiB.
1764 Platforms which normally make use of ROM-able zImage formats
1765 normally set this to a suitable value in their defconfig file.
1767 If ZBOOT_ROM is not enabled, this has no effect.
1770 bool "Compressed boot loader in ROM/flash"
1771 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1772 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1774 Say Y here if you intend to execute your compressed kernel image
1775 (zImage) directly from ROM or flash. If unsure, say N.
1777 config ARM_APPENDED_DTB
1778 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1781 With this option, the boot code will look for a device tree binary
1782 (DTB) appended to zImage
1783 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1785 This is meant as a backward compatibility convenience for those
1786 systems with a bootloader that can't be upgraded to accommodate
1787 the documented boot protocol using a device tree.
1789 Beware that there is very little in terms of protection against
1790 this option being confused by leftover garbage in memory that might
1791 look like a DTB header after a reboot if no actual DTB is appended
1792 to zImage. Do not leave this option active in a production kernel
1793 if you don't intend to always append a DTB. Proper passing of the
1794 location into r2 of a bootloader provided DTB is always preferable
1797 config ARM_ATAG_DTB_COMPAT
1798 bool "Supplement the appended DTB with traditional ATAG information"
1799 depends on ARM_APPENDED_DTB
1801 Some old bootloaders can't be updated to a DTB capable one, yet
1802 they provide ATAGs with memory configuration, the ramdisk address,
1803 the kernel cmdline string, etc. Such information is dynamically
1804 provided by the bootloader and can't always be stored in a static
1805 DTB. To allow a device tree enabled kernel to be used with such
1806 bootloaders, this option allows zImage to extract the information
1807 from the ATAG list and store it at run time into the appended DTB.
1810 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1811 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1813 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1814 bool "Use bootloader kernel arguments if available"
1816 Uses the command-line options passed by the boot loader instead of
1817 the device tree bootargs property. If the boot loader doesn't provide
1818 any, the device tree bootargs property will be used.
1820 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1821 bool "Extend with bootloader kernel arguments"
1823 The command-line arguments provided by the boot loader will be
1824 appended to the the device tree bootargs property.
1829 string "Default kernel command string"
1832 On some architectures (EBSA110 and CATS), there is currently no way
1833 for the boot loader to pass arguments to the kernel. For these
1834 architectures, you should supply some command-line options at build
1835 time by entering them here. As a minimum, you should specify the
1836 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1839 prompt "Kernel command line type" if CMDLINE != ""
1840 default CMDLINE_FROM_BOOTLOADER
1843 config CMDLINE_FROM_BOOTLOADER
1844 bool "Use bootloader kernel arguments if available"
1846 Uses the command-line options passed by the boot loader. If
1847 the boot loader doesn't provide any, the default kernel command
1848 string provided in CMDLINE will be used.
1850 config CMDLINE_EXTEND
1851 bool "Extend bootloader kernel arguments"
1853 The command-line arguments provided by the boot loader will be
1854 appended to the default kernel command string.
1856 config CMDLINE_FORCE
1857 bool "Always use the default kernel command string"
1859 Always use the default kernel command string, even if the boot
1860 loader passes other arguments to the kernel.
1861 This is useful if you cannot or don't want to change the
1862 command-line options your boot loader passes to the kernel.
1866 bool "Kernel Execute-In-Place from ROM"
1867 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1869 Execute-In-Place allows the kernel to run from non-volatile storage
1870 directly addressable by the CPU, such as NOR flash. This saves RAM
1871 space since the text section of the kernel is not loaded from flash
1872 to RAM. Read-write sections, such as the data section and stack,
1873 are still copied to RAM. The XIP kernel is not compressed since
1874 it has to run directly from flash, so it will take more space to
1875 store it. The flash address used to link the kernel object files,
1876 and for storing it, is configuration dependent. Therefore, if you
1877 say Y here, you must know the proper physical address where to
1878 store the kernel image depending on your own flash memory usage.
1880 Also note that the make target becomes "make xipImage" rather than
1881 "make zImage" or "make Image". The final kernel binary to put in
1882 ROM memory will be arch/arm/boot/xipImage.
1886 config XIP_PHYS_ADDR
1887 hex "XIP Kernel Physical Location"
1888 depends on XIP_KERNEL
1889 default "0x00080000"
1891 This is the physical address in your flash memory the kernel will
1892 be linked for and stored to. This address is dependent on your
1895 config XIP_DEFLATED_DATA
1896 bool "Store kernel .data section compressed in ROM"
1897 depends on XIP_KERNEL
1900 Before the kernel is actually executed, its .data section has to be
1901 copied to RAM from ROM. This option allows for storing that data
1902 in compressed form and decompressed to RAM rather than merely being
1903 copied, saving some precious ROM space. A possible drawback is a
1904 slightly longer boot delay.
1907 bool "Kexec system call (EXPERIMENTAL)"
1908 depends on (!SMP || PM_SLEEP_SMP)
1912 kexec is a system call that implements the ability to shutdown your
1913 current kernel, and to start another kernel. It is like a reboot
1914 but it is independent of the system firmware. And like a reboot
1915 you can start any kernel with it, not just Linux.
1917 It is an ongoing process to be certain the hardware in a machine
1918 is properly shutdown, so do not be surprised if this code does not
1919 initially work for you.
1922 bool "Export atags in procfs"
1923 depends on ATAGS && KEXEC
1926 Should the atags used to boot the kernel be exported in an "atags"
1927 file in procfs. Useful with kexec.
1930 bool "Build kdump crash kernel (EXPERIMENTAL)"
1932 Generate crash dump after being started by kexec. This should
1933 be normally only set in special crash dump kernels which are
1934 loaded in the main kernel with kexec-tools into a specially
1935 reserved region and then later executed after a crash by
1936 kdump/kexec. The crash dump kernel must be compiled to a
1937 memory address not used by the main kernel
1939 For more details see Documentation/admin-guide/kdump/kdump.rst
1941 config AUTO_ZRELADDR
1942 bool "Auto calculation of the decompressed kernel image address"
1944 ZRELADDR is the physical address where the decompressed kernel
1945 image will be placed. If AUTO_ZRELADDR is selected, the address
1946 will be determined at run-time by masking the current IP with
1947 0xf8000000. This assumes the zImage being placed in the first 128MB
1948 from start of memory.
1954 bool "UEFI runtime support"
1955 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1957 select EFI_PARAMS_FROM_FDT
1960 select EFI_RUNTIME_WRAPPERS
1962 This option provides support for runtime services provided
1963 by UEFI firmware (such as non-volatile variables, realtime
1964 clock, and platform reset). A UEFI stub is also provided to
1965 allow the kernel to be booted as an EFI application. This
1966 is only useful for kernels that may run on systems that have
1970 bool "Enable support for SMBIOS (DMI) tables"
1974 This enables SMBIOS/DMI feature for systems.
1976 This option is only useful on systems that have UEFI firmware.
1977 However, even with this option, the resultant kernel should
1978 continue to boot on existing non-UEFI platforms.
1980 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1981 i.e., the the practice of identifying the platform via DMI to
1982 decide whether certain workarounds for buggy hardware and/or
1983 firmware need to be enabled. This would require the DMI subsystem
1984 to be enabled much earlier than we do on ARM, which is non-trivial.
1988 menu "CPU Power Management"
1990 source "drivers/cpufreq/Kconfig"
1992 source "drivers/cpuidle/Kconfig"
1996 menu "Floating point emulation"
1998 comment "At least one emulation must be selected"
2001 bool "NWFPE math emulation"
2002 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2004 Say Y to include the NWFPE floating point emulator in the kernel.
2005 This is necessary to run most binaries. Linux does not currently
2006 support floating point hardware so you need to say Y here even if
2007 your machine has an FPA or floating point co-processor podule.
2009 You may say N here if you are going to load the Acorn FPEmulator
2010 early in the bootup.
2013 bool "Support extended precision"
2014 depends on FPE_NWFPE
2016 Say Y to include 80-bit support in the kernel floating-point
2017 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2018 Note that gcc does not generate 80-bit operations by default,
2019 so in most cases this option only enlarges the size of the
2020 floating point emulator without any good reason.
2022 You almost surely want to say N here.
2025 bool "FastFPE math emulation (EXPERIMENTAL)"
2026 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2028 Say Y here to include the FAST floating point emulator in the kernel.
2029 This is an experimental much faster emulator which now also has full
2030 precision for the mantissa. It does not support any exceptions.
2031 It is very simple, and approximately 3-6 times faster than NWFPE.
2033 It should be sufficient for most programs. It may be not suitable
2034 for scientific calculations, but you have to check this for yourself.
2035 If you do not feel you need a faster FP emulation you should better
2039 bool "VFP-format floating point maths"
2040 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2042 Say Y to include VFP support code in the kernel. This is needed
2043 if your hardware includes a VFP unit.
2045 Please see <file:Documentation/arm/vfp/release-notes.rst> for
2046 release notes and additional status information.
2048 Say N if your target does not have VFP hardware.
2056 bool "Advanced SIMD (NEON) Extension support"
2057 depends on VFPv3 && CPU_V7
2059 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2062 config KERNEL_MODE_NEON
2063 bool "Support for NEON in kernel mode"
2064 depends on NEON && AEABI
2066 Say Y to include support for NEON in kernel mode.
2070 menu "Power management options"
2072 source "kernel/power/Kconfig"
2074 config ARCH_SUSPEND_POSSIBLE
2075 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2076 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2079 config ARM_CPU_SUSPEND
2080 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2081 depends on ARCH_SUSPEND_POSSIBLE
2083 config ARCH_HIBERNATION_POSSIBLE
2086 default y if ARCH_SUSPEND_POSSIBLE
2090 source "drivers/firmware/Kconfig"
2093 source "arch/arm/crypto/Kconfig"
2096 source "arch/arm/kvm/Kconfig"