1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CLOCKSOURCE_DATA
7 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
8 select ARCH_HAS_DEBUG_VIRTUAL if MMU
9 select ARCH_HAS_DEVMEM_IS_ALLOWED
10 select ARCH_HAS_ELF_RANDOMIZE
11 select ARCH_HAS_FORTIFY_SOURCE
13 select ARCH_HAS_MEMBARRIER_SYNC_CORE
14 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
15 select ARCH_HAS_PHYS_TO_DMA
16 select ARCH_HAS_SET_MEMORY
17 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
18 select ARCH_HAS_STRICT_MODULE_RWX if MMU
19 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
20 select ARCH_HAVE_CUSTOM_GPIO_H
21 select ARCH_HAS_GCOV_PROFILE_ALL
22 select ARCH_MIGHT_HAVE_PC_PARPORT
23 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
24 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
25 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
26 select ARCH_SUPPORTS_ATOMIC_RMW
27 select ARCH_USE_BUILTIN_BSWAP
28 select ARCH_USE_CMPXCHG_LOCKREF
29 select ARCH_WANT_IPC_PARSE_VERSION
30 select BUILDTIME_EXTABLE_SORT if MMU
31 select CLONE_BACKWARDS
32 select CPU_PM if SUSPEND || CPU_IDLE
33 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
34 select DMA_REMAP if MMU
36 select EDAC_ATOMIC_SCRUB
37 select GENERIC_ALLOCATOR
38 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
39 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
40 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
41 select GENERIC_CPU_AUTOPROBE
42 select GENERIC_EARLY_IOREMAP
43 select GENERIC_IDLE_POLL_SETUP
44 select GENERIC_IRQ_PROBE
45 select GENERIC_IRQ_SHOW
46 select GENERIC_IRQ_SHOW_LEVEL
47 select GENERIC_PCI_IOMAP
48 select GENERIC_SCHED_CLOCK
49 select GENERIC_SMP_IDLE_THREAD
50 select GENERIC_STRNCPY_FROM_USER
51 select GENERIC_STRNLEN_USER
52 select HANDLE_DOMAIN_IRQ
53 select HARDIRQS_SW_RESEND
54 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
55 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
56 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
57 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
58 select HAVE_ARCH_MMAP_RND_BITS if MMU
59 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
60 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
61 select HAVE_ARCH_TRACEHOOK
62 select HAVE_ARM_SMCCC if CPU_V7
63 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
64 select HAVE_CONTEXT_TRACKING
65 select HAVE_C_RECORDMCOUNT
66 select HAVE_DEBUG_KMEMLEAK
67 select HAVE_DMA_CONTIGUOUS if MMU
68 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
69 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
70 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
71 select HAVE_EXIT_THREAD
72 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
73 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL
74 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
75 select HAVE_GCC_PLUGINS
76 select HAVE_GENERIC_DMA_COHERENT
77 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
78 select HAVE_IDE if PCI || ISA || PCMCIA
79 select HAVE_IRQ_TIME_ACCOUNTING
80 select HAVE_KERNEL_GZIP
81 select HAVE_KERNEL_LZ4
82 select HAVE_KERNEL_LZMA
83 select HAVE_KERNEL_LZO
85 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
86 select HAVE_KRETPROBES if HAVE_KPROBES
87 select HAVE_MOD_ARCH_SPECIFIC
89 select HAVE_OPROFILE if HAVE_PERF_EVENTS
90 select HAVE_OPTPROBES if !THUMB2_KERNEL
91 select HAVE_PERF_EVENTS
93 select HAVE_PERF_USER_STACK_DUMP
94 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE
95 select HAVE_REGS_AND_STACK_ACCESS_API
97 select HAVE_STACKPROTECTOR
98 select HAVE_SYSCALL_TRACEPOINTS
100 select HAVE_VIRT_CPU_ACCOUNTING_GEN
101 select IRQ_FORCED_THREADING
102 select MODULES_USE_ELF_REL
103 select NEED_DMA_MAP_STATE
104 select OF_EARLY_FLATTREE if OF
105 select OF_RESERVED_MEM if OF
107 select OLD_SIGSUSPEND3
108 select PCI_SYSCALL if PCI
109 select PERF_USE_VMALLOC
112 select SYS_SUPPORTS_APM_EMULATION
113 # Above selects are sorted alphabetically; please add new ones
114 # according to that. Thanks.
116 The ARM series is a line of low-power-consumption RISC chip designs
117 licensed by ARM Ltd and targeted at embedded applications and
118 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
119 manufactured, but legacy ARM-based PC hardware remains popular in
120 Europe. There is an ARM Linux project with a web page at
121 <http://www.arm.linux.org.uk/>.
123 config ARM_HAS_SG_CHAIN
126 config ARM_DMA_USE_IOMMU
128 select ARM_HAS_SG_CHAIN
129 select NEED_SG_DMA_LENGTH
133 config ARM_DMA_IOMMU_ALIGNMENT
134 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
138 DMA mapping framework by default aligns all buffers to the smallest
139 PAGE_SIZE order which is greater than or equal to the requested buffer
140 size. This works well for buffers up to a few hundreds kilobytes, but
141 for larger buffers it just a waste of address space. Drivers which has
142 relatively small addressing window (like 64Mib) might run out of
143 virtual space with just a few allocations.
145 With this parameter you can specify the maximum PAGE_SIZE order for
146 DMA IOMMU buffers. Larger buffers will be aligned only to this
147 specified order. The order is expressed as a power of two multiplied
152 config SYS_SUPPORTS_APM_EMULATION
157 select GENERIC_ALLOCATOR
168 config STACKTRACE_SUPPORT
172 config LOCKDEP_SUPPORT
176 config TRACE_IRQFLAGS_SUPPORT
180 config RWSEM_XCHGADD_ALGORITHM
184 config ARCH_HAS_ILOG2_U32
187 config ARCH_HAS_ILOG2_U64
190 config ARCH_HAS_BANDGAP
193 config FIX_EARLYCON_MEM
196 config GENERIC_HWEIGHT
200 config GENERIC_CALIBRATE_DELAY
204 config ARCH_MAY_HAVE_PC_FDC
210 config ARCH_SUPPORTS_UPROBES
213 config ARCH_HAS_DMA_SET_COHERENT_MASK
216 config GENERIC_ISA_DMA
222 config NEED_RET_TO_USER
228 config ARM_PATCH_PHYS_VIRT
229 bool "Patch physical to virtual translations at runtime" if EMBEDDED
231 depends on !XIP_KERNEL && MMU
233 Patch phys-to-virt and virt-to-phys translation functions at
234 boot and module load time according to the position of the
235 kernel in system memory.
237 This can only be used with non-XIP MMU kernels where the base
238 of physical memory is at a 16MB boundary.
240 Only disable this option if you know that you do not require
241 this feature (eg, building a kernel for a single machine) and
242 you need to shrink the kernel to the minimal size.
244 config NEED_MACH_IO_H
247 Select this when mach/io.h is required to provide special
248 definitions for this platform. The need for mach/io.h should
249 be avoided when possible.
251 config NEED_MACH_MEMORY_H
254 Select this when mach/memory.h is required to provide special
255 definitions for this platform. The need for mach/memory.h should
256 be avoided when possible.
259 hex "Physical address of main memory" if MMU
260 depends on !ARM_PATCH_PHYS_VIRT
261 default DRAM_BASE if !MMU
262 default 0x00000000 if ARCH_EBSA110 || \
268 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
269 default 0x20000000 if ARCH_S5PV210
270 default 0xc0000000 if ARCH_SA1100
272 Please provide the physical address corresponding to the
273 location of main memory in your system.
279 config PGTABLE_LEVELS
281 default 3 if ARM_LPAE
287 bool "MMU-based Paged Memory Management Support"
290 Select if you want MMU-based virtualised addressing space
291 support by paged memory management. If unsure, say 'Y'.
293 config ARCH_MMAP_RND_BITS_MIN
296 config ARCH_MMAP_RND_BITS_MAX
297 default 14 if PAGE_OFFSET=0x40000000
298 default 15 if PAGE_OFFSET=0x80000000
302 # The "ARM system type" choice list is ordered alphabetically by option
303 # text. Please add new entries in the option alphabetic order.
306 prompt "ARM system type"
307 default ARM_SINGLE_ARMV7M if !MMU
308 default ARCH_MULTIPLATFORM if MMU
310 config ARCH_MULTIPLATFORM
311 bool "Allow multiple platforms to be selected"
313 select ARM_HAS_SG_CHAIN
314 select ARM_PATCH_PHYS_VIRT
318 select GENERIC_CLOCKEVENTS
319 select GENERIC_IRQ_MULTI_HANDLER
321 select PCI_DOMAINS_GENERIC if PCI
325 config ARM_SINGLE_ARMV7M
326 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
333 select GENERIC_CLOCKEVENTS
340 select ARCH_USES_GETTIMEOFFSET
343 select NEED_MACH_IO_H
344 select NEED_MACH_MEMORY_H
347 This is an evaluation board for the StrongARM processor available
348 from Digital. It has limited hardware on-board, including an
349 Ethernet interface, two PCMCIA sockets, two serial ports and a
354 select ARCH_SPARSEMEM_ENABLE
356 imply ARM_PATCH_PHYS_VIRT
362 select GENERIC_CLOCKEVENTS
365 This enables support for the Cirrus EP93xx series of CPUs.
367 config ARCH_FOOTBRIDGE
371 select GENERIC_CLOCKEVENTS
373 select NEED_MACH_IO_H if !MMU
374 select NEED_MACH_MEMORY_H
376 Support for systems based on the DC21285 companion chip
377 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
380 bool "Hilscher NetX based"
384 select GENERIC_CLOCKEVENTS
386 This enables support for systems based on the Hilscher NetX Soc
392 select NEED_MACH_MEMORY_H
393 select NEED_RET_TO_USER
399 Support for Intel's IOP13XX (XScale) family of processors.
407 select NEED_RET_TO_USER
411 Support for Intel's 80219 and IOP32X (XScale) family of
420 select NEED_RET_TO_USER
424 Support for Intel's IOP33X (XScale) family of processors.
429 select ARCH_HAS_DMA_SET_COHERENT_MASK
430 select ARCH_SUPPORTS_BIG_ENDIAN
433 select DMABOUNCE if PCI
434 select GENERIC_CLOCKEVENTS
437 select NEED_MACH_IO_H
438 select USB_EHCI_BIG_ENDIAN_DESC
439 select USB_EHCI_BIG_ENDIAN_MMIO
441 Support for Intel's IXP4XX (XScale) family of processors.
446 select GENERIC_CLOCKEVENTS
447 select GENERIC_IRQ_MULTI_HANDLER
453 select PLAT_ORION_LEGACY
455 select PM_GENERIC_DOMAINS if PM
457 Support for the Marvell Dove SoC 88AP510
460 bool "Micrel/Kendin KS8695"
463 select GENERIC_CLOCKEVENTS
465 select NEED_MACH_MEMORY_H
467 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
468 System-on-Chip devices.
471 bool "Nuvoton W90X900 CPU"
475 select GENERIC_CLOCKEVENTS
478 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
479 At present, the w90x900 has been renamed nuc900, regarding
480 the ARM series product line, you can login the following
481 link address to know more.
483 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
484 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
490 select CLKSRC_LPC32XX
493 select GENERIC_CLOCKEVENTS
494 select GENERIC_IRQ_MULTI_HANDLER
499 Support for the NXP LPC32XX family of processors
502 bool "PXA2xx/PXA3xx-based"
505 select ARM_CPU_SUSPEND if PM
512 select CPU_XSCALE if !CPU_XSC3
513 select GENERIC_CLOCKEVENTS
514 select GENERIC_IRQ_MULTI_HANDLER
522 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
528 select ARCH_MAY_HAVE_PC_FDC
529 select ARCH_SPARSEMEM_ENABLE
530 select ARCH_USES_GETTIMEOFFSET
534 select HAVE_PATA_PLATFORM
536 select NEED_MACH_IO_H
537 select NEED_MACH_MEMORY_H
540 On the Acorn Risc-PC, Linux can support the internal IDE disk and
541 CD-ROM interface, serial and parallel port, and the floppy drive.
546 select ARCH_SPARSEMEM_ENABLE
550 select TIMER_OF if OF
553 select GENERIC_CLOCKEVENTS
554 select GENERIC_IRQ_MULTI_HANDLER
559 select NEED_MACH_MEMORY_H
562 Support for StrongARM 11x0 based boards.
565 bool "Samsung S3C24XX SoCs"
568 select CLKSRC_SAMSUNG_PWM
569 select GENERIC_CLOCKEVENTS
572 select GENERIC_IRQ_MULTI_HANDLER
573 select HAVE_S3C2410_I2C if I2C
574 select HAVE_S3C2410_WATCHDOG if WATCHDOG
575 select HAVE_S3C_RTC if RTC_CLASS
576 select NEED_MACH_IO_H
580 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
581 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
582 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
583 Samsung SMDK2410 development board (and derivatives).
587 select ARCH_HAS_HOLES_MEMORYMODEL
590 select GENERIC_ALLOCATOR
591 select GENERIC_CLOCKEVENTS
592 select GENERIC_IRQ_CHIP
593 select GENERIC_IRQ_MULTI_HANDLER
596 select PM_GENERIC_DOMAINS if PM
597 select PM_GENERIC_DOMAINS_OF if PM && OF
598 select RESET_CONTROLLER
603 Support for TI's DaVinci platform.
608 select ARCH_HAS_HOLES_MEMORYMODEL
612 select GENERIC_CLOCKEVENTS
613 select GENERIC_IRQ_CHIP
614 select GENERIC_IRQ_MULTI_HANDLER
618 select NEED_MACH_IO_H if PCCARD
619 select NEED_MACH_MEMORY_H
622 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
626 menu "Multiple platform selection"
627 depends on ARCH_MULTIPLATFORM
629 comment "CPU Core family selection"
632 bool "ARMv4 based platforms (FA526)"
633 depends on !ARCH_MULTI_V6_V7
634 select ARCH_MULTI_V4_V5
637 config ARCH_MULTI_V4T
638 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
639 depends on !ARCH_MULTI_V6_V7
640 select ARCH_MULTI_V4_V5
641 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
642 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
643 CPU_ARM925T || CPU_ARM940T)
646 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
647 depends on !ARCH_MULTI_V6_V7
648 select ARCH_MULTI_V4_V5
649 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
650 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
651 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
653 config ARCH_MULTI_V4_V5
657 bool "ARMv6 based platforms (ARM11)"
658 select ARCH_MULTI_V6_V7
662 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
664 select ARCH_MULTI_V6_V7
668 config ARCH_MULTI_V6_V7
670 select MIGHT_HAVE_CACHE_L2X0
672 config ARCH_MULTI_CPU_AUTO
673 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
679 bool "Dummy Virtual Machine"
680 depends on ARCH_MULTI_V7
683 select ARM_GIC_V2M if PCI
685 select ARM_GIC_V3_ITS if PCI
687 select HAVE_ARM_ARCH_TIMER
688 select ARCH_SUPPORTS_BIG_ENDIAN
691 # This is sorted alphabetically by mach-* pathname. However, plat-*
692 # Kconfigs may be included either alphabetically (according to the
693 # plat- suffix) or along side the corresponding mach-* source.
695 source "arch/arm/mach-actions/Kconfig"
697 source "arch/arm/mach-alpine/Kconfig"
699 source "arch/arm/mach-artpec/Kconfig"
701 source "arch/arm/mach-asm9260/Kconfig"
703 source "arch/arm/mach-aspeed/Kconfig"
705 source "arch/arm/mach-at91/Kconfig"
707 source "arch/arm/mach-axxia/Kconfig"
709 source "arch/arm/mach-bcm/Kconfig"
711 source "arch/arm/mach-berlin/Kconfig"
713 source "arch/arm/mach-clps711x/Kconfig"
715 source "arch/arm/mach-cns3xxx/Kconfig"
717 source "arch/arm/mach-davinci/Kconfig"
719 source "arch/arm/mach-digicolor/Kconfig"
721 source "arch/arm/mach-dove/Kconfig"
723 source "arch/arm/mach-ep93xx/Kconfig"
725 source "arch/arm/mach-exynos/Kconfig"
726 source "arch/arm/plat-samsung/Kconfig"
728 source "arch/arm/mach-footbridge/Kconfig"
730 source "arch/arm/mach-gemini/Kconfig"
732 source "arch/arm/mach-highbank/Kconfig"
734 source "arch/arm/mach-hisi/Kconfig"
736 source "arch/arm/mach-imx/Kconfig"
738 source "arch/arm/mach-integrator/Kconfig"
740 source "arch/arm/mach-iop13xx/Kconfig"
742 source "arch/arm/mach-iop32x/Kconfig"
744 source "arch/arm/mach-iop33x/Kconfig"
746 source "arch/arm/mach-ixp4xx/Kconfig"
748 source "arch/arm/mach-keystone/Kconfig"
750 source "arch/arm/mach-ks8695/Kconfig"
752 source "arch/arm/mach-mediatek/Kconfig"
754 source "arch/arm/mach-meson/Kconfig"
756 source "arch/arm/mach-milbeaut/Kconfig"
758 source "arch/arm/mach-mmp/Kconfig"
760 source "arch/arm/mach-moxart/Kconfig"
762 source "arch/arm/mach-mv78xx0/Kconfig"
764 source "arch/arm/mach-mvebu/Kconfig"
766 source "arch/arm/mach-mxs/Kconfig"
768 source "arch/arm/mach-netx/Kconfig"
770 source "arch/arm/mach-nomadik/Kconfig"
772 source "arch/arm/mach-npcm/Kconfig"
774 source "arch/arm/mach-nspire/Kconfig"
776 source "arch/arm/plat-omap/Kconfig"
778 source "arch/arm/mach-omap1/Kconfig"
780 source "arch/arm/mach-omap2/Kconfig"
782 source "arch/arm/mach-orion5x/Kconfig"
784 source "arch/arm/mach-oxnas/Kconfig"
786 source "arch/arm/mach-picoxcell/Kconfig"
788 source "arch/arm/mach-prima2/Kconfig"
790 source "arch/arm/mach-pxa/Kconfig"
791 source "arch/arm/plat-pxa/Kconfig"
793 source "arch/arm/mach-qcom/Kconfig"
795 source "arch/arm/mach-rda/Kconfig"
797 source "arch/arm/mach-realview/Kconfig"
799 source "arch/arm/mach-rockchip/Kconfig"
801 source "arch/arm/mach-s3c24xx/Kconfig"
803 source "arch/arm/mach-s3c64xx/Kconfig"
805 source "arch/arm/mach-s5pv210/Kconfig"
807 source "arch/arm/mach-sa1100/Kconfig"
809 source "arch/arm/mach-shmobile/Kconfig"
811 source "arch/arm/mach-socfpga/Kconfig"
813 source "arch/arm/mach-spear/Kconfig"
815 source "arch/arm/mach-sti/Kconfig"
817 source "arch/arm/mach-stm32/Kconfig"
819 source "arch/arm/mach-sunxi/Kconfig"
821 source "arch/arm/mach-tango/Kconfig"
823 source "arch/arm/mach-tegra/Kconfig"
825 source "arch/arm/mach-u300/Kconfig"
827 source "arch/arm/mach-uniphier/Kconfig"
829 source "arch/arm/mach-ux500/Kconfig"
831 source "arch/arm/mach-versatile/Kconfig"
833 source "arch/arm/mach-vexpress/Kconfig"
834 source "arch/arm/plat-versatile/Kconfig"
836 source "arch/arm/mach-vt8500/Kconfig"
838 source "arch/arm/mach-w90x900/Kconfig"
840 source "arch/arm/mach-zx/Kconfig"
842 source "arch/arm/mach-zynq/Kconfig"
844 # ARMv7-M architecture
846 bool "Energy Micro efm32"
847 depends on ARM_SINGLE_ARMV7M
850 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
854 bool "NXP LPC18xx/LPC43xx"
855 depends on ARM_SINGLE_ARMV7M
856 select ARCH_HAS_RESET_CONTROLLER
858 select CLKSRC_LPC32XX
861 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
862 high performance microcontrollers.
865 bool "ARM MPS2 platform"
866 depends on ARM_SINGLE_ARMV7M
870 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
871 with a range of available cores like Cortex-M3/M4/M7.
873 Please, note that depends which Application Note is used memory map
874 for the platform may vary, so adjustment of RAM base might be needed.
876 # Definitions to make life easier
882 select GENERIC_CLOCKEVENTS
888 select GENERIC_IRQ_CHIP
891 config PLAT_ORION_LEGACY
898 config PLAT_VERSATILE
901 source "arch/arm/firmware/Kconfig"
903 source "arch/arm/mm/Kconfig"
906 bool "Enable iWMMXt support"
907 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
908 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
910 Enable support for iWMMXt context switching at run time if
911 running on a CPU that supports it.
914 source "arch/arm/Kconfig-nommu"
917 config PJ4B_ERRATA_4742
918 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
919 depends on CPU_PJ4B && MACH_ARMADA_370
922 When coming out of either a Wait for Interrupt (WFI) or a Wait for
923 Event (WFE) IDLE states, a specific timing sensitivity exists between
924 the retiring WFI/WFE instructions and the newly issued subsequent
925 instructions. This sensitivity can result in a CPU hang scenario.
927 The software must insert either a Data Synchronization Barrier (DSB)
928 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
931 config ARM_ERRATA_326103
932 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
935 Executing a SWP instruction to read-only memory does not set bit 11
936 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
937 treat the access as a read, preventing a COW from occurring and
938 causing the faulting task to livelock.
940 config ARM_ERRATA_411920
941 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
942 depends on CPU_V6 || CPU_V6K
944 Invalidation of the Instruction Cache operation can
945 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
946 It does not affect the MPCore. This option enables the ARM Ltd.
947 recommended workaround.
949 config ARM_ERRATA_430973
950 bool "ARM errata: Stale prediction on replaced interworking branch"
953 This option enables the workaround for the 430973 Cortex-A8
954 r1p* erratum. If a code sequence containing an ARM/Thumb
955 interworking branch is replaced with another code sequence at the
956 same virtual address, whether due to self-modifying code or virtual
957 to physical address re-mapping, Cortex-A8 does not recover from the
958 stale interworking branch prediction. This results in Cortex-A8
959 executing the new code sequence in the incorrect ARM or Thumb state.
960 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
961 and also flushes the branch target cache at every context switch.
962 Note that setting specific bits in the ACTLR register may not be
963 available in non-secure mode.
965 config ARM_ERRATA_458693
966 bool "ARM errata: Processor deadlock when a false hazard is created"
968 depends on !ARCH_MULTIPLATFORM
970 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
971 erratum. For very specific sequences of memory operations, it is
972 possible for a hazard condition intended for a cache line to instead
973 be incorrectly associated with a different cache line. This false
974 hazard might then cause a processor deadlock. The workaround enables
975 the L1 caching of the NEON accesses and disables the PLD instruction
976 in the ACTLR register. Note that setting specific bits in the ACTLR
977 register may not be available in non-secure mode.
979 config ARM_ERRATA_460075
980 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
982 depends on !ARCH_MULTIPLATFORM
984 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
985 erratum. Any asynchronous access to the L2 cache may encounter a
986 situation in which recent store transactions to the L2 cache are lost
987 and overwritten with stale memory contents from external memory. The
988 workaround disables the write-allocate mode for the L2 cache via the
989 ACTLR register. Note that setting specific bits in the ACTLR register
990 may not be available in non-secure mode.
992 config ARM_ERRATA_742230
993 bool "ARM errata: DMB operation may be faulty"
994 depends on CPU_V7 && SMP
995 depends on !ARCH_MULTIPLATFORM
997 This option enables the workaround for the 742230 Cortex-A9
998 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
999 between two write operations may not ensure the correct visibility
1000 ordering of the two writes. This workaround sets a specific bit in
1001 the diagnostic register of the Cortex-A9 which causes the DMB
1002 instruction to behave as a DSB, ensuring the correct behaviour of
1005 config ARM_ERRATA_742231
1006 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1007 depends on CPU_V7 && SMP
1008 depends on !ARCH_MULTIPLATFORM
1010 This option enables the workaround for the 742231 Cortex-A9
1011 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1012 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1013 accessing some data located in the same cache line, may get corrupted
1014 data due to bad handling of the address hazard when the line gets
1015 replaced from one of the CPUs at the same time as another CPU is
1016 accessing it. This workaround sets specific bits in the diagnostic
1017 register of the Cortex-A9 which reduces the linefill issuing
1018 capabilities of the processor.
1020 config ARM_ERRATA_643719
1021 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1022 depends on CPU_V7 && SMP
1025 This option enables the workaround for the 643719 Cortex-A9 (prior to
1026 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1027 register returns zero when it should return one. The workaround
1028 corrects this value, ensuring cache maintenance operations which use
1029 it behave as intended and avoiding data corruption.
1031 config ARM_ERRATA_720789
1032 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1035 This option enables the workaround for the 720789 Cortex-A9 (prior to
1036 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1037 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1038 As a consequence of this erratum, some TLB entries which should be
1039 invalidated are not, resulting in an incoherency in the system page
1040 tables. The workaround changes the TLB flushing routines to invalidate
1041 entries regardless of the ASID.
1043 config ARM_ERRATA_743622
1044 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1046 depends on !ARCH_MULTIPLATFORM
1048 This option enables the workaround for the 743622 Cortex-A9
1049 (r2p*) erratum. Under very rare conditions, a faulty
1050 optimisation in the Cortex-A9 Store Buffer may lead to data
1051 corruption. This workaround sets a specific bit in the diagnostic
1052 register of the Cortex-A9 which disables the Store Buffer
1053 optimisation, preventing the defect from occurring. This has no
1054 visible impact on the overall performance or power consumption of the
1057 config ARM_ERRATA_751472
1058 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1060 depends on !ARCH_MULTIPLATFORM
1062 This option enables the workaround for the 751472 Cortex-A9 (prior
1063 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1064 completion of a following broadcasted operation if the second
1065 operation is received by a CPU before the ICIALLUIS has completed,
1066 potentially leading to corrupted entries in the cache or TLB.
1068 config ARM_ERRATA_754322
1069 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1072 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1073 r3p*) erratum. A speculative memory access may cause a page table walk
1074 which starts prior to an ASID switch but completes afterwards. This
1075 can populate the micro-TLB with a stale entry which may be hit with
1076 the new ASID. This workaround places two dsb instructions in the mm
1077 switching code so that no page table walks can cross the ASID switch.
1079 config ARM_ERRATA_754327
1080 bool "ARM errata: no automatic Store Buffer drain"
1081 depends on CPU_V7 && SMP
1083 This option enables the workaround for the 754327 Cortex-A9 (prior to
1084 r2p0) erratum. The Store Buffer does not have any automatic draining
1085 mechanism and therefore a livelock may occur if an external agent
1086 continuously polls a memory location waiting to observe an update.
1087 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1088 written polling loops from denying visibility of updates to memory.
1090 config ARM_ERRATA_364296
1091 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1094 This options enables the workaround for the 364296 ARM1136
1095 r0p2 erratum (possible cache data corruption with
1096 hit-under-miss enabled). It sets the undocumented bit 31 in
1097 the auxiliary control register and the FI bit in the control
1098 register, thus disabling hit-under-miss without putting the
1099 processor into full low interrupt latency mode. ARM11MPCore
1102 config ARM_ERRATA_764369
1103 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1104 depends on CPU_V7 && SMP
1106 This option enables the workaround for erratum 764369
1107 affecting Cortex-A9 MPCore with two or more processors (all
1108 current revisions). Under certain timing circumstances, a data
1109 cache line maintenance operation by MVA targeting an Inner
1110 Shareable memory region may fail to proceed up to either the
1111 Point of Coherency or to the Point of Unification of the
1112 system. This workaround adds a DSB instruction before the
1113 relevant cache maintenance functions and sets a specific bit
1114 in the diagnostic control register of the SCU.
1116 config ARM_ERRATA_775420
1117 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1120 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1121 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1122 operation aborts with MMU exception, it might cause the processor
1123 to deadlock. This workaround puts DSB before executing ISB if
1124 an abort may occur on cache maintenance.
1126 config ARM_ERRATA_798181
1127 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1128 depends on CPU_V7 && SMP
1130 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1131 adequately shooting down all use of the old entries. This
1132 option enables the Linux kernel workaround for this erratum
1133 which sends an IPI to the CPUs that are running the same ASID
1134 as the one being invalidated.
1136 config ARM_ERRATA_773022
1137 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1140 This option enables the workaround for the 773022 Cortex-A15
1141 (up to r0p4) erratum. In certain rare sequences of code, the
1142 loop buffer may deliver incorrect instructions. This
1143 workaround disables the loop buffer to avoid the erratum.
1145 config ARM_ERRATA_818325_852422
1146 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1149 This option enables the workaround for:
1150 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1151 instruction might deadlock. Fixed in r0p1.
1152 - Cortex-A12 852422: Execution of a sequence of instructions might
1153 lead to either a data corruption or a CPU deadlock. Not fixed in
1154 any Cortex-A12 cores yet.
1155 This workaround for all both errata involves setting bit[12] of the
1156 Feature Register. This bit disables an optimisation applied to a
1157 sequence of 2 instructions that use opposing condition codes.
1159 config ARM_ERRATA_821420
1160 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1163 This option enables the workaround for the 821420 Cortex-A12
1164 (all revs) erratum. In very rare timing conditions, a sequence
1165 of VMOV to Core registers instructions, for which the second
1166 one is in the shadow of a branch or abort, can lead to a
1167 deadlock when the VMOV instructions are issued out-of-order.
1169 config ARM_ERRATA_825619
1170 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1173 This option enables the workaround for the 825619 Cortex-A12
1174 (all revs) erratum. Within rare timing constraints, executing a
1175 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1176 and Device/Strongly-Ordered loads and stores might cause deadlock
1178 config ARM_ERRATA_852421
1179 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1182 This option enables the workaround for the 852421 Cortex-A17
1183 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1184 execution of a DMB ST instruction might fail to properly order
1185 stores from GroupA and stores from GroupB.
1187 config ARM_ERRATA_852423
1188 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1191 This option enables the workaround for:
1192 - Cortex-A17 852423: Execution of a sequence of instructions might
1193 lead to either a data corruption or a CPU deadlock. Not fixed in
1194 any Cortex-A17 cores yet.
1195 This is identical to Cortex-A12 erratum 852422. It is a separate
1196 config option from the A12 erratum due to the way errata are checked
1201 source "arch/arm/common/Kconfig"
1208 Find out whether you have ISA slots on your motherboard. ISA is the
1209 name of a bus system, i.e. the way the CPU talks to the other stuff
1210 inside your box. Other bus systems are PCI, EISA, MicroChannel
1211 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1212 newer boards don't support it. If you have ISA, say Y, otherwise N.
1214 # Select ISA DMA controller support
1219 # Select ISA DMA interface
1223 config PCI_NANOENGINE
1224 bool "BSE nanoEngine PCI support"
1225 depends on SA1100_NANOENGINE
1227 Enable PCI on the BSE nanoEngine board.
1229 config PCI_HOST_ITE8152
1231 depends on PCI && MACH_ARMCORE
1237 menu "Kernel Features"
1242 This option should be selected by machines which have an SMP-
1245 The only effect of this option is to make the SMP-related
1246 options available to the user for configuration.
1249 bool "Symmetric Multi-Processing"
1250 depends on CPU_V6K || CPU_V7
1251 depends on GENERIC_CLOCKEVENTS
1253 depends on MMU || ARM_MPU
1256 This enables support for systems with more than one CPU. If you have
1257 a system with only one CPU, say N. If you have a system with more
1258 than one CPU, say Y.
1260 If you say N here, the kernel will run on uni- and multiprocessor
1261 machines, but will use only one CPU of a multiprocessor machine. If
1262 you say Y here, the kernel will run on many, but not all,
1263 uniprocessor machines. On a uniprocessor machine, the kernel
1264 will run faster if you say N here.
1266 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1267 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at
1268 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1270 If you don't know what to do here, say N.
1273 bool "Allow booting SMP kernel on uniprocessor systems"
1274 depends on SMP && !XIP_KERNEL && MMU
1277 SMP kernels contain instructions which fail on non-SMP processors.
1278 Enabling this option allows the kernel to modify itself to make
1279 these instructions safe. Disabling it allows about 1K of space
1282 If you don't know what to do here, say Y.
1284 config ARM_CPU_TOPOLOGY
1285 bool "Support cpu topology definition"
1286 depends on SMP && CPU_V7
1289 Support ARM cpu topology definition. The MPIDR register defines
1290 affinity between processors which is then used to describe the cpu
1291 topology of an ARM System.
1294 bool "Multi-core scheduler support"
1295 depends on ARM_CPU_TOPOLOGY
1297 Multi-core scheduler support improves the CPU scheduler's decision
1298 making when dealing with multi-core CPU chips at a cost of slightly
1299 increased overhead in some places. If unsure say N here.
1302 bool "SMT scheduler support"
1303 depends on ARM_CPU_TOPOLOGY
1305 Improves the CPU scheduler's decision making when dealing with
1306 MultiThreading at a cost of slightly increased overhead in some
1307 places. If unsure say N here.
1312 This option enables support for the ARM system coherency unit
1314 config HAVE_ARM_ARCH_TIMER
1315 bool "Architected timer support"
1317 select ARM_ARCH_TIMER
1318 select GENERIC_CLOCKEVENTS
1320 This option enables support for the ARM architected timer
1324 select TIMER_OF if OF
1326 This options enables support for the ARM timer and watchdog unit
1329 bool "Multi-Cluster Power Management"
1330 depends on CPU_V7 && SMP
1332 This option provides the common power management infrastructure
1333 for (multi-)cluster based systems, such as big.LITTLE based
1336 config MCPM_QUAD_CLUSTER
1340 To avoid wasting resources unnecessarily, MCPM only supports up
1341 to 2 clusters by default.
1342 Platforms with 3 or 4 clusters that use MCPM must select this
1343 option to allow the additional clusters to be managed.
1346 bool "big.LITTLE support (Experimental)"
1347 depends on CPU_V7 && SMP
1350 This option enables support selections for the big.LITTLE
1351 system architecture.
1354 bool "big.LITTLE switcher support"
1355 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1358 The big.LITTLE "switcher" provides the core functionality to
1359 transparently handle transition between a cluster of A15's
1360 and a cluster of A7's in a big.LITTLE system.
1362 config BL_SWITCHER_DUMMY_IF
1363 tristate "Simple big.LITTLE switcher user interface"
1364 depends on BL_SWITCHER && DEBUG_KERNEL
1366 This is a simple and dummy char dev interface to control
1367 the big.LITTLE switcher core code. It is meant for
1368 debugging purposes only.
1371 prompt "Memory split"
1375 Select the desired split between kernel and user memory.
1377 If you are not absolutely sure what you are doing, leave this
1381 bool "3G/1G user/kernel split"
1382 config VMSPLIT_3G_OPT
1383 depends on !ARM_LPAE
1384 bool "3G/1G user/kernel split (for full 1G low memory)"
1386 bool "2G/2G user/kernel split"
1388 bool "1G/3G user/kernel split"
1393 default PHYS_OFFSET if !MMU
1394 default 0x40000000 if VMSPLIT_1G
1395 default 0x80000000 if VMSPLIT_2G
1396 default 0xB0000000 if VMSPLIT_3G_OPT
1400 int "Maximum number of CPUs (2-32)"
1406 bool "Support for hot-pluggable CPUs"
1408 select GENERIC_IRQ_MIGRATION
1410 Say Y here to experiment with turning CPUs off and on. CPUs
1411 can be controlled through /sys/devices/system/cpu.
1414 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1415 depends on HAVE_ARM_SMCCC
1418 Say Y here if you want Linux to communicate with system firmware
1419 implementing the PSCI specification for CPU-centric power
1420 management operations described in ARM document number ARM DEN
1421 0022A ("Power State Coordination Interface System Software on
1424 # The GPIO number here must be sorted by descending number. In case of
1425 # a multiplatform kernel, we just want the highest value required by the
1426 # selected platforms.
1429 default 2048 if ARCH_SOCFPGA
1430 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1432 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1433 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1434 default 416 if ARCH_SUNXI
1435 default 392 if ARCH_U8500
1436 default 352 if ARCH_VT8500
1437 default 288 if ARCH_ROCKCHIP
1438 default 264 if MACH_H4700
1441 Maximum number of GPIOs in the system.
1443 If unsure, leave the default value.
1447 default 200 if ARCH_EBSA110
1448 default 128 if SOC_AT91RM9200
1452 depends on HZ_FIXED = 0
1453 prompt "Timer frequency"
1477 default HZ_FIXED if HZ_FIXED != 0
1478 default 100 if HZ_100
1479 default 200 if HZ_200
1480 default 250 if HZ_250
1481 default 300 if HZ_300
1482 default 500 if HZ_500
1486 def_bool HIGH_RES_TIMERS
1488 config THUMB2_KERNEL
1489 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1490 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1491 default y if CPU_THUMBONLY
1494 By enabling this option, the kernel will be compiled in
1499 config THUMB2_AVOID_R_ARM_THM_JUMP11
1500 bool "Work around buggy Thumb-2 short branch relocations in gas"
1501 depends on THUMB2_KERNEL && MODULES
1504 Various binutils versions can resolve Thumb-2 branches to
1505 locally-defined, preemptible global symbols as short-range "b.n"
1506 branch instructions.
1508 This is a problem, because there's no guarantee the final
1509 destination of the symbol, or any candidate locations for a
1510 trampoline, are within range of the branch. For this reason, the
1511 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1512 relocation in modules at all, and it makes little sense to add
1515 The symptom is that the kernel fails with an "unsupported
1516 relocation" error when loading some modules.
1518 Until fixed tools are available, passing
1519 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1520 code which hits this problem, at the cost of a bit of extra runtime
1521 stack usage in some cases.
1523 The problem is described in more detail at:
1524 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1526 Only Thumb-2 kernels are affected.
1528 Unless you are sure your tools don't have this problem, say Y.
1530 config ARM_PATCH_IDIV
1531 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1532 depends on CPU_32v7 && !XIP_KERNEL
1535 The ARM compiler inserts calls to __aeabi_idiv() and
1536 __aeabi_uidiv() when it needs to perform division on signed
1537 and unsigned integers. Some v7 CPUs have support for the sdiv
1538 and udiv instructions that can be used to implement those
1541 Enabling this option allows the kernel to modify itself to
1542 replace the first two instructions of these library functions
1543 with the sdiv or udiv plus "bx lr" instructions when the CPU
1544 it is running on supports them. Typically this will be faster
1545 and less power intensive than running the original library
1546 code to do integer division.
1549 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1550 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1552 This option allows for the kernel to be compiled using the latest
1553 ARM ABI (aka EABI). This is only useful if you are using a user
1554 space environment that is also compiled with EABI.
1556 Since there are major incompatibilities between the legacy ABI and
1557 EABI, especially with regard to structure member alignment, this
1558 option also changes the kernel syscall calling convention to
1559 disambiguate both ABIs and allow for backward compatibility support
1560 (selected with CONFIG_OABI_COMPAT).
1562 To use this you need GCC version 4.0.0 or later.
1565 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1566 depends on AEABI && !THUMB2_KERNEL
1568 This option preserves the old syscall interface along with the
1569 new (ARM EABI) one. It also provides a compatibility layer to
1570 intercept syscalls that have structure arguments which layout
1571 in memory differs between the legacy ABI and the new ARM EABI
1572 (only for non "thumb" binaries). This option adds a tiny
1573 overhead to all syscalls and produces a slightly larger kernel.
1575 The seccomp filter system will not be available when this is
1576 selected, since there is no way yet to sensibly distinguish
1577 between calling conventions during filtering.
1579 If you know you'll be using only pure EABI user space then you
1580 can say N here. If this option is not selected and you attempt
1581 to execute a legacy ABI binary then the result will be
1582 UNPREDICTABLE (in fact it can be predicted that it won't work
1583 at all). If in doubt say N.
1585 config ARCH_HAS_HOLES_MEMORYMODEL
1588 config ARCH_SPARSEMEM_ENABLE
1591 config ARCH_SPARSEMEM_DEFAULT
1592 def_bool ARCH_SPARSEMEM_ENABLE
1594 config ARCH_SELECT_MEMORY_MODEL
1595 def_bool ARCH_SPARSEMEM_ENABLE
1597 config HAVE_ARCH_PFN_VALID
1598 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1600 config HAVE_GENERIC_GUP
1605 bool "High Memory Support"
1608 The address space of ARM processors is only 4 Gigabytes large
1609 and it has to accommodate user address space, kernel address
1610 space as well as some memory mapped IO. That means that, if you
1611 have a large amount of physical memory and/or IO, not all of the
1612 memory can be "permanently mapped" by the kernel. The physical
1613 memory that is not permanently mapped is called "high memory".
1615 Depending on the selected kernel/user memory split, minimum
1616 vmalloc space and actual amount of RAM, you may not need this
1617 option which should result in a slightly faster kernel.
1622 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1626 The VM uses one page of physical memory for each page table.
1627 For systems with a lot of processes, this can use a lot of
1628 precious low memory, eventually leading to low memory being
1629 consumed by page tables. Setting this option will allow
1630 user-space 2nd level page tables to reside in high memory.
1632 config CPU_SW_DOMAIN_PAN
1633 bool "Enable use of CPU domains to implement privileged no-access"
1634 depends on MMU && !ARM_LPAE
1637 Increase kernel security by ensuring that normal kernel accesses
1638 are unable to access userspace addresses. This can help prevent
1639 use-after-free bugs becoming an exploitable privilege escalation
1640 by ensuring that magic values (such as LIST_POISON) will always
1641 fault when dereferenced.
1643 CPUs with low-vector mappings use a best-efforts implementation.
1644 Their lower 1MB needs to remain accessible for the vectors, but
1645 the remainder of userspace will become appropriately inaccessible.
1647 config HW_PERF_EVENTS
1651 config SYS_SUPPORTS_HUGETLBFS
1655 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1659 config ARCH_WANT_GENERAL_HUGETLB
1662 config ARM_MODULE_PLTS
1663 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1667 Allocate PLTs when loading modules so that jumps and calls whose
1668 targets are too far away for their relative offsets to be encoded
1669 in the instructions themselves can be bounced via veneers in the
1670 module's PLT. This allows modules to be allocated in the generic
1671 vmalloc area after the dedicated module memory area has been
1672 exhausted. The modules will use slightly more memory, but after
1673 rounding up to page size, the actual memory footprint is usually
1676 Disabling this is usually safe for small single-platform
1677 configurations. If unsure, say y.
1679 config FORCE_MAX_ZONEORDER
1680 int "Maximum zone order"
1681 default "12" if SOC_AM33XX
1682 default "9" if SA1111 || ARCH_EFM32
1685 The kernel memory allocator divides physically contiguous memory
1686 blocks into "zones", where each zone is a power of two number of
1687 pages. This option selects the largest power of two that the kernel
1688 keeps in the memory allocator. If you need to allocate very large
1689 blocks of physically contiguous memory, then you may need to
1690 increase this value.
1692 This config option is actually maximum order plus one. For example,
1693 a value of 11 means that the largest free memory block is 2^10 pages.
1695 config ALIGNMENT_TRAP
1697 depends on CPU_CP15_MMU
1698 default y if !ARCH_EBSA110
1699 select HAVE_PROC_CPU if PROC_FS
1701 ARM processors cannot fetch/store information which is not
1702 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1703 address divisible by 4. On 32-bit ARM processors, these non-aligned
1704 fetch/store instructions will be emulated in software if you say
1705 here, which has a severe performance impact. This is necessary for
1706 correct operation of some network protocols. With an IP-only
1707 configuration it is safe to say N, otherwise say Y.
1709 config UACCESS_WITH_MEMCPY
1710 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1712 default y if CPU_FEROCEON
1714 Implement faster copy_to_user and clear_user methods for CPU
1715 cores where a 8-word STM instruction give significantly higher
1716 memory write throughput than a sequence of individual 32bit stores.
1718 A possible side effect is a slight increase in scheduling latency
1719 between threads sharing the same address space if they invoke
1720 such copy operations with large buffers.
1722 However, if the CPU data cache is using a write-allocate mode,
1723 this option is unlikely to provide any performance gain.
1727 prompt "Enable seccomp to safely compute untrusted bytecode"
1729 This kernel feature is useful for number crunching applications
1730 that may need to compute untrusted bytecode during their
1731 execution. By using pipes or other transports made available to
1732 the process as file descriptors supporting the read/write
1733 syscalls, it's possible to isolate those applications in
1734 their own address space using seccomp. Once seccomp is
1735 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1736 and the task is only allowed to execute a few safe syscalls
1737 defined by each seccomp mode.
1740 bool "Enable paravirtualization code"
1742 This changes the kernel so it can modify itself when it is run
1743 under a hypervisor, potentially improving performance significantly
1744 over full virtualization.
1746 config PARAVIRT_TIME_ACCOUNTING
1747 bool "Paravirtual steal time accounting"
1750 Select this option to enable fine granularity task steal time
1751 accounting. Time spent executing other tasks in parallel with
1752 the current vCPU is discounted from the vCPU power. To account for
1753 that, there can be a small performance impact.
1755 If in doubt, say N here.
1762 bool "Xen guest support on ARM"
1763 depends on ARM && AEABI && OF
1764 depends on CPU_V7 && !CPU_V6
1765 depends on !GENERIC_ATOMIC64
1767 select ARCH_DMA_ADDR_T_64BIT
1773 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1775 config STACKPROTECTOR_PER_TASK
1776 bool "Use a unique stack canary value for each task"
1777 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1778 select GCC_PLUGIN_ARM_SSP_PER_TASK
1781 Due to the fact that GCC uses an ordinary symbol reference from
1782 which to load the value of the stack canary, this value can only
1783 change at reboot time on SMP systems, and all tasks running in the
1784 kernel's address space are forced to use the same canary value for
1785 the entire duration that the system is up.
1787 Enable this option to switch to a different method that uses a
1788 different canary value for each task.
1795 bool "Flattened Device Tree support"
1799 Include support for flattened device tree machine descriptions.
1802 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1805 This is the traditional way of passing data to the kernel at boot
1806 time. If you are solely relying on the flattened device tree (or
1807 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1808 to remove ATAGS support from your kernel binary. If unsure,
1811 config DEPRECATED_PARAM_STRUCT
1812 bool "Provide old way to pass kernel parameters"
1815 This was deprecated in 2001 and announced to live on for 5 years.
1816 Some old boot loaders still use this way.
1818 # Compressed boot loader in ROM. Yes, we really want to ask about
1819 # TEXT and BSS so we preserve their values in the config files.
1820 config ZBOOT_ROM_TEXT
1821 hex "Compressed ROM boot loader base address"
1824 The physical address at which the ROM-able zImage is to be
1825 placed in the target. Platforms which normally make use of
1826 ROM-able zImage formats normally set this to a suitable
1827 value in their defconfig file.
1829 If ZBOOT_ROM is not enabled, this has no effect.
1831 config ZBOOT_ROM_BSS
1832 hex "Compressed ROM boot loader BSS address"
1835 The base address of an area of read/write memory in the target
1836 for the ROM-able zImage which must be available while the
1837 decompressor is running. It must be large enough to hold the
1838 entire decompressed kernel plus an additional 128 KiB.
1839 Platforms which normally make use of ROM-able zImage formats
1840 normally set this to a suitable value in their defconfig file.
1842 If ZBOOT_ROM is not enabled, this has no effect.
1845 bool "Compressed boot loader in ROM/flash"
1846 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1847 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1849 Say Y here if you intend to execute your compressed kernel image
1850 (zImage) directly from ROM or flash. If unsure, say N.
1852 config ARM_APPENDED_DTB
1853 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1856 With this option, the boot code will look for a device tree binary
1857 (DTB) appended to zImage
1858 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1860 This is meant as a backward compatibility convenience for those
1861 systems with a bootloader that can't be upgraded to accommodate
1862 the documented boot protocol using a device tree.
1864 Beware that there is very little in terms of protection against
1865 this option being confused by leftover garbage in memory that might
1866 look like a DTB header after a reboot if no actual DTB is appended
1867 to zImage. Do not leave this option active in a production kernel
1868 if you don't intend to always append a DTB. Proper passing of the
1869 location into r2 of a bootloader provided DTB is always preferable
1872 config ARM_ATAG_DTB_COMPAT
1873 bool "Supplement the appended DTB with traditional ATAG information"
1874 depends on ARM_APPENDED_DTB
1876 Some old bootloaders can't be updated to a DTB capable one, yet
1877 they provide ATAGs with memory configuration, the ramdisk address,
1878 the kernel cmdline string, etc. Such information is dynamically
1879 provided by the bootloader and can't always be stored in a static
1880 DTB. To allow a device tree enabled kernel to be used with such
1881 bootloaders, this option allows zImage to extract the information
1882 from the ATAG list and store it at run time into the appended DTB.
1885 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1886 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1888 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1889 bool "Use bootloader kernel arguments if available"
1891 Uses the command-line options passed by the boot loader instead of
1892 the device tree bootargs property. If the boot loader doesn't provide
1893 any, the device tree bootargs property will be used.
1895 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1896 bool "Extend with bootloader kernel arguments"
1898 The command-line arguments provided by the boot loader will be
1899 appended to the the device tree bootargs property.
1904 string "Default kernel command string"
1907 On some architectures (EBSA110 and CATS), there is currently no way
1908 for the boot loader to pass arguments to the kernel. For these
1909 architectures, you should supply some command-line options at build
1910 time by entering them here. As a minimum, you should specify the
1911 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1914 prompt "Kernel command line type" if CMDLINE != ""
1915 default CMDLINE_FROM_BOOTLOADER
1918 config CMDLINE_FROM_BOOTLOADER
1919 bool "Use bootloader kernel arguments if available"
1921 Uses the command-line options passed by the boot loader. If
1922 the boot loader doesn't provide any, the default kernel command
1923 string provided in CMDLINE will be used.
1925 config CMDLINE_EXTEND
1926 bool "Extend bootloader kernel arguments"
1928 The command-line arguments provided by the boot loader will be
1929 appended to the default kernel command string.
1931 config CMDLINE_FORCE
1932 bool "Always use the default kernel command string"
1934 Always use the default kernel command string, even if the boot
1935 loader passes other arguments to the kernel.
1936 This is useful if you cannot or don't want to change the
1937 command-line options your boot loader passes to the kernel.
1941 bool "Kernel Execute-In-Place from ROM"
1942 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1944 Execute-In-Place allows the kernel to run from non-volatile storage
1945 directly addressable by the CPU, such as NOR flash. This saves RAM
1946 space since the text section of the kernel is not loaded from flash
1947 to RAM. Read-write sections, such as the data section and stack,
1948 are still copied to RAM. The XIP kernel is not compressed since
1949 it has to run directly from flash, so it will take more space to
1950 store it. The flash address used to link the kernel object files,
1951 and for storing it, is configuration dependent. Therefore, if you
1952 say Y here, you must know the proper physical address where to
1953 store the kernel image depending on your own flash memory usage.
1955 Also note that the make target becomes "make xipImage" rather than
1956 "make zImage" or "make Image". The final kernel binary to put in
1957 ROM memory will be arch/arm/boot/xipImage.
1961 config XIP_PHYS_ADDR
1962 hex "XIP Kernel Physical Location"
1963 depends on XIP_KERNEL
1964 default "0x00080000"
1966 This is the physical address in your flash memory the kernel will
1967 be linked for and stored to. This address is dependent on your
1970 config XIP_DEFLATED_DATA
1971 bool "Store kernel .data section compressed in ROM"
1972 depends on XIP_KERNEL
1975 Before the kernel is actually executed, its .data section has to be
1976 copied to RAM from ROM. This option allows for storing that data
1977 in compressed form and decompressed to RAM rather than merely being
1978 copied, saving some precious ROM space. A possible drawback is a
1979 slightly longer boot delay.
1982 bool "Kexec system call (EXPERIMENTAL)"
1983 depends on (!SMP || PM_SLEEP_SMP)
1987 kexec is a system call that implements the ability to shutdown your
1988 current kernel, and to start another kernel. It is like a reboot
1989 but it is independent of the system firmware. And like a reboot
1990 you can start any kernel with it, not just Linux.
1992 It is an ongoing process to be certain the hardware in a machine
1993 is properly shutdown, so do not be surprised if this code does not
1994 initially work for you.
1997 bool "Export atags in procfs"
1998 depends on ATAGS && KEXEC
2001 Should the atags used to boot the kernel be exported in an "atags"
2002 file in procfs. Useful with kexec.
2005 bool "Build kdump crash kernel (EXPERIMENTAL)"
2007 Generate crash dump after being started by kexec. This should
2008 be normally only set in special crash dump kernels which are
2009 loaded in the main kernel with kexec-tools into a specially
2010 reserved region and then later executed after a crash by
2011 kdump/kexec. The crash dump kernel must be compiled to a
2012 memory address not used by the main kernel
2014 For more details see Documentation/kdump/kdump.txt
2016 config AUTO_ZRELADDR
2017 bool "Auto calculation of the decompressed kernel image address"
2019 ZRELADDR is the physical address where the decompressed kernel
2020 image will be placed. If AUTO_ZRELADDR is selected, the address
2021 will be determined at run-time by masking the current IP with
2022 0xf8000000. This assumes the zImage being placed in the first 128MB
2023 from start of memory.
2029 bool "UEFI runtime support"
2030 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2032 select EFI_PARAMS_FROM_FDT
2035 select EFI_RUNTIME_WRAPPERS
2037 This option provides support for runtime services provided
2038 by UEFI firmware (such as non-volatile variables, realtime
2039 clock, and platform reset). A UEFI stub is also provided to
2040 allow the kernel to be booted as an EFI application. This
2041 is only useful for kernels that may run on systems that have
2045 bool "Enable support for SMBIOS (DMI) tables"
2049 This enables SMBIOS/DMI feature for systems.
2051 This option is only useful on systems that have UEFI firmware.
2052 However, even with this option, the resultant kernel should
2053 continue to boot on existing non-UEFI platforms.
2055 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2056 i.e., the the practice of identifying the platform via DMI to
2057 decide whether certain workarounds for buggy hardware and/or
2058 firmware need to be enabled. This would require the DMI subsystem
2059 to be enabled much earlier than we do on ARM, which is non-trivial.
2063 menu "CPU Power Management"
2065 source "drivers/cpufreq/Kconfig"
2067 source "drivers/cpuidle/Kconfig"
2071 menu "Floating point emulation"
2073 comment "At least one emulation must be selected"
2076 bool "NWFPE math emulation"
2077 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2079 Say Y to include the NWFPE floating point emulator in the kernel.
2080 This is necessary to run most binaries. Linux does not currently
2081 support floating point hardware so you need to say Y here even if
2082 your machine has an FPA or floating point co-processor podule.
2084 You may say N here if you are going to load the Acorn FPEmulator
2085 early in the bootup.
2088 bool "Support extended precision"
2089 depends on FPE_NWFPE
2091 Say Y to include 80-bit support in the kernel floating-point
2092 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2093 Note that gcc does not generate 80-bit operations by default,
2094 so in most cases this option only enlarges the size of the
2095 floating point emulator without any good reason.
2097 You almost surely want to say N here.
2100 bool "FastFPE math emulation (EXPERIMENTAL)"
2101 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2103 Say Y here to include the FAST floating point emulator in the kernel.
2104 This is an experimental much faster emulator which now also has full
2105 precision for the mantissa. It does not support any exceptions.
2106 It is very simple, and approximately 3-6 times faster than NWFPE.
2108 It should be sufficient for most programs. It may be not suitable
2109 for scientific calculations, but you have to check this for yourself.
2110 If you do not feel you need a faster FP emulation you should better
2114 bool "VFP-format floating point maths"
2115 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2117 Say Y to include VFP support code in the kernel. This is needed
2118 if your hardware includes a VFP unit.
2120 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2121 release notes and additional status information.
2123 Say N if your target does not have VFP hardware.
2131 bool "Advanced SIMD (NEON) Extension support"
2132 depends on VFPv3 && CPU_V7
2134 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2137 config KERNEL_MODE_NEON
2138 bool "Support for NEON in kernel mode"
2139 depends on NEON && AEABI
2141 Say Y to include support for NEON in kernel mode.
2145 menu "Power management options"
2147 source "kernel/power/Kconfig"
2149 config ARCH_SUSPEND_POSSIBLE
2150 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2151 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2154 config ARM_CPU_SUSPEND
2155 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2156 depends on ARCH_SUSPEND_POSSIBLE
2158 config ARCH_HIBERNATION_POSSIBLE
2161 default y if ARCH_SUSPEND_POSSIBLE
2165 source "drivers/firmware/Kconfig"
2168 source "arch/arm/crypto/Kconfig"
2171 source "arch/arm/kvm/Kconfig"