1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_CLOCKSOURCE_DATA
6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DEVMEM_IS_ALLOWED
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_FORTIFY_SOURCE
12 select ARCH_HAS_MEMBARRIER_SYNC_CORE
13 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
14 select ARCH_HAS_PHYS_TO_DMA
15 select ARCH_HAS_SET_MEMORY
16 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
17 select ARCH_HAS_STRICT_MODULE_RWX if MMU
18 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
19 select ARCH_HAVE_CUSTOM_GPIO_H
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_MIGHT_HAVE_PC_PARPORT
22 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
23 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
24 select ARCH_SUPPORTS_ATOMIC_RMW
25 select ARCH_USE_BUILTIN_BSWAP
26 select ARCH_USE_CMPXCHG_LOCKREF
27 select ARCH_WANT_IPC_PARSE_VERSION
28 select BUILDTIME_EXTABLE_SORT if MMU
29 select CLONE_BACKWARDS
30 select CPU_PM if (SUSPEND || CPU_IDLE)
31 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
32 select DMA_DIRECT_OPS if !MMU
34 select EDAC_ATOMIC_SCRUB
35 select GENERIC_ALLOCATOR
36 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
37 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
38 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
39 select GENERIC_CPU_AUTOPROBE
40 select GENERIC_EARLY_IOREMAP
41 select GENERIC_IDLE_POLL_SETUP
42 select GENERIC_IRQ_PROBE
43 select GENERIC_IRQ_SHOW
44 select GENERIC_IRQ_SHOW_LEVEL
45 select GENERIC_PCI_IOMAP
46 select GENERIC_SCHED_CLOCK
47 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_STRNCPY_FROM_USER
49 select GENERIC_STRNLEN_USER
50 select HANDLE_DOMAIN_IRQ
51 select HARDIRQS_SW_RESEND
52 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
53 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
54 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
55 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
56 select HAVE_ARCH_MMAP_RND_BITS if MMU
57 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
58 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
59 select HAVE_ARCH_TRACEHOOK
60 select HAVE_ARM_SMCCC if CPU_V7
61 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
62 select HAVE_CONTEXT_TRACKING
63 select HAVE_C_RECORDMCOUNT
64 select HAVE_DEBUG_KMEMLEAK
65 select HAVE_DMA_CONTIGUOUS if MMU
66 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
67 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
68 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
69 select HAVE_EXIT_THREAD
70 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
71 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
72 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
73 select HAVE_GCC_PLUGINS
74 select HAVE_GENERIC_DMA_COHERENT
75 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
76 select HAVE_IDE if PCI || ISA || PCMCIA
77 select HAVE_IRQ_TIME_ACCOUNTING
78 select HAVE_KERNEL_GZIP
79 select HAVE_KERNEL_LZ4
80 select HAVE_KERNEL_LZMA
81 select HAVE_KERNEL_LZO
83 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
84 select HAVE_KRETPROBES if (HAVE_KPROBES)
85 select HAVE_MOD_ARCH_SPECIFIC
87 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
88 select HAVE_OPTPROBES if !THUMB2_KERNEL
89 select HAVE_PERF_EVENTS
91 select HAVE_PERF_USER_STACK_DUMP
92 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
93 select HAVE_REGS_AND_STACK_ACCESS_API
95 select HAVE_STACKPROTECTOR
96 select HAVE_SYSCALL_TRACEPOINTS
98 select HAVE_VIRT_CPU_ACCOUNTING_GEN
99 select IRQ_FORCED_THREADING
100 select MODULES_USE_ELF_REL
101 select NEED_DMA_MAP_STATE
102 select OF_EARLY_FLATTREE if OF
103 select OF_RESERVED_MEM if OF
105 select OLD_SIGSUSPEND3
106 select PERF_USE_VMALLOC
109 select SYS_SUPPORTS_APM_EMULATION
110 # Above selects are sorted alphabetically; please add new ones
111 # according to that. Thanks.
113 The ARM series is a line of low-power-consumption RISC chip designs
114 licensed by ARM Ltd and targeted at embedded applications and
115 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
116 manufactured, but legacy ARM-based PC hardware remains popular in
117 Europe. There is an ARM Linux project with a web page at
118 <http://www.arm.linux.org.uk/>.
120 config ARM_HAS_SG_CHAIN
121 select ARCH_HAS_SG_CHAIN
124 config ARM_DMA_USE_IOMMU
126 select ARM_HAS_SG_CHAIN
127 select NEED_SG_DMA_LENGTH
131 config ARM_DMA_IOMMU_ALIGNMENT
132 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
136 DMA mapping framework by default aligns all buffers to the smallest
137 PAGE_SIZE order which is greater than or equal to the requested buffer
138 size. This works well for buffers up to a few hundreds kilobytes, but
139 for larger buffers it just a waste of address space. Drivers which has
140 relatively small addressing window (like 64Mib) might run out of
141 virtual space with just a few allocations.
143 With this parameter you can specify the maximum PAGE_SIZE order for
144 DMA IOMMU buffers. Larger buffers will be aligned only to this
145 specified order. The order is expressed as a power of two multiplied
150 config SYS_SUPPORTS_APM_EMULATION
155 select GENERIC_ALLOCATOR
166 The Extended Industry Standard Architecture (EISA) bus was
167 developed as an open alternative to the IBM MicroChannel bus.
169 The EISA bus provided some of the features of the IBM MicroChannel
170 bus while maintaining backward compatibility with cards made for
171 the older ISA bus. The EISA bus saw limited use between 1988 and
172 1995 when it was made obsolete by the PCI bus.
174 Say Y here if you are building a kernel for an EISA-based machine.
181 config STACKTRACE_SUPPORT
185 config LOCKDEP_SUPPORT
189 config TRACE_IRQFLAGS_SUPPORT
193 config RWSEM_XCHGADD_ALGORITHM
197 config ARCH_HAS_ILOG2_U32
200 config ARCH_HAS_ILOG2_U64
203 config ARCH_HAS_BANDGAP
206 config FIX_EARLYCON_MEM
209 config GENERIC_HWEIGHT
213 config GENERIC_CALIBRATE_DELAY
217 config ARCH_MAY_HAVE_PC_FDC
223 config ARCH_SUPPORTS_UPROBES
226 config ARCH_HAS_DMA_SET_COHERENT_MASK
229 config GENERIC_ISA_DMA
235 config NEED_RET_TO_USER
241 config ARM_PATCH_PHYS_VIRT
242 bool "Patch physical to virtual translations at runtime" if EMBEDDED
244 depends on !XIP_KERNEL && MMU
246 Patch phys-to-virt and virt-to-phys translation functions at
247 boot and module load time according to the position of the
248 kernel in system memory.
250 This can only be used with non-XIP MMU kernels where the base
251 of physical memory is at a 16MB boundary.
253 Only disable this option if you know that you do not require
254 this feature (eg, building a kernel for a single machine) and
255 you need to shrink the kernel to the minimal size.
257 config NEED_MACH_IO_H
260 Select this when mach/io.h is required to provide special
261 definitions for this platform. The need for mach/io.h should
262 be avoided when possible.
264 config NEED_MACH_MEMORY_H
267 Select this when mach/memory.h is required to provide special
268 definitions for this platform. The need for mach/memory.h should
269 be avoided when possible.
272 hex "Physical address of main memory" if MMU
273 depends on !ARM_PATCH_PHYS_VIRT
274 default DRAM_BASE if !MMU
275 default 0x00000000 if ARCH_EBSA110 || \
281 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
282 default 0x20000000 if ARCH_S5PV210
283 default 0xc0000000 if ARCH_SA1100
285 Please provide the physical address corresponding to the
286 location of main memory in your system.
292 config PGTABLE_LEVELS
294 default 3 if ARM_LPAE
300 bool "MMU-based Paged Memory Management Support"
303 Select if you want MMU-based virtualised addressing space
304 support by paged memory management. If unsure, say 'Y'.
306 config ARCH_MMAP_RND_BITS_MIN
309 config ARCH_MMAP_RND_BITS_MAX
310 default 14 if PAGE_OFFSET=0x40000000
311 default 15 if PAGE_OFFSET=0x80000000
315 # The "ARM system type" choice list is ordered alphabetically by option
316 # text. Please add new entries in the option alphabetic order.
319 prompt "ARM system type"
320 default ARM_SINGLE_ARMV7M if !MMU
321 default ARCH_MULTIPLATFORM if MMU
323 config ARCH_MULTIPLATFORM
324 bool "Allow multiple platforms to be selected"
326 select ARM_HAS_SG_CHAIN
327 select ARM_PATCH_PHYS_VIRT
331 select GENERIC_CLOCKEVENTS
332 select GENERIC_IRQ_MULTI_HANDLER
334 select PCI_DOMAINS if PCI
338 config ARM_SINGLE_ARMV7M
339 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
346 select GENERIC_CLOCKEVENTS
353 select ARCH_USES_GETTIMEOFFSET
356 select NEED_MACH_IO_H
357 select NEED_MACH_MEMORY_H
360 This is an evaluation board for the StrongARM processor available
361 from Digital. It has limited hardware on-board, including an
362 Ethernet interface, two PCMCIA sockets, two serial ports and a
367 select ARCH_SPARSEMEM_ENABLE
369 imply ARM_PATCH_PHYS_VIRT
375 select GENERIC_CLOCKEVENTS
378 This enables support for the Cirrus EP93xx series of CPUs.
380 config ARCH_FOOTBRIDGE
384 select GENERIC_CLOCKEVENTS
386 select NEED_MACH_IO_H if !MMU
387 select NEED_MACH_MEMORY_H
389 Support for systems based on the DC21285 companion chip
390 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
393 bool "Hilscher NetX based"
397 select GENERIC_CLOCKEVENTS
399 This enables support for systems based on the Hilscher NetX Soc
405 select NEED_MACH_MEMORY_H
406 select NEED_RET_TO_USER
412 Support for Intel's IOP13XX (XScale) family of processors.
420 select NEED_RET_TO_USER
424 Support for Intel's 80219 and IOP32X (XScale) family of
433 select NEED_RET_TO_USER
437 Support for Intel's IOP33X (XScale) family of processors.
442 select ARCH_HAS_DMA_SET_COHERENT_MASK
443 select ARCH_SUPPORTS_BIG_ENDIAN
446 select DMABOUNCE if PCI
447 select GENERIC_CLOCKEVENTS
450 select NEED_MACH_IO_H
451 select USB_EHCI_BIG_ENDIAN_DESC
452 select USB_EHCI_BIG_ENDIAN_MMIO
454 Support for Intel's IXP4XX (XScale) family of processors.
459 select GENERIC_CLOCKEVENTS
460 select GENERIC_IRQ_MULTI_HANDLER
466 select PLAT_ORION_LEGACY
468 select PM_GENERIC_DOMAINS if PM
470 Support for the Marvell Dove SoC 88AP510
473 bool "Micrel/Kendin KS8695"
476 select GENERIC_CLOCKEVENTS
478 select NEED_MACH_MEMORY_H
480 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
481 System-on-Chip devices.
484 bool "Nuvoton W90X900 CPU"
488 select GENERIC_CLOCKEVENTS
491 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
492 At present, the w90x900 has been renamed nuc900, regarding
493 the ARM series product line, you can login the following
494 link address to know more.
496 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
497 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
503 select CLKSRC_LPC32XX
506 select GENERIC_CLOCKEVENTS
507 select GENERIC_IRQ_MULTI_HANDLER
512 Support for the NXP LPC32XX family of processors
515 bool "PXA2xx/PXA3xx-based"
518 select ARM_CPU_SUSPEND if PM
525 select CPU_XSCALE if !CPU_XSC3
526 select GENERIC_CLOCKEVENTS
527 select GENERIC_IRQ_MULTI_HANDLER
535 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
541 select ARCH_MAY_HAVE_PC_FDC
542 select ARCH_SPARSEMEM_ENABLE
543 select ARCH_USES_GETTIMEOFFSET
547 select HAVE_PATA_PLATFORM
549 select NEED_MACH_IO_H
550 select NEED_MACH_MEMORY_H
553 On the Acorn Risc-PC, Linux can support the internal IDE disk and
554 CD-ROM interface, serial and parallel port, and the floppy drive.
559 select ARCH_SPARSEMEM_ENABLE
563 select TIMER_OF if OF
566 select GENERIC_CLOCKEVENTS
567 select GENERIC_IRQ_MULTI_HANDLER
572 select NEED_MACH_MEMORY_H
575 Support for StrongARM 11x0 based boards.
578 bool "Samsung S3C24XX SoCs"
581 select CLKSRC_SAMSUNG_PWM
582 select GENERIC_CLOCKEVENTS
585 select GENERIC_IRQ_MULTI_HANDLER
586 select HAVE_S3C2410_I2C if I2C
587 select HAVE_S3C2410_WATCHDOG if WATCHDOG
588 select HAVE_S3C_RTC if RTC_CLASS
589 select NEED_MACH_IO_H
593 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
594 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
595 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
596 Samsung SMDK2410 development board (and derivatives).
600 select ARCH_HAS_HOLES_MEMORYMODEL
603 select GENERIC_ALLOCATOR
604 select GENERIC_CLOCKEVENTS
605 select GENERIC_IRQ_CHIP
608 select PM_GENERIC_DOMAINS if PM
609 select PM_GENERIC_DOMAINS_OF if PM && OF
610 select RESET_CONTROLLER
614 Support for TI's DaVinci platform.
619 select ARCH_HAS_HOLES_MEMORYMODEL
623 select GENERIC_CLOCKEVENTS
624 select GENERIC_IRQ_CHIP
625 select GENERIC_IRQ_MULTI_HANDLER
629 select NEED_MACH_IO_H if PCCARD
630 select NEED_MACH_MEMORY_H
633 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
637 menu "Multiple platform selection"
638 depends on ARCH_MULTIPLATFORM
640 comment "CPU Core family selection"
643 bool "ARMv4 based platforms (FA526)"
644 depends on !ARCH_MULTI_V6_V7
645 select ARCH_MULTI_V4_V5
648 config ARCH_MULTI_V4T
649 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
650 depends on !ARCH_MULTI_V6_V7
651 select ARCH_MULTI_V4_V5
652 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
653 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
654 CPU_ARM925T || CPU_ARM940T)
657 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
658 depends on !ARCH_MULTI_V6_V7
659 select ARCH_MULTI_V4_V5
660 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
661 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
662 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
664 config ARCH_MULTI_V4_V5
668 bool "ARMv6 based platforms (ARM11)"
669 select ARCH_MULTI_V6_V7
673 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
675 select ARCH_MULTI_V6_V7
679 config ARCH_MULTI_V6_V7
681 select MIGHT_HAVE_CACHE_L2X0
683 config ARCH_MULTI_CPU_AUTO
684 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
690 bool "Dummy Virtual Machine"
691 depends on ARCH_MULTI_V7
694 select ARM_GIC_V2M if PCI
696 select ARM_GIC_V3_ITS if PCI
698 select HAVE_ARM_ARCH_TIMER
699 select ARCH_SUPPORTS_BIG_ENDIAN
702 # This is sorted alphabetically by mach-* pathname. However, plat-*
703 # Kconfigs may be included either alphabetically (according to the
704 # plat- suffix) or along side the corresponding mach-* source.
706 source "arch/arm/mach-actions/Kconfig"
708 source "arch/arm/mach-alpine/Kconfig"
710 source "arch/arm/mach-artpec/Kconfig"
712 source "arch/arm/mach-asm9260/Kconfig"
714 source "arch/arm/mach-aspeed/Kconfig"
716 source "arch/arm/mach-at91/Kconfig"
718 source "arch/arm/mach-axxia/Kconfig"
720 source "arch/arm/mach-bcm/Kconfig"
722 source "arch/arm/mach-berlin/Kconfig"
724 source "arch/arm/mach-clps711x/Kconfig"
726 source "arch/arm/mach-cns3xxx/Kconfig"
728 source "arch/arm/mach-davinci/Kconfig"
730 source "arch/arm/mach-digicolor/Kconfig"
732 source "arch/arm/mach-dove/Kconfig"
734 source "arch/arm/mach-ep93xx/Kconfig"
736 source "arch/arm/mach-exynos/Kconfig"
737 source "arch/arm/plat-samsung/Kconfig"
739 source "arch/arm/mach-footbridge/Kconfig"
741 source "arch/arm/mach-gemini/Kconfig"
743 source "arch/arm/mach-highbank/Kconfig"
745 source "arch/arm/mach-hisi/Kconfig"
747 source "arch/arm/mach-imx/Kconfig"
749 source "arch/arm/mach-integrator/Kconfig"
751 source "arch/arm/mach-iop13xx/Kconfig"
753 source "arch/arm/mach-iop32x/Kconfig"
755 source "arch/arm/mach-iop33x/Kconfig"
757 source "arch/arm/mach-ixp4xx/Kconfig"
759 source "arch/arm/mach-keystone/Kconfig"
761 source "arch/arm/mach-ks8695/Kconfig"
763 source "arch/arm/mach-mediatek/Kconfig"
765 source "arch/arm/mach-meson/Kconfig"
767 source "arch/arm/mach-mmp/Kconfig"
769 source "arch/arm/mach-moxart/Kconfig"
771 source "arch/arm/mach-mv78xx0/Kconfig"
773 source "arch/arm/mach-mvebu/Kconfig"
775 source "arch/arm/mach-mxs/Kconfig"
777 source "arch/arm/mach-netx/Kconfig"
779 source "arch/arm/mach-nomadik/Kconfig"
781 source "arch/arm/mach-npcm/Kconfig"
783 source "arch/arm/mach-nspire/Kconfig"
785 source "arch/arm/plat-omap/Kconfig"
787 source "arch/arm/mach-omap1/Kconfig"
789 source "arch/arm/mach-omap2/Kconfig"
791 source "arch/arm/mach-orion5x/Kconfig"
793 source "arch/arm/mach-oxnas/Kconfig"
795 source "arch/arm/mach-picoxcell/Kconfig"
797 source "arch/arm/mach-prima2/Kconfig"
799 source "arch/arm/mach-pxa/Kconfig"
800 source "arch/arm/plat-pxa/Kconfig"
802 source "arch/arm/mach-qcom/Kconfig"
804 source "arch/arm/mach-realview/Kconfig"
806 source "arch/arm/mach-rockchip/Kconfig"
808 source "arch/arm/mach-s3c24xx/Kconfig"
810 source "arch/arm/mach-s3c64xx/Kconfig"
812 source "arch/arm/mach-s5pv210/Kconfig"
814 source "arch/arm/mach-sa1100/Kconfig"
816 source "arch/arm/mach-shmobile/Kconfig"
818 source "arch/arm/mach-socfpga/Kconfig"
820 source "arch/arm/mach-spear/Kconfig"
822 source "arch/arm/mach-sti/Kconfig"
824 source "arch/arm/mach-stm32/Kconfig"
826 source "arch/arm/mach-sunxi/Kconfig"
828 source "arch/arm/mach-tango/Kconfig"
830 source "arch/arm/mach-tegra/Kconfig"
832 source "arch/arm/mach-u300/Kconfig"
834 source "arch/arm/mach-uniphier/Kconfig"
836 source "arch/arm/mach-ux500/Kconfig"
838 source "arch/arm/mach-versatile/Kconfig"
840 source "arch/arm/mach-vexpress/Kconfig"
841 source "arch/arm/plat-versatile/Kconfig"
843 source "arch/arm/mach-vt8500/Kconfig"
845 source "arch/arm/mach-w90x900/Kconfig"
847 source "arch/arm/mach-zx/Kconfig"
849 source "arch/arm/mach-zynq/Kconfig"
851 # ARMv7-M architecture
853 bool "Energy Micro efm32"
854 depends on ARM_SINGLE_ARMV7M
857 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
861 bool "NXP LPC18xx/LPC43xx"
862 depends on ARM_SINGLE_ARMV7M
863 select ARCH_HAS_RESET_CONTROLLER
865 select CLKSRC_LPC32XX
868 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
869 high performance microcontrollers.
872 bool "ARM MPS2 platform"
873 depends on ARM_SINGLE_ARMV7M
877 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
878 with a range of available cores like Cortex-M3/M4/M7.
880 Please, note that depends which Application Note is used memory map
881 for the platform may vary, so adjustment of RAM base might be needed.
883 # Definitions to make life easier
889 select GENERIC_CLOCKEVENTS
895 select GENERIC_IRQ_CHIP
898 config PLAT_ORION_LEGACY
905 config PLAT_VERSATILE
908 source "arch/arm/firmware/Kconfig"
910 source arch/arm/mm/Kconfig
913 bool "Enable iWMMXt support"
914 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
915 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
917 Enable support for iWMMXt context switching at run time if
918 running on a CPU that supports it.
921 source "arch/arm/Kconfig-nommu"
924 config PJ4B_ERRATA_4742
925 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
926 depends on CPU_PJ4B && MACH_ARMADA_370
929 When coming out of either a Wait for Interrupt (WFI) or a Wait for
930 Event (WFE) IDLE states, a specific timing sensitivity exists between
931 the retiring WFI/WFE instructions and the newly issued subsequent
932 instructions. This sensitivity can result in a CPU hang scenario.
934 The software must insert either a Data Synchronization Barrier (DSB)
935 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
938 config ARM_ERRATA_326103
939 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
942 Executing a SWP instruction to read-only memory does not set bit 11
943 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
944 treat the access as a read, preventing a COW from occurring and
945 causing the faulting task to livelock.
947 config ARM_ERRATA_411920
948 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
949 depends on CPU_V6 || CPU_V6K
951 Invalidation of the Instruction Cache operation can
952 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
953 It does not affect the MPCore. This option enables the ARM Ltd.
954 recommended workaround.
956 config ARM_ERRATA_430973
957 bool "ARM errata: Stale prediction on replaced interworking branch"
960 This option enables the workaround for the 430973 Cortex-A8
961 r1p* erratum. If a code sequence containing an ARM/Thumb
962 interworking branch is replaced with another code sequence at the
963 same virtual address, whether due to self-modifying code or virtual
964 to physical address re-mapping, Cortex-A8 does not recover from the
965 stale interworking branch prediction. This results in Cortex-A8
966 executing the new code sequence in the incorrect ARM or Thumb state.
967 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
968 and also flushes the branch target cache at every context switch.
969 Note that setting specific bits in the ACTLR register may not be
970 available in non-secure mode.
972 config ARM_ERRATA_458693
973 bool "ARM errata: Processor deadlock when a false hazard is created"
975 depends on !ARCH_MULTIPLATFORM
977 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
978 erratum. For very specific sequences of memory operations, it is
979 possible for a hazard condition intended for a cache line to instead
980 be incorrectly associated with a different cache line. This false
981 hazard might then cause a processor deadlock. The workaround enables
982 the L1 caching of the NEON accesses and disables the PLD instruction
983 in the ACTLR register. Note that setting specific bits in the ACTLR
984 register may not be available in non-secure mode.
986 config ARM_ERRATA_460075
987 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
989 depends on !ARCH_MULTIPLATFORM
991 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
992 erratum. Any asynchronous access to the L2 cache may encounter a
993 situation in which recent store transactions to the L2 cache are lost
994 and overwritten with stale memory contents from external memory. The
995 workaround disables the write-allocate mode for the L2 cache via the
996 ACTLR register. Note that setting specific bits in the ACTLR register
997 may not be available in non-secure mode.
999 config ARM_ERRATA_742230
1000 bool "ARM errata: DMB operation may be faulty"
1001 depends on CPU_V7 && SMP
1002 depends on !ARCH_MULTIPLATFORM
1004 This option enables the workaround for the 742230 Cortex-A9
1005 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1006 between two write operations may not ensure the correct visibility
1007 ordering of the two writes. This workaround sets a specific bit in
1008 the diagnostic register of the Cortex-A9 which causes the DMB
1009 instruction to behave as a DSB, ensuring the correct behaviour of
1012 config ARM_ERRATA_742231
1013 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1014 depends on CPU_V7 && SMP
1015 depends on !ARCH_MULTIPLATFORM
1017 This option enables the workaround for the 742231 Cortex-A9
1018 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1019 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1020 accessing some data located in the same cache line, may get corrupted
1021 data due to bad handling of the address hazard when the line gets
1022 replaced from one of the CPUs at the same time as another CPU is
1023 accessing it. This workaround sets specific bits in the diagnostic
1024 register of the Cortex-A9 which reduces the linefill issuing
1025 capabilities of the processor.
1027 config ARM_ERRATA_643719
1028 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1029 depends on CPU_V7 && SMP
1032 This option enables the workaround for the 643719 Cortex-A9 (prior to
1033 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1034 register returns zero when it should return one. The workaround
1035 corrects this value, ensuring cache maintenance operations which use
1036 it behave as intended and avoiding data corruption.
1038 config ARM_ERRATA_720789
1039 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1042 This option enables the workaround for the 720789 Cortex-A9 (prior to
1043 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1044 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1045 As a consequence of this erratum, some TLB entries which should be
1046 invalidated are not, resulting in an incoherency in the system page
1047 tables. The workaround changes the TLB flushing routines to invalidate
1048 entries regardless of the ASID.
1050 config ARM_ERRATA_743622
1051 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1053 depends on !ARCH_MULTIPLATFORM
1055 This option enables the workaround for the 743622 Cortex-A9
1056 (r2p*) erratum. Under very rare conditions, a faulty
1057 optimisation in the Cortex-A9 Store Buffer may lead to data
1058 corruption. This workaround sets a specific bit in the diagnostic
1059 register of the Cortex-A9 which disables the Store Buffer
1060 optimisation, preventing the defect from occurring. This has no
1061 visible impact on the overall performance or power consumption of the
1064 config ARM_ERRATA_751472
1065 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1067 depends on !ARCH_MULTIPLATFORM
1069 This option enables the workaround for the 751472 Cortex-A9 (prior
1070 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1071 completion of a following broadcasted operation if the second
1072 operation is received by a CPU before the ICIALLUIS has completed,
1073 potentially leading to corrupted entries in the cache or TLB.
1075 config ARM_ERRATA_754322
1076 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1079 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1080 r3p*) erratum. A speculative memory access may cause a page table walk
1081 which starts prior to an ASID switch but completes afterwards. This
1082 can populate the micro-TLB with a stale entry which may be hit with
1083 the new ASID. This workaround places two dsb instructions in the mm
1084 switching code so that no page table walks can cross the ASID switch.
1086 config ARM_ERRATA_754327
1087 bool "ARM errata: no automatic Store Buffer drain"
1088 depends on CPU_V7 && SMP
1090 This option enables the workaround for the 754327 Cortex-A9 (prior to
1091 r2p0) erratum. The Store Buffer does not have any automatic draining
1092 mechanism and therefore a livelock may occur if an external agent
1093 continuously polls a memory location waiting to observe an update.
1094 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1095 written polling loops from denying visibility of updates to memory.
1097 config ARM_ERRATA_364296
1098 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1101 This options enables the workaround for the 364296 ARM1136
1102 r0p2 erratum (possible cache data corruption with
1103 hit-under-miss enabled). It sets the undocumented bit 31 in
1104 the auxiliary control register and the FI bit in the control
1105 register, thus disabling hit-under-miss without putting the
1106 processor into full low interrupt latency mode. ARM11MPCore
1109 config ARM_ERRATA_764369
1110 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1111 depends on CPU_V7 && SMP
1113 This option enables the workaround for erratum 764369
1114 affecting Cortex-A9 MPCore with two or more processors (all
1115 current revisions). Under certain timing circumstances, a data
1116 cache line maintenance operation by MVA targeting an Inner
1117 Shareable memory region may fail to proceed up to either the
1118 Point of Coherency or to the Point of Unification of the
1119 system. This workaround adds a DSB instruction before the
1120 relevant cache maintenance functions and sets a specific bit
1121 in the diagnostic control register of the SCU.
1123 config ARM_ERRATA_775420
1124 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1127 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1128 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1129 operation aborts with MMU exception, it might cause the processor
1130 to deadlock. This workaround puts DSB before executing ISB if
1131 an abort may occur on cache maintenance.
1133 config ARM_ERRATA_798181
1134 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1135 depends on CPU_V7 && SMP
1137 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1138 adequately shooting down all use of the old entries. This
1139 option enables the Linux kernel workaround for this erratum
1140 which sends an IPI to the CPUs that are running the same ASID
1141 as the one being invalidated.
1143 config ARM_ERRATA_773022
1144 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1147 This option enables the workaround for the 773022 Cortex-A15
1148 (up to r0p4) erratum. In certain rare sequences of code, the
1149 loop buffer may deliver incorrect instructions. This
1150 workaround disables the loop buffer to avoid the erratum.
1152 config ARM_ERRATA_818325_852422
1153 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1156 This option enables the workaround for:
1157 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1158 instruction might deadlock. Fixed in r0p1.
1159 - Cortex-A12 852422: Execution of a sequence of instructions might
1160 lead to either a data corruption or a CPU deadlock. Not fixed in
1161 any Cortex-A12 cores yet.
1162 This workaround for all both errata involves setting bit[12] of the
1163 Feature Register. This bit disables an optimisation applied to a
1164 sequence of 2 instructions that use opposing condition codes.
1166 config ARM_ERRATA_821420
1167 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1170 This option enables the workaround for the 821420 Cortex-A12
1171 (all revs) erratum. In very rare timing conditions, a sequence
1172 of VMOV to Core registers instructions, for which the second
1173 one is in the shadow of a branch or abort, can lead to a
1174 deadlock when the VMOV instructions are issued out-of-order.
1176 config ARM_ERRATA_825619
1177 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1180 This option enables the workaround for the 825619 Cortex-A12
1181 (all revs) erratum. Within rare timing constraints, executing a
1182 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1183 and Device/Strongly-Ordered loads and stores might cause deadlock
1185 config ARM_ERRATA_852421
1186 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1189 This option enables the workaround for the 852421 Cortex-A17
1190 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1191 execution of a DMB ST instruction might fail to properly order
1192 stores from GroupA and stores from GroupB.
1194 config ARM_ERRATA_852423
1195 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1198 This option enables the workaround for:
1199 - Cortex-A17 852423: Execution of a sequence of instructions might
1200 lead to either a data corruption or a CPU deadlock. Not fixed in
1201 any Cortex-A17 cores yet.
1202 This is identical to Cortex-A12 erratum 852422. It is a separate
1203 config option from the A12 erratum due to the way errata are checked
1208 source "arch/arm/common/Kconfig"
1215 Find out whether you have ISA slots on your motherboard. ISA is the
1216 name of a bus system, i.e. the way the CPU talks to the other stuff
1217 inside your box. Other bus systems are PCI, EISA, MicroChannel
1218 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1219 newer boards don't support it. If you have ISA, say Y, otherwise N.
1221 # Select ISA DMA controller support
1226 # Select ISA DMA interface
1231 bool "Support for multiple PCI domains"
1234 Enable PCI domains kernel management. Say Y if your machine
1235 has a PCI bus hierarchy that requires more than one PCI
1236 domain (aka segment) to be correctly managed. Say N otherwise.
1238 If you don't know what to do here, say N.
1240 config PCI_DOMAINS_GENERIC
1241 def_bool PCI_DOMAINS
1243 config PCI_NANOENGINE
1244 bool "BSE nanoEngine PCI support"
1245 depends on SA1100_NANOENGINE
1247 Enable PCI on the BSE nanoEngine board.
1252 config PCI_HOST_ITE8152
1254 depends on PCI && MACH_ARMCORE
1258 source "drivers/pcmcia/Kconfig"
1262 menu "Kernel Features"
1267 This option should be selected by machines which have an SMP-
1270 The only effect of this option is to make the SMP-related
1271 options available to the user for configuration.
1274 bool "Symmetric Multi-Processing"
1275 depends on CPU_V6K || CPU_V7
1276 depends on GENERIC_CLOCKEVENTS
1278 depends on MMU || ARM_MPU
1281 This enables support for systems with more than one CPU. If you have
1282 a system with only one CPU, say N. If you have a system with more
1283 than one CPU, say Y.
1285 If you say N here, the kernel will run on uni- and multiprocessor
1286 machines, but will use only one CPU of a multiprocessor machine. If
1287 you say Y here, the kernel will run on many, but not all,
1288 uniprocessor machines. On a uniprocessor machine, the kernel
1289 will run faster if you say N here.
1291 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1292 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at
1293 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1295 If you don't know what to do here, say N.
1298 bool "Allow booting SMP kernel on uniprocessor systems"
1299 depends on SMP && !XIP_KERNEL && MMU
1302 SMP kernels contain instructions which fail on non-SMP processors.
1303 Enabling this option allows the kernel to modify itself to make
1304 these instructions safe. Disabling it allows about 1K of space
1307 If you don't know what to do here, say Y.
1309 config ARM_CPU_TOPOLOGY
1310 bool "Support cpu topology definition"
1311 depends on SMP && CPU_V7
1314 Support ARM cpu topology definition. The MPIDR register defines
1315 affinity between processors which is then used to describe the cpu
1316 topology of an ARM System.
1319 bool "Multi-core scheduler support"
1320 depends on ARM_CPU_TOPOLOGY
1322 Multi-core scheduler support improves the CPU scheduler's decision
1323 making when dealing with multi-core CPU chips at a cost of slightly
1324 increased overhead in some places. If unsure say N here.
1327 bool "SMT scheduler support"
1328 depends on ARM_CPU_TOPOLOGY
1330 Improves the CPU scheduler's decision making when dealing with
1331 MultiThreading at a cost of slightly increased overhead in some
1332 places. If unsure say N here.
1337 This option enables support for the ARM system coherency unit
1339 config HAVE_ARM_ARCH_TIMER
1340 bool "Architected timer support"
1342 select ARM_ARCH_TIMER
1343 select GENERIC_CLOCKEVENTS
1345 This option enables support for the ARM architected timer
1349 select TIMER_OF if OF
1351 This options enables support for the ARM timer and watchdog unit
1354 bool "Multi-Cluster Power Management"
1355 depends on CPU_V7 && SMP
1357 This option provides the common power management infrastructure
1358 for (multi-)cluster based systems, such as big.LITTLE based
1361 config MCPM_QUAD_CLUSTER
1365 To avoid wasting resources unnecessarily, MCPM only supports up
1366 to 2 clusters by default.
1367 Platforms with 3 or 4 clusters that use MCPM must select this
1368 option to allow the additional clusters to be managed.
1371 bool "big.LITTLE support (Experimental)"
1372 depends on CPU_V7 && SMP
1375 This option enables support selections for the big.LITTLE
1376 system architecture.
1379 bool "big.LITTLE switcher support"
1380 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1383 The big.LITTLE "switcher" provides the core functionality to
1384 transparently handle transition between a cluster of A15's
1385 and a cluster of A7's in a big.LITTLE system.
1387 config BL_SWITCHER_DUMMY_IF
1388 tristate "Simple big.LITTLE switcher user interface"
1389 depends on BL_SWITCHER && DEBUG_KERNEL
1391 This is a simple and dummy char dev interface to control
1392 the big.LITTLE switcher core code. It is meant for
1393 debugging purposes only.
1396 prompt "Memory split"
1400 Select the desired split between kernel and user memory.
1402 If you are not absolutely sure what you are doing, leave this
1406 bool "3G/1G user/kernel split"
1407 config VMSPLIT_3G_OPT
1408 depends on !ARM_LPAE
1409 bool "3G/1G user/kernel split (for full 1G low memory)"
1411 bool "2G/2G user/kernel split"
1413 bool "1G/3G user/kernel split"
1418 default PHYS_OFFSET if !MMU
1419 default 0x40000000 if VMSPLIT_1G
1420 default 0x80000000 if VMSPLIT_2G
1421 default 0xB0000000 if VMSPLIT_3G_OPT
1425 int "Maximum number of CPUs (2-32)"
1431 bool "Support for hot-pluggable CPUs"
1434 Say Y here to experiment with turning CPUs off and on. CPUs
1435 can be controlled through /sys/devices/system/cpu.
1438 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1439 depends on HAVE_ARM_SMCCC
1442 Say Y here if you want Linux to communicate with system firmware
1443 implementing the PSCI specification for CPU-centric power
1444 management operations described in ARM document number ARM DEN
1445 0022A ("Power State Coordination Interface System Software on
1448 # The GPIO number here must be sorted by descending number. In case of
1449 # a multiplatform kernel, we just want the highest value required by the
1450 # selected platforms.
1453 default 2048 if ARCH_SOCFPGA
1454 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1456 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1457 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1458 default 416 if ARCH_SUNXI
1459 default 392 if ARCH_U8500
1460 default 352 if ARCH_VT8500
1461 default 288 if ARCH_ROCKCHIP
1462 default 264 if MACH_H4700
1465 Maximum number of GPIOs in the system.
1467 If unsure, leave the default value.
1471 default 200 if ARCH_EBSA110
1472 default 128 if SOC_AT91RM9200
1476 depends on HZ_FIXED = 0
1477 prompt "Timer frequency"
1501 default HZ_FIXED if HZ_FIXED != 0
1502 default 100 if HZ_100
1503 default 200 if HZ_200
1504 default 250 if HZ_250
1505 default 300 if HZ_300
1506 default 500 if HZ_500
1510 def_bool HIGH_RES_TIMERS
1512 config THUMB2_KERNEL
1513 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1514 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1515 default y if CPU_THUMBONLY
1518 By enabling this option, the kernel will be compiled in
1523 config THUMB2_AVOID_R_ARM_THM_JUMP11
1524 bool "Work around buggy Thumb-2 short branch relocations in gas"
1525 depends on THUMB2_KERNEL && MODULES
1528 Various binutils versions can resolve Thumb-2 branches to
1529 locally-defined, preemptible global symbols as short-range "b.n"
1530 branch instructions.
1532 This is a problem, because there's no guarantee the final
1533 destination of the symbol, or any candidate locations for a
1534 trampoline, are within range of the branch. For this reason, the
1535 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1536 relocation in modules at all, and it makes little sense to add
1539 The symptom is that the kernel fails with an "unsupported
1540 relocation" error when loading some modules.
1542 Until fixed tools are available, passing
1543 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1544 code which hits this problem, at the cost of a bit of extra runtime
1545 stack usage in some cases.
1547 The problem is described in more detail at:
1548 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1550 Only Thumb-2 kernels are affected.
1552 Unless you are sure your tools don't have this problem, say Y.
1554 config ARM_PATCH_IDIV
1555 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1556 depends on CPU_32v7 && !XIP_KERNEL
1559 The ARM compiler inserts calls to __aeabi_idiv() and
1560 __aeabi_uidiv() when it needs to perform division on signed
1561 and unsigned integers. Some v7 CPUs have support for the sdiv
1562 and udiv instructions that can be used to implement those
1565 Enabling this option allows the kernel to modify itself to
1566 replace the first two instructions of these library functions
1567 with the sdiv or udiv plus "bx lr" instructions when the CPU
1568 it is running on supports them. Typically this will be faster
1569 and less power intensive than running the original library
1570 code to do integer division.
1573 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1574 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1576 This option allows for the kernel to be compiled using the latest
1577 ARM ABI (aka EABI). This is only useful if you are using a user
1578 space environment that is also compiled with EABI.
1580 Since there are major incompatibilities between the legacy ABI and
1581 EABI, especially with regard to structure member alignment, this
1582 option also changes the kernel syscall calling convention to
1583 disambiguate both ABIs and allow for backward compatibility support
1584 (selected with CONFIG_OABI_COMPAT).
1586 To use this you need GCC version 4.0.0 or later.
1589 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1590 depends on AEABI && !THUMB2_KERNEL
1592 This option preserves the old syscall interface along with the
1593 new (ARM EABI) one. It also provides a compatibility layer to
1594 intercept syscalls that have structure arguments which layout
1595 in memory differs between the legacy ABI and the new ARM EABI
1596 (only for non "thumb" binaries). This option adds a tiny
1597 overhead to all syscalls and produces a slightly larger kernel.
1599 The seccomp filter system will not be available when this is
1600 selected, since there is no way yet to sensibly distinguish
1601 between calling conventions during filtering.
1603 If you know you'll be using only pure EABI user space then you
1604 can say N here. If this option is not selected and you attempt
1605 to execute a legacy ABI binary then the result will be
1606 UNPREDICTABLE (in fact it can be predicted that it won't work
1607 at all). If in doubt say N.
1609 config ARCH_HAS_HOLES_MEMORYMODEL
1612 config ARCH_SPARSEMEM_ENABLE
1615 config ARCH_SPARSEMEM_DEFAULT
1616 def_bool ARCH_SPARSEMEM_ENABLE
1618 config ARCH_SELECT_MEMORY_MODEL
1619 def_bool ARCH_SPARSEMEM_ENABLE
1621 config HAVE_ARCH_PFN_VALID
1622 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1624 config HAVE_GENERIC_GUP
1629 bool "High Memory Support"
1632 The address space of ARM processors is only 4 Gigabytes large
1633 and it has to accommodate user address space, kernel address
1634 space as well as some memory mapped IO. That means that, if you
1635 have a large amount of physical memory and/or IO, not all of the
1636 memory can be "permanently mapped" by the kernel. The physical
1637 memory that is not permanently mapped is called "high memory".
1639 Depending on the selected kernel/user memory split, minimum
1640 vmalloc space and actual amount of RAM, you may not need this
1641 option which should result in a slightly faster kernel.
1646 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1650 The VM uses one page of physical memory for each page table.
1651 For systems with a lot of processes, this can use a lot of
1652 precious low memory, eventually leading to low memory being
1653 consumed by page tables. Setting this option will allow
1654 user-space 2nd level page tables to reside in high memory.
1656 config CPU_SW_DOMAIN_PAN
1657 bool "Enable use of CPU domains to implement privileged no-access"
1658 depends on MMU && !ARM_LPAE
1661 Increase kernel security by ensuring that normal kernel accesses
1662 are unable to access userspace addresses. This can help prevent
1663 use-after-free bugs becoming an exploitable privilege escalation
1664 by ensuring that magic values (such as LIST_POISON) will always
1665 fault when dereferenced.
1667 CPUs with low-vector mappings use a best-efforts implementation.
1668 Their lower 1MB needs to remain accessible for the vectors, but
1669 the remainder of userspace will become appropriately inaccessible.
1671 config HW_PERF_EVENTS
1675 config SYS_SUPPORTS_HUGETLBFS
1679 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1683 config ARCH_WANT_GENERAL_HUGETLB
1686 config ARM_MODULE_PLTS
1687 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1691 Allocate PLTs when loading modules so that jumps and calls whose
1692 targets are too far away for their relative offsets to be encoded
1693 in the instructions themselves can be bounced via veneers in the
1694 module's PLT. This allows modules to be allocated in the generic
1695 vmalloc area after the dedicated module memory area has been
1696 exhausted. The modules will use slightly more memory, but after
1697 rounding up to page size, the actual memory footprint is usually
1700 Disabling this is usually safe for small single-platform
1701 configurations. If unsure, say y.
1703 config FORCE_MAX_ZONEORDER
1704 int "Maximum zone order"
1705 default "12" if SOC_AM33XX
1706 default "9" if SA1111 || ARCH_EFM32
1709 The kernel memory allocator divides physically contiguous memory
1710 blocks into "zones", where each zone is a power of two number of
1711 pages. This option selects the largest power of two that the kernel
1712 keeps in the memory allocator. If you need to allocate very large
1713 blocks of physically contiguous memory, then you may need to
1714 increase this value.
1716 This config option is actually maximum order plus one. For example,
1717 a value of 11 means that the largest free memory block is 2^10 pages.
1719 config ALIGNMENT_TRAP
1721 depends on CPU_CP15_MMU
1722 default y if !ARCH_EBSA110
1723 select HAVE_PROC_CPU if PROC_FS
1725 ARM processors cannot fetch/store information which is not
1726 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1727 address divisible by 4. On 32-bit ARM processors, these non-aligned
1728 fetch/store instructions will be emulated in software if you say
1729 here, which has a severe performance impact. This is necessary for
1730 correct operation of some network protocols. With an IP-only
1731 configuration it is safe to say N, otherwise say Y.
1733 config UACCESS_WITH_MEMCPY
1734 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1736 default y if CPU_FEROCEON
1738 Implement faster copy_to_user and clear_user methods for CPU
1739 cores where a 8-word STM instruction give significantly higher
1740 memory write throughput than a sequence of individual 32bit stores.
1742 A possible side effect is a slight increase in scheduling latency
1743 between threads sharing the same address space if they invoke
1744 such copy operations with large buffers.
1746 However, if the CPU data cache is using a write-allocate mode,
1747 this option is unlikely to provide any performance gain.
1751 prompt "Enable seccomp to safely compute untrusted bytecode"
1753 This kernel feature is useful for number crunching applications
1754 that may need to compute untrusted bytecode during their
1755 execution. By using pipes or other transports made available to
1756 the process as file descriptors supporting the read/write
1757 syscalls, it's possible to isolate those applications in
1758 their own address space using seccomp. Once seccomp is
1759 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1760 and the task is only allowed to execute a few safe syscalls
1761 defined by each seccomp mode.
1764 bool "Enable paravirtualization code"
1766 This changes the kernel so it can modify itself when it is run
1767 under a hypervisor, potentially improving performance significantly
1768 over full virtualization.
1770 config PARAVIRT_TIME_ACCOUNTING
1771 bool "Paravirtual steal time accounting"
1775 Select this option to enable fine granularity task steal time
1776 accounting. Time spent executing other tasks in parallel with
1777 the current vCPU is discounted from the vCPU power. To account for
1778 that, there can be a small performance impact.
1780 If in doubt, say N here.
1787 bool "Xen guest support on ARM"
1788 depends on ARM && AEABI && OF
1789 depends on CPU_V7 && !CPU_V6
1790 depends on !GENERIC_ATOMIC64
1792 select ARCH_DMA_ADDR_T_64BIT
1798 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1805 bool "Flattened Device Tree support"
1809 Include support for flattened device tree machine descriptions.
1812 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1815 This is the traditional way of passing data to the kernel at boot
1816 time. If you are solely relying on the flattened device tree (or
1817 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1818 to remove ATAGS support from your kernel binary. If unsure,
1821 config DEPRECATED_PARAM_STRUCT
1822 bool "Provide old way to pass kernel parameters"
1825 This was deprecated in 2001 and announced to live on for 5 years.
1826 Some old boot loaders still use this way.
1828 # Compressed boot loader in ROM. Yes, we really want to ask about
1829 # TEXT and BSS so we preserve their values in the config files.
1830 config ZBOOT_ROM_TEXT
1831 hex "Compressed ROM boot loader base address"
1834 The physical address at which the ROM-able zImage is to be
1835 placed in the target. Platforms which normally make use of
1836 ROM-able zImage formats normally set this to a suitable
1837 value in their defconfig file.
1839 If ZBOOT_ROM is not enabled, this has no effect.
1841 config ZBOOT_ROM_BSS
1842 hex "Compressed ROM boot loader BSS address"
1845 The base address of an area of read/write memory in the target
1846 for the ROM-able zImage which must be available while the
1847 decompressor is running. It must be large enough to hold the
1848 entire decompressed kernel plus an additional 128 KiB.
1849 Platforms which normally make use of ROM-able zImage formats
1850 normally set this to a suitable value in their defconfig file.
1852 If ZBOOT_ROM is not enabled, this has no effect.
1855 bool "Compressed boot loader in ROM/flash"
1856 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1857 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1859 Say Y here if you intend to execute your compressed kernel image
1860 (zImage) directly from ROM or flash. If unsure, say N.
1862 config ARM_APPENDED_DTB
1863 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1866 With this option, the boot code will look for a device tree binary
1867 (DTB) appended to zImage
1868 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1870 This is meant as a backward compatibility convenience for those
1871 systems with a bootloader that can't be upgraded to accommodate
1872 the documented boot protocol using a device tree.
1874 Beware that there is very little in terms of protection against
1875 this option being confused by leftover garbage in memory that might
1876 look like a DTB header after a reboot if no actual DTB is appended
1877 to zImage. Do not leave this option active in a production kernel
1878 if you don't intend to always append a DTB. Proper passing of the
1879 location into r2 of a bootloader provided DTB is always preferable
1882 config ARM_ATAG_DTB_COMPAT
1883 bool "Supplement the appended DTB with traditional ATAG information"
1884 depends on ARM_APPENDED_DTB
1886 Some old bootloaders can't be updated to a DTB capable one, yet
1887 they provide ATAGs with memory configuration, the ramdisk address,
1888 the kernel cmdline string, etc. Such information is dynamically
1889 provided by the bootloader and can't always be stored in a static
1890 DTB. To allow a device tree enabled kernel to be used with such
1891 bootloaders, this option allows zImage to extract the information
1892 from the ATAG list and store it at run time into the appended DTB.
1895 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1896 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1898 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1899 bool "Use bootloader kernel arguments if available"
1901 Uses the command-line options passed by the boot loader instead of
1902 the device tree bootargs property. If the boot loader doesn't provide
1903 any, the device tree bootargs property will be used.
1905 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1906 bool "Extend with bootloader kernel arguments"
1908 The command-line arguments provided by the boot loader will be
1909 appended to the the device tree bootargs property.
1914 string "Default kernel command string"
1917 On some architectures (EBSA110 and CATS), there is currently no way
1918 for the boot loader to pass arguments to the kernel. For these
1919 architectures, you should supply some command-line options at build
1920 time by entering them here. As a minimum, you should specify the
1921 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1924 prompt "Kernel command line type" if CMDLINE != ""
1925 default CMDLINE_FROM_BOOTLOADER
1928 config CMDLINE_FROM_BOOTLOADER
1929 bool "Use bootloader kernel arguments if available"
1931 Uses the command-line options passed by the boot loader. If
1932 the boot loader doesn't provide any, the default kernel command
1933 string provided in CMDLINE will be used.
1935 config CMDLINE_EXTEND
1936 bool "Extend bootloader kernel arguments"
1938 The command-line arguments provided by the boot loader will be
1939 appended to the default kernel command string.
1941 config CMDLINE_FORCE
1942 bool "Always use the default kernel command string"
1944 Always use the default kernel command string, even if the boot
1945 loader passes other arguments to the kernel.
1946 This is useful if you cannot or don't want to change the
1947 command-line options your boot loader passes to the kernel.
1951 bool "Kernel Execute-In-Place from ROM"
1952 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1954 Execute-In-Place allows the kernel to run from non-volatile storage
1955 directly addressable by the CPU, such as NOR flash. This saves RAM
1956 space since the text section of the kernel is not loaded from flash
1957 to RAM. Read-write sections, such as the data section and stack,
1958 are still copied to RAM. The XIP kernel is not compressed since
1959 it has to run directly from flash, so it will take more space to
1960 store it. The flash address used to link the kernel object files,
1961 and for storing it, is configuration dependent. Therefore, if you
1962 say Y here, you must know the proper physical address where to
1963 store the kernel image depending on your own flash memory usage.
1965 Also note that the make target becomes "make xipImage" rather than
1966 "make zImage" or "make Image". The final kernel binary to put in
1967 ROM memory will be arch/arm/boot/xipImage.
1971 config XIP_PHYS_ADDR
1972 hex "XIP Kernel Physical Location"
1973 depends on XIP_KERNEL
1974 default "0x00080000"
1976 This is the physical address in your flash memory the kernel will
1977 be linked for and stored to. This address is dependent on your
1980 config XIP_DEFLATED_DATA
1981 bool "Store kernel .data section compressed in ROM"
1982 depends on XIP_KERNEL
1985 Before the kernel is actually executed, its .data section has to be
1986 copied to RAM from ROM. This option allows for storing that data
1987 in compressed form and decompressed to RAM rather than merely being
1988 copied, saving some precious ROM space. A possible drawback is a
1989 slightly longer boot delay.
1992 bool "Kexec system call (EXPERIMENTAL)"
1993 depends on (!SMP || PM_SLEEP_SMP)
1997 kexec is a system call that implements the ability to shutdown your
1998 current kernel, and to start another kernel. It is like a reboot
1999 but it is independent of the system firmware. And like a reboot
2000 you can start any kernel with it, not just Linux.
2002 It is an ongoing process to be certain the hardware in a machine
2003 is properly shutdown, so do not be surprised if this code does not
2004 initially work for you.
2007 bool "Export atags in procfs"
2008 depends on ATAGS && KEXEC
2011 Should the atags used to boot the kernel be exported in an "atags"
2012 file in procfs. Useful with kexec.
2015 bool "Build kdump crash kernel (EXPERIMENTAL)"
2017 Generate crash dump after being started by kexec. This should
2018 be normally only set in special crash dump kernels which are
2019 loaded in the main kernel with kexec-tools into a specially
2020 reserved region and then later executed after a crash by
2021 kdump/kexec. The crash dump kernel must be compiled to a
2022 memory address not used by the main kernel
2024 For more details see Documentation/kdump/kdump.txt
2026 config AUTO_ZRELADDR
2027 bool "Auto calculation of the decompressed kernel image address"
2029 ZRELADDR is the physical address where the decompressed kernel
2030 image will be placed. If AUTO_ZRELADDR is selected, the address
2031 will be determined at run-time by masking the current IP with
2032 0xf8000000. This assumes the zImage being placed in the first 128MB
2033 from start of memory.
2039 bool "UEFI runtime support"
2040 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2042 select EFI_PARAMS_FROM_FDT
2045 select EFI_RUNTIME_WRAPPERS
2047 This option provides support for runtime services provided
2048 by UEFI firmware (such as non-volatile variables, realtime
2049 clock, and platform reset). A UEFI stub is also provided to
2050 allow the kernel to be booted as an EFI application. This
2051 is only useful for kernels that may run on systems that have
2055 bool "Enable support for SMBIOS (DMI) tables"
2059 This enables SMBIOS/DMI feature for systems.
2061 This option is only useful on systems that have UEFI firmware.
2062 However, even with this option, the resultant kernel should
2063 continue to boot on existing non-UEFI platforms.
2065 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2066 i.e., the the practice of identifying the platform via DMI to
2067 decide whether certain workarounds for buggy hardware and/or
2068 firmware need to be enabled. This would require the DMI subsystem
2069 to be enabled much earlier than we do on ARM, which is non-trivial.
2073 menu "CPU Power Management"
2075 source "drivers/cpufreq/Kconfig"
2077 source "drivers/cpuidle/Kconfig"
2081 menu "Floating point emulation"
2083 comment "At least one emulation must be selected"
2086 bool "NWFPE math emulation"
2087 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2089 Say Y to include the NWFPE floating point emulator in the kernel.
2090 This is necessary to run most binaries. Linux does not currently
2091 support floating point hardware so you need to say Y here even if
2092 your machine has an FPA or floating point co-processor podule.
2094 You may say N here if you are going to load the Acorn FPEmulator
2095 early in the bootup.
2098 bool "Support extended precision"
2099 depends on FPE_NWFPE
2101 Say Y to include 80-bit support in the kernel floating-point
2102 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2103 Note that gcc does not generate 80-bit operations by default,
2104 so in most cases this option only enlarges the size of the
2105 floating point emulator without any good reason.
2107 You almost surely want to say N here.
2110 bool "FastFPE math emulation (EXPERIMENTAL)"
2111 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2113 Say Y here to include the FAST floating point emulator in the kernel.
2114 This is an experimental much faster emulator which now also has full
2115 precision for the mantissa. It does not support any exceptions.
2116 It is very simple, and approximately 3-6 times faster than NWFPE.
2118 It should be sufficient for most programs. It may be not suitable
2119 for scientific calculations, but you have to check this for yourself.
2120 If you do not feel you need a faster FP emulation you should better
2124 bool "VFP-format floating point maths"
2125 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2127 Say Y to include VFP support code in the kernel. This is needed
2128 if your hardware includes a VFP unit.
2130 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2131 release notes and additional status information.
2133 Say N if your target does not have VFP hardware.
2141 bool "Advanced SIMD (NEON) Extension support"
2142 depends on VFPv3 && CPU_V7
2144 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2147 config KERNEL_MODE_NEON
2148 bool "Support for NEON in kernel mode"
2149 depends on NEON && AEABI
2151 Say Y to include support for NEON in kernel mode.
2155 menu "Power management options"
2157 source "kernel/power/Kconfig"
2159 config ARCH_SUSPEND_POSSIBLE
2160 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2161 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2164 config ARM_CPU_SUSPEND
2165 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2166 depends on ARCH_SUSPEND_POSSIBLE
2168 config ARCH_HIBERNATION_POSSIBLE
2171 default y if ARCH_SUSPEND_POSSIBLE
2175 source "drivers/firmware/Kconfig"
2178 source "arch/arm/crypto/Kconfig"
2181 source "arch/arm/kvm/Kconfig"