4 select ARCH_CLOCKSOURCE_DATA
5 select ARCH_HAS_DEBUG_VIRTUAL
6 select ARCH_HAS_DEVMEM_IS_ALLOWED
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_SET_MEMORY
9 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
10 select ARCH_HAS_STRICT_MODULE_RWX if MMU
11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
12 select ARCH_HAVE_CUSTOM_GPIO_H
13 select ARCH_HAS_GCOV_PROFILE_ALL
14 select ARCH_MIGHT_HAVE_PC_PARPORT
15 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
16 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
17 select ARCH_SUPPORTS_ATOMIC_RMW
18 select ARCH_USE_BUILTIN_BSWAP
19 select ARCH_USE_CMPXCHG_LOCKREF
20 select ARCH_WANT_IPC_PARSE_VERSION
21 select BUILDTIME_EXTABLE_SORT if MMU
22 select CLONE_BACKWARDS
23 select CPU_PM if (SUSPEND || CPU_IDLE)
24 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
25 select DMA_NOOP_OPS if !MMU
27 select EDAC_ATOMIC_SCRUB
28 select GENERIC_ALLOCATOR
29 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
30 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
31 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
32 select GENERIC_CPU_AUTOPROBE
33 select GENERIC_EARLY_IOREMAP
34 select GENERIC_IDLE_POLL_SETUP
35 select GENERIC_IRQ_PROBE
36 select GENERIC_IRQ_SHOW
37 select GENERIC_IRQ_SHOW_LEVEL
38 select GENERIC_PCI_IOMAP
39 select GENERIC_SCHED_CLOCK
40 select GENERIC_SMP_IDLE_THREAD
41 select GENERIC_STRNCPY_FROM_USER
42 select GENERIC_STRNLEN_USER
43 select HANDLE_DOMAIN_IRQ
44 select HARDIRQS_SW_RESEND
45 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
46 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
47 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
48 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
49 select HAVE_ARCH_MMAP_RND_BITS if MMU
50 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
51 select HAVE_ARCH_TRACEHOOK
52 select HAVE_ARM_SMCCC if CPU_V7
54 select HAVE_CC_STACKPROTECTOR
55 select HAVE_CONTEXT_TRACKING
56 select HAVE_C_RECORDMCOUNT
57 select HAVE_DEBUG_KMEMLEAK
58 select HAVE_DMA_API_DEBUG
59 select HAVE_DMA_CONTIGUOUS if MMU
60 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
61 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
62 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
63 select HAVE_EXIT_THREAD
64 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
65 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
66 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
67 select HAVE_GCC_PLUGINS
68 select HAVE_GENERIC_DMA_COHERENT
69 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
70 select HAVE_IDE if PCI || ISA || PCMCIA
71 select HAVE_IRQ_TIME_ACCOUNTING
72 select HAVE_KERNEL_GZIP
73 select HAVE_KERNEL_LZ4
74 select HAVE_KERNEL_LZMA
75 select HAVE_KERNEL_LZO
77 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
78 select HAVE_KRETPROBES if (HAVE_KPROBES)
80 select HAVE_MOD_ARCH_SPECIFIC
82 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
83 select HAVE_OPTPROBES if !THUMB2_KERNEL
84 select HAVE_PERF_EVENTS
86 select HAVE_PERF_USER_STACK_DUMP
87 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
88 select HAVE_REGS_AND_STACK_ACCESS_API
89 select HAVE_SYSCALL_TRACEPOINTS
91 select HAVE_VIRT_CPU_ACCOUNTING_GEN
92 select IRQ_FORCED_THREADING
93 select MODULES_USE_ELF_REL
95 select OF_EARLY_FLATTREE if OF
96 select OF_RESERVED_MEM if OF
98 select OLD_SIGSUSPEND3
99 select PERF_USE_VMALLOC
101 select SYS_SUPPORTS_APM_EMULATION
102 # Above selects are sorted alphabetically; please add new ones
103 # according to that. Thanks.
105 The ARM series is a line of low-power-consumption RISC chip designs
106 licensed by ARM Ltd and targeted at embedded applications and
107 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
108 manufactured, but legacy ARM-based PC hardware remains popular in
109 Europe. There is an ARM Linux project with a web page at
110 <http://www.arm.linux.org.uk/>.
112 config ARM_HAS_SG_CHAIN
113 select ARCH_HAS_SG_CHAIN
116 config NEED_SG_DMA_LENGTH
119 config ARM_DMA_USE_IOMMU
121 select ARM_HAS_SG_CHAIN
122 select NEED_SG_DMA_LENGTH
126 config ARM_DMA_IOMMU_ALIGNMENT
127 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
131 DMA mapping framework by default aligns all buffers to the smallest
132 PAGE_SIZE order which is greater than or equal to the requested buffer
133 size. This works well for buffers up to a few hundreds kilobytes, but
134 for larger buffers it just a waste of address space. Drivers which has
135 relatively small addressing window (like 64Mib) might run out of
136 virtual space with just a few allocations.
138 With this parameter you can specify the maximum PAGE_SIZE order for
139 DMA IOMMU buffers. Larger buffers will be aligned only to this
140 specified order. The order is expressed as a power of two multiplied
145 config MIGHT_HAVE_PCI
148 config SYS_SUPPORTS_APM_EMULATION
153 select GENERIC_ALLOCATOR
164 The Extended Industry Standard Architecture (EISA) bus was
165 developed as an open alternative to the IBM MicroChannel bus.
167 The EISA bus provided some of the features of the IBM MicroChannel
168 bus while maintaining backward compatibility with cards made for
169 the older ISA bus. The EISA bus saw limited use between 1988 and
170 1995 when it was made obsolete by the PCI bus.
172 Say Y here if you are building a kernel for an EISA-based machine.
179 config STACKTRACE_SUPPORT
183 config LOCKDEP_SUPPORT
187 config TRACE_IRQFLAGS_SUPPORT
191 config RWSEM_XCHGADD_ALGORITHM
195 config ARCH_HAS_ILOG2_U32
198 config ARCH_HAS_ILOG2_U64
201 config ARCH_HAS_BANDGAP
204 config FIX_EARLYCON_MEM
207 config GENERIC_HWEIGHT
211 config GENERIC_CALIBRATE_DELAY
215 config ARCH_MAY_HAVE_PC_FDC
221 config NEED_DMA_MAP_STATE
224 config ARCH_SUPPORTS_UPROBES
227 config ARCH_HAS_DMA_SET_COHERENT_MASK
230 config GENERIC_ISA_DMA
236 config NEED_RET_TO_USER
244 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
245 default DRAM_BASE if REMAP_VECTORS_TO_RAM
248 The base address of exception vectors. This must be two pages
251 config ARM_PATCH_PHYS_VIRT
252 bool "Patch physical to virtual translations at runtime" if EMBEDDED
254 depends on !XIP_KERNEL && MMU
256 Patch phys-to-virt and virt-to-phys translation functions at
257 boot and module load time according to the position of the
258 kernel in system memory.
260 This can only be used with non-XIP MMU kernels where the base
261 of physical memory is at a 16MB boundary.
263 Only disable this option if you know that you do not require
264 this feature (eg, building a kernel for a single machine) and
265 you need to shrink the kernel to the minimal size.
267 config NEED_MACH_IO_H
270 Select this when mach/io.h is required to provide special
271 definitions for this platform. The need for mach/io.h should
272 be avoided when possible.
274 config NEED_MACH_MEMORY_H
277 Select this when mach/memory.h is required to provide special
278 definitions for this platform. The need for mach/memory.h should
279 be avoided when possible.
282 hex "Physical address of main memory" if MMU
283 depends on !ARM_PATCH_PHYS_VIRT
284 default DRAM_BASE if !MMU
285 default 0x00000000 if ARCH_EBSA110 || \
291 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
292 default 0x20000000 if ARCH_S5PV210
293 default 0xc0000000 if ARCH_SA1100
295 Please provide the physical address corresponding to the
296 location of main memory in your system.
302 config PGTABLE_LEVELS
304 default 3 if ARM_LPAE
307 source "init/Kconfig"
309 source "kernel/Kconfig.freezer"
314 bool "MMU-based Paged Memory Management Support"
317 Select if you want MMU-based virtualised addressing space
318 support by paged memory management. If unsure, say 'Y'.
320 config ARCH_MMAP_RND_BITS_MIN
323 config ARCH_MMAP_RND_BITS_MAX
324 default 14 if PAGE_OFFSET=0x40000000
325 default 15 if PAGE_OFFSET=0x80000000
329 # The "ARM system type" choice list is ordered alphabetically by option
330 # text. Please add new entries in the option alphabetic order.
333 prompt "ARM system type"
334 default ARM_SINGLE_ARMV7M if !MMU
335 default ARCH_MULTIPLATFORM if MMU
337 config ARCH_MULTIPLATFORM
338 bool "Allow multiple platforms to be selected"
340 select ARM_HAS_SG_CHAIN
341 select ARM_PATCH_PHYS_VIRT
345 select GENERIC_CLOCKEVENTS
346 select MIGHT_HAVE_PCI
347 select MULTI_IRQ_HANDLER
348 select PCI_DOMAINS if PCI
352 config ARM_SINGLE_ARMV7M
353 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
360 select GENERIC_CLOCKEVENTS
367 select ARCH_USES_GETTIMEOFFSET
370 select NEED_MACH_IO_H
371 select NEED_MACH_MEMORY_H
374 This is an evaluation board for the StrongARM processor available
375 from Digital. It has limited hardware on-board, including an
376 Ethernet interface, two PCMCIA sockets, two serial ports and a
381 select ARCH_HAS_HOLES_MEMORYMODEL
383 select ARM_PATCH_PHYS_VIRT
389 select GENERIC_CLOCKEVENTS
392 This enables support for the Cirrus EP93xx series of CPUs.
394 config ARCH_FOOTBRIDGE
398 select GENERIC_CLOCKEVENTS
400 select NEED_MACH_IO_H if !MMU
401 select NEED_MACH_MEMORY_H
403 Support for systems based on the DC21285 companion chip
404 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
407 bool "Hilscher NetX based"
411 select GENERIC_CLOCKEVENTS
413 This enables support for systems based on the Hilscher NetX Soc
419 select NEED_MACH_MEMORY_H
420 select NEED_RET_TO_USER
426 Support for Intel's IOP13XX (XScale) family of processors.
434 select NEED_RET_TO_USER
438 Support for Intel's 80219 and IOP32X (XScale) family of
447 select NEED_RET_TO_USER
451 Support for Intel's IOP33X (XScale) family of processors.
456 select ARCH_HAS_DMA_SET_COHERENT_MASK
457 select ARCH_SUPPORTS_BIG_ENDIAN
460 select DMABOUNCE if PCI
461 select GENERIC_CLOCKEVENTS
463 select MIGHT_HAVE_PCI
464 select NEED_MACH_IO_H
465 select USB_EHCI_BIG_ENDIAN_DESC
466 select USB_EHCI_BIG_ENDIAN_MMIO
468 Support for Intel's IXP4XX (XScale) family of processors.
473 select GENERIC_CLOCKEVENTS
475 select MIGHT_HAVE_PCI
476 select MULTI_IRQ_HANDLER
480 select PLAT_ORION_LEGACY
482 select PM_GENERIC_DOMAINS if PM
484 Support for the Marvell Dove SoC 88AP510
487 bool "Micrel/Kendin KS8695"
490 select GENERIC_CLOCKEVENTS
492 select NEED_MACH_MEMORY_H
494 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
495 System-on-Chip devices.
498 bool "Nuvoton W90X900 CPU"
502 select GENERIC_CLOCKEVENTS
505 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
506 At present, the w90x900 has been renamed nuc900, regarding
507 the ARM series product line, you can login the following
508 link address to know more.
510 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
511 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
517 select CLKSRC_LPC32XX
520 select GENERIC_CLOCKEVENTS
522 select MULTI_IRQ_HANDLER
526 Support for the NXP LPC32XX family of processors
529 bool "PXA2xx/PXA3xx-based"
532 select ARM_CPU_SUSPEND if PM
539 select CPU_XSCALE if !CPU_XSC3
540 select GENERIC_CLOCKEVENTS
545 select MULTI_IRQ_HANDLER
549 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
555 select ARCH_MAY_HAVE_PC_FDC
556 select ARCH_SPARSEMEM_ENABLE
557 select ARCH_USES_GETTIMEOFFSET
561 select HAVE_PATA_PLATFORM
563 select NEED_MACH_IO_H
564 select NEED_MACH_MEMORY_H
567 On the Acorn Risc-PC, Linux can support the internal IDE disk and
568 CD-ROM interface, serial and parallel port, and the floppy drive.
573 select ARCH_SPARSEMEM_ENABLE
577 select TIMER_OF if OF
580 select GENERIC_CLOCKEVENTS
585 select MULTI_IRQ_HANDLER
586 select NEED_MACH_MEMORY_H
589 Support for StrongARM 11x0 based boards.
592 bool "Samsung S3C24XX SoCs"
595 select CLKSRC_SAMSUNG_PWM
596 select GENERIC_CLOCKEVENTS
599 select HAVE_S3C2410_I2C if I2C
600 select HAVE_S3C2410_WATCHDOG if WATCHDOG
601 select HAVE_S3C_RTC if RTC_CLASS
602 select MULTI_IRQ_HANDLER
603 select NEED_MACH_IO_H
606 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
607 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
608 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
609 Samsung SMDK2410 development board (and derivatives).
613 select ARCH_HAS_HOLES_MEMORYMODEL
616 select GENERIC_ALLOCATOR
617 select GENERIC_CLOCKEVENTS
618 select GENERIC_IRQ_CHIP
624 Support for TI's DaVinci platform.
629 select ARCH_HAS_HOLES_MEMORYMODEL
633 select GENERIC_CLOCKEVENTS
634 select GENERIC_IRQ_CHIP
638 select MULTI_IRQ_HANDLER
639 select NEED_MACH_IO_H if PCCARD
640 select NEED_MACH_MEMORY_H
643 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
647 menu "Multiple platform selection"
648 depends on ARCH_MULTIPLATFORM
650 comment "CPU Core family selection"
653 bool "ARMv4 based platforms (FA526)"
654 depends on !ARCH_MULTI_V6_V7
655 select ARCH_MULTI_V4_V5
658 config ARCH_MULTI_V4T
659 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
660 depends on !ARCH_MULTI_V6_V7
661 select ARCH_MULTI_V4_V5
662 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
663 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
664 CPU_ARM925T || CPU_ARM940T)
667 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
668 depends on !ARCH_MULTI_V6_V7
669 select ARCH_MULTI_V4_V5
670 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
671 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
672 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
674 config ARCH_MULTI_V4_V5
678 bool "ARMv6 based platforms (ARM11)"
679 select ARCH_MULTI_V6_V7
683 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
685 select ARCH_MULTI_V6_V7
689 config ARCH_MULTI_V6_V7
691 select MIGHT_HAVE_CACHE_L2X0
693 config ARCH_MULTI_CPU_AUTO
694 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
700 bool "Dummy Virtual Machine"
701 depends on ARCH_MULTI_V7
704 select ARM_GIC_V2M if PCI
706 select ARM_GIC_V3_ITS if PCI
708 select HAVE_ARM_ARCH_TIMER
711 # This is sorted alphabetically by mach-* pathname. However, plat-*
712 # Kconfigs may be included either alphabetically (according to the
713 # plat- suffix) or along side the corresponding mach-* source.
715 source "arch/arm/mach-mvebu/Kconfig"
717 source "arch/arm/mach-actions/Kconfig"
719 source "arch/arm/mach-alpine/Kconfig"
721 source "arch/arm/mach-artpec/Kconfig"
723 source "arch/arm/mach-asm9260/Kconfig"
725 source "arch/arm/mach-at91/Kconfig"
727 source "arch/arm/mach-axxia/Kconfig"
729 source "arch/arm/mach-bcm/Kconfig"
731 source "arch/arm/mach-berlin/Kconfig"
733 source "arch/arm/mach-clps711x/Kconfig"
735 source "arch/arm/mach-cns3xxx/Kconfig"
737 source "arch/arm/mach-davinci/Kconfig"
739 source "arch/arm/mach-digicolor/Kconfig"
741 source "arch/arm/mach-dove/Kconfig"
743 source "arch/arm/mach-ep93xx/Kconfig"
745 source "arch/arm/mach-footbridge/Kconfig"
747 source "arch/arm/mach-gemini/Kconfig"
749 source "arch/arm/mach-highbank/Kconfig"
751 source "arch/arm/mach-hisi/Kconfig"
753 source "arch/arm/mach-integrator/Kconfig"
755 source "arch/arm/mach-iop32x/Kconfig"
757 source "arch/arm/mach-iop33x/Kconfig"
759 source "arch/arm/mach-iop13xx/Kconfig"
761 source "arch/arm/mach-ixp4xx/Kconfig"
763 source "arch/arm/mach-keystone/Kconfig"
765 source "arch/arm/mach-ks8695/Kconfig"
767 source "arch/arm/mach-meson/Kconfig"
769 source "arch/arm/mach-moxart/Kconfig"
771 source "arch/arm/mach-aspeed/Kconfig"
773 source "arch/arm/mach-mv78xx0/Kconfig"
775 source "arch/arm/mach-imx/Kconfig"
777 source "arch/arm/mach-mediatek/Kconfig"
779 source "arch/arm/mach-mxs/Kconfig"
781 source "arch/arm/mach-netx/Kconfig"
783 source "arch/arm/mach-nomadik/Kconfig"
785 source "arch/arm/mach-nspire/Kconfig"
787 source "arch/arm/plat-omap/Kconfig"
789 source "arch/arm/mach-omap1/Kconfig"
791 source "arch/arm/mach-omap2/Kconfig"
793 source "arch/arm/mach-orion5x/Kconfig"
795 source "arch/arm/mach-picoxcell/Kconfig"
797 source "arch/arm/mach-pxa/Kconfig"
798 source "arch/arm/plat-pxa/Kconfig"
800 source "arch/arm/mach-mmp/Kconfig"
802 source "arch/arm/mach-oxnas/Kconfig"
804 source "arch/arm/mach-qcom/Kconfig"
806 source "arch/arm/mach-realview/Kconfig"
808 source "arch/arm/mach-rockchip/Kconfig"
810 source "arch/arm/mach-sa1100/Kconfig"
812 source "arch/arm/mach-socfpga/Kconfig"
814 source "arch/arm/mach-spear/Kconfig"
816 source "arch/arm/mach-sti/Kconfig"
818 source "arch/arm/mach-stm32/Kconfig"
820 source "arch/arm/mach-s3c24xx/Kconfig"
822 source "arch/arm/mach-s3c64xx/Kconfig"
824 source "arch/arm/mach-s5pv210/Kconfig"
826 source "arch/arm/mach-exynos/Kconfig"
827 source "arch/arm/plat-samsung/Kconfig"
829 source "arch/arm/mach-shmobile/Kconfig"
831 source "arch/arm/mach-sunxi/Kconfig"
833 source "arch/arm/mach-prima2/Kconfig"
835 source "arch/arm/mach-tango/Kconfig"
837 source "arch/arm/mach-tegra/Kconfig"
839 source "arch/arm/mach-u300/Kconfig"
841 source "arch/arm/mach-uniphier/Kconfig"
843 source "arch/arm/mach-ux500/Kconfig"
845 source "arch/arm/mach-versatile/Kconfig"
847 source "arch/arm/mach-vexpress/Kconfig"
848 source "arch/arm/plat-versatile/Kconfig"
850 source "arch/arm/mach-vt8500/Kconfig"
852 source "arch/arm/mach-w90x900/Kconfig"
854 source "arch/arm/mach-zx/Kconfig"
856 source "arch/arm/mach-zynq/Kconfig"
858 # ARMv7-M architecture
860 bool "Energy Micro efm32"
861 depends on ARM_SINGLE_ARMV7M
864 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
868 bool "NXP LPC18xx/LPC43xx"
869 depends on ARM_SINGLE_ARMV7M
870 select ARCH_HAS_RESET_CONTROLLER
872 select CLKSRC_LPC32XX
875 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
876 high performance microcontrollers.
879 bool "ARM MPS2 platform"
880 depends on ARM_SINGLE_ARMV7M
884 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
885 with a range of available cores like Cortex-M3/M4/M7.
887 Please, note that depends which Application Note is used memory map
888 for the platform may vary, so adjustment of RAM base might be needed.
890 # Definitions to make life easier
896 select GENERIC_CLOCKEVENTS
902 select GENERIC_IRQ_CHIP
905 config PLAT_ORION_LEGACY
912 config PLAT_VERSATILE
915 source "arch/arm/firmware/Kconfig"
917 source arch/arm/mm/Kconfig
920 bool "Enable iWMMXt support"
921 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
922 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
924 Enable support for iWMMXt context switching at run time if
925 running on a CPU that supports it.
927 config MULTI_IRQ_HANDLER
930 Allow each machine to specify it's own IRQ handler at run time.
933 source "arch/arm/Kconfig-nommu"
936 config PJ4B_ERRATA_4742
937 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
938 depends on CPU_PJ4B && MACH_ARMADA_370
941 When coming out of either a Wait for Interrupt (WFI) or a Wait for
942 Event (WFE) IDLE states, a specific timing sensitivity exists between
943 the retiring WFI/WFE instructions and the newly issued subsequent
944 instructions. This sensitivity can result in a CPU hang scenario.
946 The software must insert either a Data Synchronization Barrier (DSB)
947 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
950 config ARM_ERRATA_326103
951 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
954 Executing a SWP instruction to read-only memory does not set bit 11
955 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
956 treat the access as a read, preventing a COW from occurring and
957 causing the faulting task to livelock.
959 config ARM_ERRATA_411920
960 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
961 depends on CPU_V6 || CPU_V6K
963 Invalidation of the Instruction Cache operation can
964 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
965 It does not affect the MPCore. This option enables the ARM Ltd.
966 recommended workaround.
968 config ARM_ERRATA_430973
969 bool "ARM errata: Stale prediction on replaced interworking branch"
972 This option enables the workaround for the 430973 Cortex-A8
973 r1p* erratum. If a code sequence containing an ARM/Thumb
974 interworking branch is replaced with another code sequence at the
975 same virtual address, whether due to self-modifying code or virtual
976 to physical address re-mapping, Cortex-A8 does not recover from the
977 stale interworking branch prediction. This results in Cortex-A8
978 executing the new code sequence in the incorrect ARM or Thumb state.
979 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
980 and also flushes the branch target cache at every context switch.
981 Note that setting specific bits in the ACTLR register may not be
982 available in non-secure mode.
984 config ARM_ERRATA_458693
985 bool "ARM errata: Processor deadlock when a false hazard is created"
987 depends on !ARCH_MULTIPLATFORM
989 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
990 erratum. For very specific sequences of memory operations, it is
991 possible for a hazard condition intended for a cache line to instead
992 be incorrectly associated with a different cache line. This false
993 hazard might then cause a processor deadlock. The workaround enables
994 the L1 caching of the NEON accesses and disables the PLD instruction
995 in the ACTLR register. Note that setting specific bits in the ACTLR
996 register may not be available in non-secure mode.
998 config ARM_ERRATA_460075
999 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1001 depends on !ARCH_MULTIPLATFORM
1003 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1004 erratum. Any asynchronous access to the L2 cache may encounter a
1005 situation in which recent store transactions to the L2 cache are lost
1006 and overwritten with stale memory contents from external memory. The
1007 workaround disables the write-allocate mode for the L2 cache via the
1008 ACTLR register. Note that setting specific bits in the ACTLR register
1009 may not be available in non-secure mode.
1011 config ARM_ERRATA_742230
1012 bool "ARM errata: DMB operation may be faulty"
1013 depends on CPU_V7 && SMP
1014 depends on !ARCH_MULTIPLATFORM
1016 This option enables the workaround for the 742230 Cortex-A9
1017 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1018 between two write operations may not ensure the correct visibility
1019 ordering of the two writes. This workaround sets a specific bit in
1020 the diagnostic register of the Cortex-A9 which causes the DMB
1021 instruction to behave as a DSB, ensuring the correct behaviour of
1024 config ARM_ERRATA_742231
1025 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1026 depends on CPU_V7 && SMP
1027 depends on !ARCH_MULTIPLATFORM
1029 This option enables the workaround for the 742231 Cortex-A9
1030 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1031 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1032 accessing some data located in the same cache line, may get corrupted
1033 data due to bad handling of the address hazard when the line gets
1034 replaced from one of the CPUs at the same time as another CPU is
1035 accessing it. This workaround sets specific bits in the diagnostic
1036 register of the Cortex-A9 which reduces the linefill issuing
1037 capabilities of the processor.
1039 config ARM_ERRATA_643719
1040 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1041 depends on CPU_V7 && SMP
1044 This option enables the workaround for the 643719 Cortex-A9 (prior to
1045 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1046 register returns zero when it should return one. The workaround
1047 corrects this value, ensuring cache maintenance operations which use
1048 it behave as intended and avoiding data corruption.
1050 config ARM_ERRATA_720789
1051 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1054 This option enables the workaround for the 720789 Cortex-A9 (prior to
1055 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1056 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1057 As a consequence of this erratum, some TLB entries which should be
1058 invalidated are not, resulting in an incoherency in the system page
1059 tables. The workaround changes the TLB flushing routines to invalidate
1060 entries regardless of the ASID.
1062 config ARM_ERRATA_743622
1063 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1065 depends on !ARCH_MULTIPLATFORM
1067 This option enables the workaround for the 743622 Cortex-A9
1068 (r2p*) erratum. Under very rare conditions, a faulty
1069 optimisation in the Cortex-A9 Store Buffer may lead to data
1070 corruption. This workaround sets a specific bit in the diagnostic
1071 register of the Cortex-A9 which disables the Store Buffer
1072 optimisation, preventing the defect from occurring. This has no
1073 visible impact on the overall performance or power consumption of the
1076 config ARM_ERRATA_751472
1077 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1079 depends on !ARCH_MULTIPLATFORM
1081 This option enables the workaround for the 751472 Cortex-A9 (prior
1082 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1083 completion of a following broadcasted operation if the second
1084 operation is received by a CPU before the ICIALLUIS has completed,
1085 potentially leading to corrupted entries in the cache or TLB.
1087 config ARM_ERRATA_754322
1088 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1091 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1092 r3p*) erratum. A speculative memory access may cause a page table walk
1093 which starts prior to an ASID switch but completes afterwards. This
1094 can populate the micro-TLB with a stale entry which may be hit with
1095 the new ASID. This workaround places two dsb instructions in the mm
1096 switching code so that no page table walks can cross the ASID switch.
1098 config ARM_ERRATA_754327
1099 bool "ARM errata: no automatic Store Buffer drain"
1100 depends on CPU_V7 && SMP
1102 This option enables the workaround for the 754327 Cortex-A9 (prior to
1103 r2p0) erratum. The Store Buffer does not have any automatic draining
1104 mechanism and therefore a livelock may occur if an external agent
1105 continuously polls a memory location waiting to observe an update.
1106 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1107 written polling loops from denying visibility of updates to memory.
1109 config ARM_ERRATA_364296
1110 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1113 This options enables the workaround for the 364296 ARM1136
1114 r0p2 erratum (possible cache data corruption with
1115 hit-under-miss enabled). It sets the undocumented bit 31 in
1116 the auxiliary control register and the FI bit in the control
1117 register, thus disabling hit-under-miss without putting the
1118 processor into full low interrupt latency mode. ARM11MPCore
1121 config ARM_ERRATA_764369
1122 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1123 depends on CPU_V7 && SMP
1125 This option enables the workaround for erratum 764369
1126 affecting Cortex-A9 MPCore with two or more processors (all
1127 current revisions). Under certain timing circumstances, a data
1128 cache line maintenance operation by MVA targeting an Inner
1129 Shareable memory region may fail to proceed up to either the
1130 Point of Coherency or to the Point of Unification of the
1131 system. This workaround adds a DSB instruction before the
1132 relevant cache maintenance functions and sets a specific bit
1133 in the diagnostic control register of the SCU.
1135 config ARM_ERRATA_775420
1136 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1139 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1140 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1141 operation aborts with MMU exception, it might cause the processor
1142 to deadlock. This workaround puts DSB before executing ISB if
1143 an abort may occur on cache maintenance.
1145 config ARM_ERRATA_798181
1146 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1147 depends on CPU_V7 && SMP
1149 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1150 adequately shooting down all use of the old entries. This
1151 option enables the Linux kernel workaround for this erratum
1152 which sends an IPI to the CPUs that are running the same ASID
1153 as the one being invalidated.
1155 config ARM_ERRATA_773022
1156 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1159 This option enables the workaround for the 773022 Cortex-A15
1160 (up to r0p4) erratum. In certain rare sequences of code, the
1161 loop buffer may deliver incorrect instructions. This
1162 workaround disables the loop buffer to avoid the erratum.
1164 config ARM_ERRATA_818325_852422
1165 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1168 This option enables the workaround for:
1169 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1170 instruction might deadlock. Fixed in r0p1.
1171 - Cortex-A12 852422: Execution of a sequence of instructions might
1172 lead to either a data corruption or a CPU deadlock. Not fixed in
1173 any Cortex-A12 cores yet.
1174 This workaround for all both errata involves setting bit[12] of the
1175 Feature Register. This bit disables an optimisation applied to a
1176 sequence of 2 instructions that use opposing condition codes.
1178 config ARM_ERRATA_821420
1179 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1182 This option enables the workaround for the 821420 Cortex-A12
1183 (all revs) erratum. In very rare timing conditions, a sequence
1184 of VMOV to Core registers instructions, for which the second
1185 one is in the shadow of a branch or abort, can lead to a
1186 deadlock when the VMOV instructions are issued out-of-order.
1188 config ARM_ERRATA_825619
1189 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1192 This option enables the workaround for the 825619 Cortex-A12
1193 (all revs) erratum. Within rare timing constraints, executing a
1194 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1195 and Device/Strongly-Ordered loads and stores might cause deadlock
1197 config ARM_ERRATA_852421
1198 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1201 This option enables the workaround for the 852421 Cortex-A17
1202 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1203 execution of a DMB ST instruction might fail to properly order
1204 stores from GroupA and stores from GroupB.
1206 config ARM_ERRATA_852423
1207 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1210 This option enables the workaround for:
1211 - Cortex-A17 852423: Execution of a sequence of instructions might
1212 lead to either a data corruption or a CPU deadlock. Not fixed in
1213 any Cortex-A17 cores yet.
1214 This is identical to Cortex-A12 erratum 852422. It is a separate
1215 config option from the A12 erratum due to the way errata are checked
1220 source "arch/arm/common/Kconfig"
1227 Find out whether you have ISA slots on your motherboard. ISA is the
1228 name of a bus system, i.e. the way the CPU talks to the other stuff
1229 inside your box. Other bus systems are PCI, EISA, MicroChannel
1230 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1231 newer boards don't support it. If you have ISA, say Y, otherwise N.
1233 # Select ISA DMA controller support
1238 # Select ISA DMA interface
1243 bool "PCI support" if MIGHT_HAVE_PCI
1245 Find out whether you have a PCI motherboard. PCI is the name of a
1246 bus system, i.e. the way the CPU talks to the other stuff inside
1247 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1248 VESA. If you have PCI, say Y, otherwise N.
1254 config PCI_DOMAINS_GENERIC
1255 def_bool PCI_DOMAINS
1257 config PCI_NANOENGINE
1258 bool "BSE nanoEngine PCI support"
1259 depends on SA1100_NANOENGINE
1261 Enable PCI on the BSE nanoEngine board.
1266 config PCI_HOST_ITE8152
1268 depends on PCI && MACH_ARMCORE
1272 source "drivers/pci/Kconfig"
1274 source "drivers/pcmcia/Kconfig"
1278 menu "Kernel Features"
1283 This option should be selected by machines which have an SMP-
1286 The only effect of this option is to make the SMP-related
1287 options available to the user for configuration.
1290 bool "Symmetric Multi-Processing"
1291 depends on CPU_V6K || CPU_V7
1292 depends on GENERIC_CLOCKEVENTS
1294 depends on MMU || ARM_MPU
1297 This enables support for systems with more than one CPU. If you have
1298 a system with only one CPU, say N. If you have a system with more
1299 than one CPU, say Y.
1301 If you say N here, the kernel will run on uni- and multiprocessor
1302 machines, but will use only one CPU of a multiprocessor machine. If
1303 you say Y here, the kernel will run on many, but not all,
1304 uniprocessor machines. On a uniprocessor machine, the kernel
1305 will run faster if you say N here.
1307 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1308 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1309 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1311 If you don't know what to do here, say N.
1314 bool "Allow booting SMP kernel on uniprocessor systems"
1315 depends on SMP && !XIP_KERNEL && MMU
1318 SMP kernels contain instructions which fail on non-SMP processors.
1319 Enabling this option allows the kernel to modify itself to make
1320 these instructions safe. Disabling it allows about 1K of space
1323 If you don't know what to do here, say Y.
1325 config ARM_CPU_TOPOLOGY
1326 bool "Support cpu topology definition"
1327 depends on SMP && CPU_V7
1330 Support ARM cpu topology definition. The MPIDR register defines
1331 affinity between processors which is then used to describe the cpu
1332 topology of an ARM System.
1335 bool "Multi-core scheduler support"
1336 depends on ARM_CPU_TOPOLOGY
1338 Multi-core scheduler support improves the CPU scheduler's decision
1339 making when dealing with multi-core CPU chips at a cost of slightly
1340 increased overhead in some places. If unsure say N here.
1343 bool "SMT scheduler support"
1344 depends on ARM_CPU_TOPOLOGY
1346 Improves the CPU scheduler's decision making when dealing with
1347 MultiThreading at a cost of slightly increased overhead in some
1348 places. If unsure say N here.
1353 This option enables support for the ARM system coherency unit
1355 config HAVE_ARM_ARCH_TIMER
1356 bool "Architected timer support"
1358 select ARM_ARCH_TIMER
1359 select GENERIC_CLOCKEVENTS
1361 This option enables support for the ARM architected timer
1365 select TIMER_OF if OF
1367 This options enables support for the ARM timer and watchdog unit
1370 bool "Multi-Cluster Power Management"
1371 depends on CPU_V7 && SMP
1373 This option provides the common power management infrastructure
1374 for (multi-)cluster based systems, such as big.LITTLE based
1377 config MCPM_QUAD_CLUSTER
1381 To avoid wasting resources unnecessarily, MCPM only supports up
1382 to 2 clusters by default.
1383 Platforms with 3 or 4 clusters that use MCPM must select this
1384 option to allow the additional clusters to be managed.
1387 bool "big.LITTLE support (Experimental)"
1388 depends on CPU_V7 && SMP
1391 This option enables support selections for the big.LITTLE
1392 system architecture.
1395 bool "big.LITTLE switcher support"
1396 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1399 The big.LITTLE "switcher" provides the core functionality to
1400 transparently handle transition between a cluster of A15's
1401 and a cluster of A7's in a big.LITTLE system.
1403 config BL_SWITCHER_DUMMY_IF
1404 tristate "Simple big.LITTLE switcher user interface"
1405 depends on BL_SWITCHER && DEBUG_KERNEL
1407 This is a simple and dummy char dev interface to control
1408 the big.LITTLE switcher core code. It is meant for
1409 debugging purposes only.
1412 prompt "Memory split"
1416 Select the desired split between kernel and user memory.
1418 If you are not absolutely sure what you are doing, leave this
1422 bool "3G/1G user/kernel split"
1423 config VMSPLIT_3G_OPT
1424 depends on !ARM_LPAE
1425 bool "3G/1G user/kernel split (for full 1G low memory)"
1427 bool "2G/2G user/kernel split"
1429 bool "1G/3G user/kernel split"
1434 default PHYS_OFFSET if !MMU
1435 default 0x40000000 if VMSPLIT_1G
1436 default 0x80000000 if VMSPLIT_2G
1437 default 0xB0000000 if VMSPLIT_3G_OPT
1441 int "Maximum number of CPUs (2-32)"
1447 bool "Support for hot-pluggable CPUs"
1450 Say Y here to experiment with turning CPUs off and on. CPUs
1451 can be controlled through /sys/devices/system/cpu.
1454 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1455 depends on HAVE_ARM_SMCCC
1458 Say Y here if you want Linux to communicate with system firmware
1459 implementing the PSCI specification for CPU-centric power
1460 management operations described in ARM document number ARM DEN
1461 0022A ("Power State Coordination Interface System Software on
1464 # The GPIO number here must be sorted by descending number. In case of
1465 # a multiplatform kernel, we just want the highest value required by the
1466 # selected platforms.
1469 default 2048 if ARCH_SOCFPGA
1470 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1472 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1473 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1474 default 416 if ARCH_SUNXI
1475 default 392 if ARCH_U8500
1476 default 352 if ARCH_VT8500
1477 default 288 if ARCH_ROCKCHIP
1478 default 264 if MACH_H4700
1481 Maximum number of GPIOs in the system.
1483 If unsure, leave the default value.
1485 source kernel/Kconfig.preempt
1489 default 200 if ARCH_EBSA110
1490 default 128 if SOC_AT91RM9200
1494 depends on HZ_FIXED = 0
1495 prompt "Timer frequency"
1519 default HZ_FIXED if HZ_FIXED != 0
1520 default 100 if HZ_100
1521 default 200 if HZ_200
1522 default 250 if HZ_250
1523 default 300 if HZ_300
1524 default 500 if HZ_500
1528 def_bool HIGH_RES_TIMERS
1530 config THUMB2_KERNEL
1531 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1532 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1533 default y if CPU_THUMBONLY
1535 select ARM_ASM_UNIFIED
1538 By enabling this option, the kernel will be compiled in
1539 Thumb-2 mode. A compiler/assembler that understand the unified
1540 ARM-Thumb syntax is needed.
1544 config THUMB2_AVOID_R_ARM_THM_JUMP11
1545 bool "Work around buggy Thumb-2 short branch relocations in gas"
1546 depends on THUMB2_KERNEL && MODULES
1549 Various binutils versions can resolve Thumb-2 branches to
1550 locally-defined, preemptible global symbols as short-range "b.n"
1551 branch instructions.
1553 This is a problem, because there's no guarantee the final
1554 destination of the symbol, or any candidate locations for a
1555 trampoline, are within range of the branch. For this reason, the
1556 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1557 relocation in modules at all, and it makes little sense to add
1560 The symptom is that the kernel fails with an "unsupported
1561 relocation" error when loading some modules.
1563 Until fixed tools are available, passing
1564 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1565 code which hits this problem, at the cost of a bit of extra runtime
1566 stack usage in some cases.
1568 The problem is described in more detail at:
1569 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1571 Only Thumb-2 kernels are affected.
1573 Unless you are sure your tools don't have this problem, say Y.
1575 config ARM_ASM_UNIFIED
1578 config ARM_PATCH_IDIV
1579 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1580 depends on CPU_32v7 && !XIP_KERNEL
1583 The ARM compiler inserts calls to __aeabi_idiv() and
1584 __aeabi_uidiv() when it needs to perform division on signed
1585 and unsigned integers. Some v7 CPUs have support for the sdiv
1586 and udiv instructions that can be used to implement those
1589 Enabling this option allows the kernel to modify itself to
1590 replace the first two instructions of these library functions
1591 with the sdiv or udiv plus "bx lr" instructions when the CPU
1592 it is running on supports them. Typically this will be faster
1593 and less power intensive than running the original library
1594 code to do integer division.
1597 bool "Use the ARM EABI to compile the kernel"
1599 This option allows for the kernel to be compiled using the latest
1600 ARM ABI (aka EABI). This is only useful if you are using a user
1601 space environment that is also compiled with EABI.
1603 Since there are major incompatibilities between the legacy ABI and
1604 EABI, especially with regard to structure member alignment, this
1605 option also changes the kernel syscall calling convention to
1606 disambiguate both ABIs and allow for backward compatibility support
1607 (selected with CONFIG_OABI_COMPAT).
1609 To use this you need GCC version 4.0.0 or later.
1612 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1613 depends on AEABI && !THUMB2_KERNEL
1615 This option preserves the old syscall interface along with the
1616 new (ARM EABI) one. It also provides a compatibility layer to
1617 intercept syscalls that have structure arguments which layout
1618 in memory differs between the legacy ABI and the new ARM EABI
1619 (only for non "thumb" binaries). This option adds a tiny
1620 overhead to all syscalls and produces a slightly larger kernel.
1622 The seccomp filter system will not be available when this is
1623 selected, since there is no way yet to sensibly distinguish
1624 between calling conventions during filtering.
1626 If you know you'll be using only pure EABI user space then you
1627 can say N here. If this option is not selected and you attempt
1628 to execute a legacy ABI binary then the result will be
1629 UNPREDICTABLE (in fact it can be predicted that it won't work
1630 at all). If in doubt say N.
1632 config ARCH_HAS_HOLES_MEMORYMODEL
1635 config ARCH_SPARSEMEM_ENABLE
1638 config ARCH_SPARSEMEM_DEFAULT
1639 def_bool ARCH_SPARSEMEM_ENABLE
1641 config ARCH_SELECT_MEMORY_MODEL
1642 def_bool ARCH_SPARSEMEM_ENABLE
1644 config HAVE_ARCH_PFN_VALID
1645 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1647 config HAVE_GENERIC_GUP
1652 bool "High Memory Support"
1655 The address space of ARM processors is only 4 Gigabytes large
1656 and it has to accommodate user address space, kernel address
1657 space as well as some memory mapped IO. That means that, if you
1658 have a large amount of physical memory and/or IO, not all of the
1659 memory can be "permanently mapped" by the kernel. The physical
1660 memory that is not permanently mapped is called "high memory".
1662 Depending on the selected kernel/user memory split, minimum
1663 vmalloc space and actual amount of RAM, you may not need this
1664 option which should result in a slightly faster kernel.
1669 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1673 The VM uses one page of physical memory for each page table.
1674 For systems with a lot of processes, this can use a lot of
1675 precious low memory, eventually leading to low memory being
1676 consumed by page tables. Setting this option will allow
1677 user-space 2nd level page tables to reside in high memory.
1679 config CPU_SW_DOMAIN_PAN
1680 bool "Enable use of CPU domains to implement privileged no-access"
1681 depends on MMU && !ARM_LPAE
1684 Increase kernel security by ensuring that normal kernel accesses
1685 are unable to access userspace addresses. This can help prevent
1686 use-after-free bugs becoming an exploitable privilege escalation
1687 by ensuring that magic values (such as LIST_POISON) will always
1688 fault when dereferenced.
1690 CPUs with low-vector mappings use a best-efforts implementation.
1691 Their lower 1MB needs to remain accessible for the vectors, but
1692 the remainder of userspace will become appropriately inaccessible.
1694 config HW_PERF_EVENTS
1698 config SYS_SUPPORTS_HUGETLBFS
1702 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1706 config ARCH_WANT_GENERAL_HUGETLB
1709 config ARM_MODULE_PLTS
1710 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1713 Allocate PLTs when loading modules so that jumps and calls whose
1714 targets are too far away for their relative offsets to be encoded
1715 in the instructions themselves can be bounced via veneers in the
1716 module's PLT. This allows modules to be allocated in the generic
1717 vmalloc area after the dedicated module memory area has been
1718 exhausted. The modules will use slightly more memory, but after
1719 rounding up to page size, the actual memory footprint is usually
1722 Say y if you are getting out of memory errors while loading modules
1726 config FORCE_MAX_ZONEORDER
1727 int "Maximum zone order"
1728 default "12" if SOC_AM33XX
1729 default "9" if SA1111 || ARCH_EFM32
1732 The kernel memory allocator divides physically contiguous memory
1733 blocks into "zones", where each zone is a power of two number of
1734 pages. This option selects the largest power of two that the kernel
1735 keeps in the memory allocator. If you need to allocate very large
1736 blocks of physically contiguous memory, then you may need to
1737 increase this value.
1739 This config option is actually maximum order plus one. For example,
1740 a value of 11 means that the largest free memory block is 2^10 pages.
1742 config ALIGNMENT_TRAP
1744 depends on CPU_CP15_MMU
1745 default y if !ARCH_EBSA110
1746 select HAVE_PROC_CPU if PROC_FS
1748 ARM processors cannot fetch/store information which is not
1749 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1750 address divisible by 4. On 32-bit ARM processors, these non-aligned
1751 fetch/store instructions will be emulated in software if you say
1752 here, which has a severe performance impact. This is necessary for
1753 correct operation of some network protocols. With an IP-only
1754 configuration it is safe to say N, otherwise say Y.
1756 config UACCESS_WITH_MEMCPY
1757 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1759 default y if CPU_FEROCEON
1761 Implement faster copy_to_user and clear_user methods for CPU
1762 cores where a 8-word STM instruction give significantly higher
1763 memory write throughput than a sequence of individual 32bit stores.
1765 A possible side effect is a slight increase in scheduling latency
1766 between threads sharing the same address space if they invoke
1767 such copy operations with large buffers.
1769 However, if the CPU data cache is using a write-allocate mode,
1770 this option is unlikely to provide any performance gain.
1774 prompt "Enable seccomp to safely compute untrusted bytecode"
1776 This kernel feature is useful for number crunching applications
1777 that may need to compute untrusted bytecode during their
1778 execution. By using pipes or other transports made available to
1779 the process as file descriptors supporting the read/write
1780 syscalls, it's possible to isolate those applications in
1781 their own address space using seccomp. Once seccomp is
1782 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1783 and the task is only allowed to execute a few safe syscalls
1784 defined by each seccomp mode.
1793 bool "Enable paravirtualization code"
1795 This changes the kernel so it can modify itself when it is run
1796 under a hypervisor, potentially improving performance significantly
1797 over full virtualization.
1799 config PARAVIRT_TIME_ACCOUNTING
1800 bool "Paravirtual steal time accounting"
1804 Select this option to enable fine granularity task steal time
1805 accounting. Time spent executing other tasks in parallel with
1806 the current vCPU is discounted from the vCPU power. To account for
1807 that, there can be a small performance impact.
1809 If in doubt, say N here.
1816 bool "Xen guest support on ARM"
1817 depends on ARM && AEABI && OF
1818 depends on CPU_V7 && !CPU_V6
1819 depends on !GENERIC_ATOMIC64
1821 select ARCH_DMA_ADDR_T_64BIT
1826 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1833 bool "Flattened Device Tree support"
1837 Include support for flattened device tree machine descriptions.
1840 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1843 This is the traditional way of passing data to the kernel at boot
1844 time. If you are solely relying on the flattened device tree (or
1845 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1846 to remove ATAGS support from your kernel binary. If unsure,
1849 config DEPRECATED_PARAM_STRUCT
1850 bool "Provide old way to pass kernel parameters"
1853 This was deprecated in 2001 and announced to live on for 5 years.
1854 Some old boot loaders still use this way.
1856 # Compressed boot loader in ROM. Yes, we really want to ask about
1857 # TEXT and BSS so we preserve their values in the config files.
1858 config ZBOOT_ROM_TEXT
1859 hex "Compressed ROM boot loader base address"
1862 The physical address at which the ROM-able zImage is to be
1863 placed in the target. Platforms which normally make use of
1864 ROM-able zImage formats normally set this to a suitable
1865 value in their defconfig file.
1867 If ZBOOT_ROM is not enabled, this has no effect.
1869 config ZBOOT_ROM_BSS
1870 hex "Compressed ROM boot loader BSS address"
1873 The base address of an area of read/write memory in the target
1874 for the ROM-able zImage which must be available while the
1875 decompressor is running. It must be large enough to hold the
1876 entire decompressed kernel plus an additional 128 KiB.
1877 Platforms which normally make use of ROM-able zImage formats
1878 normally set this to a suitable value in their defconfig file.
1880 If ZBOOT_ROM is not enabled, this has no effect.
1883 bool "Compressed boot loader in ROM/flash"
1884 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1885 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1887 Say Y here if you intend to execute your compressed kernel image
1888 (zImage) directly from ROM or flash. If unsure, say N.
1890 config ARM_APPENDED_DTB
1891 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1894 With this option, the boot code will look for a device tree binary
1895 (DTB) appended to zImage
1896 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1898 This is meant as a backward compatibility convenience for those
1899 systems with a bootloader that can't be upgraded to accommodate
1900 the documented boot protocol using a device tree.
1902 Beware that there is very little in terms of protection against
1903 this option being confused by leftover garbage in memory that might
1904 look like a DTB header after a reboot if no actual DTB is appended
1905 to zImage. Do not leave this option active in a production kernel
1906 if you don't intend to always append a DTB. Proper passing of the
1907 location into r2 of a bootloader provided DTB is always preferable
1910 config ARM_ATAG_DTB_COMPAT
1911 bool "Supplement the appended DTB with traditional ATAG information"
1912 depends on ARM_APPENDED_DTB
1914 Some old bootloaders can't be updated to a DTB capable one, yet
1915 they provide ATAGs with memory configuration, the ramdisk address,
1916 the kernel cmdline string, etc. Such information is dynamically
1917 provided by the bootloader and can't always be stored in a static
1918 DTB. To allow a device tree enabled kernel to be used with such
1919 bootloaders, this option allows zImage to extract the information
1920 from the ATAG list and store it at run time into the appended DTB.
1923 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1924 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1926 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1927 bool "Use bootloader kernel arguments if available"
1929 Uses the command-line options passed by the boot loader instead of
1930 the device tree bootargs property. If the boot loader doesn't provide
1931 any, the device tree bootargs property will be used.
1933 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1934 bool "Extend with bootloader kernel arguments"
1936 The command-line arguments provided by the boot loader will be
1937 appended to the the device tree bootargs property.
1942 string "Default kernel command string"
1945 On some architectures (EBSA110 and CATS), there is currently no way
1946 for the boot loader to pass arguments to the kernel. For these
1947 architectures, you should supply some command-line options at build
1948 time by entering them here. As a minimum, you should specify the
1949 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1952 prompt "Kernel command line type" if CMDLINE != ""
1953 default CMDLINE_FROM_BOOTLOADER
1956 config CMDLINE_FROM_BOOTLOADER
1957 bool "Use bootloader kernel arguments if available"
1959 Uses the command-line options passed by the boot loader. If
1960 the boot loader doesn't provide any, the default kernel command
1961 string provided in CMDLINE will be used.
1963 config CMDLINE_EXTEND
1964 bool "Extend bootloader kernel arguments"
1966 The command-line arguments provided by the boot loader will be
1967 appended to the default kernel command string.
1969 config CMDLINE_FORCE
1970 bool "Always use the default kernel command string"
1972 Always use the default kernel command string, even if the boot
1973 loader passes other arguments to the kernel.
1974 This is useful if you cannot or don't want to change the
1975 command-line options your boot loader passes to the kernel.
1979 bool "Kernel Execute-In-Place from ROM"
1980 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1982 Execute-In-Place allows the kernel to run from non-volatile storage
1983 directly addressable by the CPU, such as NOR flash. This saves RAM
1984 space since the text section of the kernel is not loaded from flash
1985 to RAM. Read-write sections, such as the data section and stack,
1986 are still copied to RAM. The XIP kernel is not compressed since
1987 it has to run directly from flash, so it will take more space to
1988 store it. The flash address used to link the kernel object files,
1989 and for storing it, is configuration dependent. Therefore, if you
1990 say Y here, you must know the proper physical address where to
1991 store the kernel image depending on your own flash memory usage.
1993 Also note that the make target becomes "make xipImage" rather than
1994 "make zImage" or "make Image". The final kernel binary to put in
1995 ROM memory will be arch/arm/boot/xipImage.
1999 config XIP_PHYS_ADDR
2000 hex "XIP Kernel Physical Location"
2001 depends on XIP_KERNEL
2002 default "0x00080000"
2004 This is the physical address in your flash memory the kernel will
2005 be linked for and stored to. This address is dependent on your
2009 bool "Kexec system call (EXPERIMENTAL)"
2010 depends on (!SMP || PM_SLEEP_SMP)
2014 kexec is a system call that implements the ability to shutdown your
2015 current kernel, and to start another kernel. It is like a reboot
2016 but it is independent of the system firmware. And like a reboot
2017 you can start any kernel with it, not just Linux.
2019 It is an ongoing process to be certain the hardware in a machine
2020 is properly shutdown, so do not be surprised if this code does not
2021 initially work for you.
2024 bool "Export atags in procfs"
2025 depends on ATAGS && KEXEC
2028 Should the atags used to boot the kernel be exported in an "atags"
2029 file in procfs. Useful with kexec.
2032 bool "Build kdump crash kernel (EXPERIMENTAL)"
2034 Generate crash dump after being started by kexec. This should
2035 be normally only set in special crash dump kernels which are
2036 loaded in the main kernel with kexec-tools into a specially
2037 reserved region and then later executed after a crash by
2038 kdump/kexec. The crash dump kernel must be compiled to a
2039 memory address not used by the main kernel
2041 For more details see Documentation/kdump/kdump.txt
2043 config AUTO_ZRELADDR
2044 bool "Auto calculation of the decompressed kernel image address"
2046 ZRELADDR is the physical address where the decompressed kernel
2047 image will be placed. If AUTO_ZRELADDR is selected, the address
2048 will be determined at run-time by masking the current IP with
2049 0xf8000000. This assumes the zImage being placed in the first 128MB
2050 from start of memory.
2056 bool "UEFI runtime support"
2057 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2059 select EFI_PARAMS_FROM_FDT
2062 select EFI_RUNTIME_WRAPPERS
2064 This option provides support for runtime services provided
2065 by UEFI firmware (such as non-volatile variables, realtime
2066 clock, and platform reset). A UEFI stub is also provided to
2067 allow the kernel to be booted as an EFI application. This
2068 is only useful for kernels that may run on systems that have
2072 bool "Enable support for SMBIOS (DMI) tables"
2076 This enables SMBIOS/DMI feature for systems.
2078 This option is only useful on systems that have UEFI firmware.
2079 However, even with this option, the resultant kernel should
2080 continue to boot on existing non-UEFI platforms.
2082 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2083 i.e., the the practice of identifying the platform via DMI to
2084 decide whether certain workarounds for buggy hardware and/or
2085 firmware need to be enabled. This would require the DMI subsystem
2086 to be enabled much earlier than we do on ARM, which is non-trivial.
2090 menu "CPU Power Management"
2092 source "drivers/cpufreq/Kconfig"
2094 source "drivers/cpuidle/Kconfig"
2098 menu "Floating point emulation"
2100 comment "At least one emulation must be selected"
2103 bool "NWFPE math emulation"
2104 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2106 Say Y to include the NWFPE floating point emulator in the kernel.
2107 This is necessary to run most binaries. Linux does not currently
2108 support floating point hardware so you need to say Y here even if
2109 your machine has an FPA or floating point co-processor podule.
2111 You may say N here if you are going to load the Acorn FPEmulator
2112 early in the bootup.
2115 bool "Support extended precision"
2116 depends on FPE_NWFPE
2118 Say Y to include 80-bit support in the kernel floating-point
2119 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2120 Note that gcc does not generate 80-bit operations by default,
2121 so in most cases this option only enlarges the size of the
2122 floating point emulator without any good reason.
2124 You almost surely want to say N here.
2127 bool "FastFPE math emulation (EXPERIMENTAL)"
2128 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2130 Say Y here to include the FAST floating point emulator in the kernel.
2131 This is an experimental much faster emulator which now also has full
2132 precision for the mantissa. It does not support any exceptions.
2133 It is very simple, and approximately 3-6 times faster than NWFPE.
2135 It should be sufficient for most programs. It may be not suitable
2136 for scientific calculations, but you have to check this for yourself.
2137 If you do not feel you need a faster FP emulation you should better
2141 bool "VFP-format floating point maths"
2142 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2144 Say Y to include VFP support code in the kernel. This is needed
2145 if your hardware includes a VFP unit.
2147 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2148 release notes and additional status information.
2150 Say N if your target does not have VFP hardware.
2158 bool "Advanced SIMD (NEON) Extension support"
2159 depends on VFPv3 && CPU_V7
2161 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2164 config KERNEL_MODE_NEON
2165 bool "Support for NEON in kernel mode"
2166 depends on NEON && AEABI
2168 Say Y to include support for NEON in kernel mode.
2172 menu "Userspace binary formats"
2174 source "fs/Kconfig.binfmt"
2178 menu "Power management options"
2180 source "kernel/power/Kconfig"
2182 config ARCH_SUSPEND_POSSIBLE
2183 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2184 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2187 config ARM_CPU_SUSPEND
2188 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2189 depends on ARCH_SUSPEND_POSSIBLE
2191 config ARCH_HIBERNATION_POSSIBLE
2194 default y if ARCH_SUSPEND_POSSIBLE
2198 source "net/Kconfig"
2200 source "drivers/Kconfig"
2202 source "drivers/firmware/Kconfig"
2206 source "arch/arm/Kconfig.debug"
2208 source "security/Kconfig"
2210 source "crypto/Kconfig"
2212 source "arch/arm/crypto/Kconfig"
2215 source "lib/Kconfig"
2217 source "arch/arm/kvm/Kconfig"