1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
6 compatible = "aspeed,ast2400";
9 interrupt-parent = <&vic>;
39 compatible = "arm,arm926ej-s";
46 device_type = "memory";
51 compatible = "simple-bus";
56 fmc: flash-controller@1e620000 {
57 reg = < 0x1e620000 0x94
58 0x20000000 0x10000000 >;
61 compatible = "aspeed,ast2400-fmc";
62 clocks = <&syscon ASPEED_CLK_AHB>;
67 compatible = "jedec,spi-nor";
72 spi: flash-controller@1e630000 {
73 reg = < 0x1e630000 0x18
74 0x30000000 0x10000000 >;
77 compatible = "aspeed,ast2400-spi";
78 clocks = <&syscon ASPEED_CLK_AHB>;
82 compatible = "jedec,spi-nor";
87 vic: interrupt-controller@1e6c0080 {
88 compatible = "aspeed,ast2400-vic";
90 #interrupt-cells = <1>;
91 valid-sources = <0xffffffff 0x0007ffff>;
92 reg = <0x1e6c0080 0x80>;
95 cvic: copro-interrupt-controller@1e6c2000 {
96 compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
97 valid-sources = <0x7fffffff>;
98 reg = <0x1e6c2000 0x80>;
101 mac0: ethernet@1e660000 {
102 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
103 reg = <0x1e660000 0x180>;
105 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
109 mac1: ethernet@1e680000 {
110 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
111 reg = <0x1e680000 0x180>;
113 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
117 ehci0: usb@1e6a1000 {
118 compatible = "aspeed,ast2400-ehci", "generic-ehci";
119 reg = <0x1e6a1000 0x100>;
121 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_usb2h_default>;
128 compatible = "aspeed,ast2400-uhci", "generic-uhci";
129 reg = <0x1e6b0000 0x100>;
132 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
135 * No default pinmux, it will follow EHCI, use an explicit pinmux
136 * override if you don't enable EHCI
140 vhub: usb-vhub@1e6a0000 {
141 compatible = "aspeed,ast2400-usb-vhub";
142 reg = <0x1e6a0000 0x300>;
144 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_usb2d_default>;
151 compatible = "simple-bus";
152 #address-cells = <1>;
156 syscon: syscon@1e6e2000 {
157 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
158 reg = <0x1e6e2000 0x1a8>;
159 #address-cells = <1>;
165 compatible = "aspeed,g4-pinctrl";
170 rng: hwrng@1e6e2078 {
171 compatible = "timeriomem_rng";
172 reg = <0x1e6e2078 0x4>;
178 compatible = "aspeed,ast2400-adc";
179 reg = <0x1e6e9000 0xb0>;
180 clocks = <&syscon ASPEED_CLK_APB>;
181 resets = <&syscon ASPEED_RESET_ADC>;
182 #io-channel-cells = <1>;
186 sram: sram@1e720000 {
187 compatible = "mmio-sram";
188 reg = <0x1e720000 0x8000>; // 32K
191 gpio: gpio@1e780000 {
194 compatible = "aspeed,ast2400-gpio";
195 reg = <0x1e780000 0x1000>;
197 gpio-ranges = <&pinctrl 0 0 220>;
198 clocks = <&syscon ASPEED_CLK_APB>;
199 interrupt-controller;
200 #interrupt-cells = <2>;
203 timer: timer@1e782000 {
204 /* This timer is a Faraday FTTMR010 derivative */
205 compatible = "aspeed,ast2400-timer";
206 reg = <0x1e782000 0x90>;
207 interrupts = <16 17 18 35 36 37 38 39>;
208 clocks = <&syscon ASPEED_CLK_APB>;
209 clock-names = "PCLK";
213 compatible = "aspeed,ast2400-rtc";
214 reg = <0x1e781000 0x18>;
218 uart1: serial@1e783000 {
219 compatible = "ns16550a";
220 reg = <0x1e783000 0x20>;
223 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
224 resets = <&lpc_reset 4>;
229 uart5: serial@1e784000 {
230 compatible = "ns16550a";
231 reg = <0x1e784000 0x20>;
234 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
239 wdt1: watchdog@1e785000 {
240 compatible = "aspeed,ast2400-wdt";
241 reg = <0x1e785000 0x1c>;
242 clocks = <&syscon ASPEED_CLK_APB>;
245 wdt2: watchdog@1e785020 {
246 compatible = "aspeed,ast2400-wdt";
247 reg = <0x1e785020 0x1c>;
248 clocks = <&syscon ASPEED_CLK_APB>;
251 pwm_tacho: pwm-tacho-controller@1e786000 {
252 compatible = "aspeed,ast2400-pwm-tacho";
253 #address-cells = <1>;
255 reg = <0x1e786000 0x1000>;
256 clocks = <&syscon ASPEED_CLK_24M>;
257 resets = <&syscon ASPEED_RESET_PWM>;
261 vuart: serial@1e787000 {
262 compatible = "aspeed,ast2400-vuart";
263 reg = <0x1e787000 0x40>;
266 clocks = <&syscon ASPEED_CLK_APB>;
272 compatible = "aspeed,ast2400-lpc", "simple-mfd";
273 reg = <0x1e789000 0x1000>;
275 #address-cells = <1>;
277 ranges = <0x0 0x1e789000 0x1000>;
280 compatible = "aspeed,ast2400-lpc-bmc";
284 lpc_host: lpc-host@80 {
285 compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
289 #address-cells = <1>;
291 ranges = <0x0 0x80 0x1e0>;
293 lpc_ctrl: lpc-ctrl@0 {
294 compatible = "aspeed,ast2400-lpc-ctrl";
296 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
300 lpc_snoop: lpc-snoop@0 {
301 compatible = "aspeed,ast2400-lpc-snoop";
308 compatible = "aspeed,ast2400-lhc";
309 reg = <0x20 0x24 0x48 0x8>;
312 lpc_reset: reset-controller@18 {
313 compatible = "aspeed,ast2400-lpc-reset";
319 compatible = "aspeed,ast2400-ibt-bmc";
327 uart2: serial@1e78d000 {
328 compatible = "ns16550a";
329 reg = <0x1e78d000 0x20>;
332 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
333 resets = <&lpc_reset 5>;
338 uart3: serial@1e78e000 {
339 compatible = "ns16550a";
340 reg = <0x1e78e000 0x20>;
343 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
344 resets = <&lpc_reset 6>;
349 uart4: serial@1e78f000 {
350 compatible = "ns16550a";
351 reg = <0x1e78f000 0x20>;
354 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
355 resets = <&lpc_reset 7>;
361 compatible = "simple-bus";
362 #address-cells = <1>;
364 ranges = <0 0x1e78a000 0x1000>;
371 i2c_ic: interrupt-controller@0 {
372 #interrupt-cells = <1>;
373 compatible = "aspeed,ast2400-i2c-ic";
376 interrupt-controller;
380 #address-cells = <1>;
382 #interrupt-cells = <1>;
385 compatible = "aspeed,ast2400-i2c-bus";
386 clocks = <&syscon ASPEED_CLK_APB>;
387 resets = <&syscon ASPEED_RESET_I2C>;
388 bus-frequency = <100000>;
390 interrupt-parent = <&i2c_ic>;
392 /* Does not need pinctrl properties */
396 #address-cells = <1>;
398 #interrupt-cells = <1>;
401 compatible = "aspeed,ast2400-i2c-bus";
402 clocks = <&syscon ASPEED_CLK_APB>;
403 resets = <&syscon ASPEED_RESET_I2C>;
404 bus-frequency = <100000>;
406 interrupt-parent = <&i2c_ic>;
408 /* Does not need pinctrl properties */
412 #address-cells = <1>;
414 #interrupt-cells = <1>;
417 compatible = "aspeed,ast2400-i2c-bus";
418 clocks = <&syscon ASPEED_CLK_APB>;
419 resets = <&syscon ASPEED_RESET_I2C>;
420 bus-frequency = <100000>;
422 interrupt-parent = <&i2c_ic>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&pinctrl_i2c3_default>;
429 #address-cells = <1>;
431 #interrupt-cells = <1>;
434 compatible = "aspeed,ast2400-i2c-bus";
435 clocks = <&syscon ASPEED_CLK_APB>;
436 resets = <&syscon ASPEED_RESET_I2C>;
437 bus-frequency = <100000>;
439 interrupt-parent = <&i2c_ic>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_i2c4_default>;
446 #address-cells = <1>;
448 #interrupt-cells = <1>;
451 compatible = "aspeed,ast2400-i2c-bus";
452 clocks = <&syscon ASPEED_CLK_APB>;
453 resets = <&syscon ASPEED_RESET_I2C>;
454 bus-frequency = <100000>;
456 interrupt-parent = <&i2c_ic>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&pinctrl_i2c5_default>;
463 #address-cells = <1>;
465 #interrupt-cells = <1>;
468 compatible = "aspeed,ast2400-i2c-bus";
469 clocks = <&syscon ASPEED_CLK_APB>;
470 resets = <&syscon ASPEED_RESET_I2C>;
471 bus-frequency = <100000>;
473 interrupt-parent = <&i2c_ic>;
474 pinctrl-names = "default";
475 pinctrl-0 = <&pinctrl_i2c6_default>;
480 #address-cells = <1>;
482 #interrupt-cells = <1>;
485 compatible = "aspeed,ast2400-i2c-bus";
486 clocks = <&syscon ASPEED_CLK_APB>;
487 resets = <&syscon ASPEED_RESET_I2C>;
488 bus-frequency = <100000>;
490 interrupt-parent = <&i2c_ic>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&pinctrl_i2c7_default>;
497 #address-cells = <1>;
499 #interrupt-cells = <1>;
502 compatible = "aspeed,ast2400-i2c-bus";
503 clocks = <&syscon ASPEED_CLK_APB>;
504 resets = <&syscon ASPEED_RESET_I2C>;
505 bus-frequency = <100000>;
507 interrupt-parent = <&i2c_ic>;
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_i2c8_default>;
514 #address-cells = <1>;
516 #interrupt-cells = <1>;
519 compatible = "aspeed,ast2400-i2c-bus";
520 clocks = <&syscon ASPEED_CLK_APB>;
521 resets = <&syscon ASPEED_RESET_I2C>;
522 bus-frequency = <100000>;
524 interrupt-parent = <&i2c_ic>;
525 pinctrl-names = "default";
526 pinctrl-0 = <&pinctrl_i2c9_default>;
531 #address-cells = <1>;
533 #interrupt-cells = <1>;
536 compatible = "aspeed,ast2400-i2c-bus";
537 clocks = <&syscon ASPEED_CLK_APB>;
538 resets = <&syscon ASPEED_RESET_I2C>;
539 bus-frequency = <100000>;
541 interrupt-parent = <&i2c_ic>;
542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_i2c10_default>;
548 #address-cells = <1>;
550 #interrupt-cells = <1>;
553 compatible = "aspeed,ast2400-i2c-bus";
554 clocks = <&syscon ASPEED_CLK_APB>;
555 resets = <&syscon ASPEED_RESET_I2C>;
556 bus-frequency = <100000>;
558 interrupt-parent = <&i2c_ic>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&pinctrl_i2c11_default>;
565 #address-cells = <1>;
567 #interrupt-cells = <1>;
570 compatible = "aspeed,ast2400-i2c-bus";
571 clocks = <&syscon ASPEED_CLK_APB>;
572 resets = <&syscon ASPEED_RESET_I2C>;
573 bus-frequency = <100000>;
575 interrupt-parent = <&i2c_ic>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&pinctrl_i2c12_default>;
582 #address-cells = <1>;
584 #interrupt-cells = <1>;
587 compatible = "aspeed,ast2400-i2c-bus";
588 clocks = <&syscon ASPEED_CLK_APB>;
589 resets = <&syscon ASPEED_RESET_I2C>;
590 bus-frequency = <100000>;
592 interrupt-parent = <&i2c_ic>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&pinctrl_i2c13_default>;
599 #address-cells = <1>;
601 #interrupt-cells = <1>;
604 compatible = "aspeed,ast2400-i2c-bus";
605 clocks = <&syscon ASPEED_CLK_APB>;
606 resets = <&syscon ASPEED_RESET_I2C>;
607 bus-frequency = <100000>;
609 interrupt-parent = <&i2c_ic>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&pinctrl_i2c14_default>;
617 pinctrl_acpi_default: acpi_default {
622 pinctrl_adc0_default: adc0_default {
627 pinctrl_adc1_default: adc1_default {
632 pinctrl_adc10_default: adc10_default {
637 pinctrl_adc11_default: adc11_default {
642 pinctrl_adc12_default: adc12_default {
647 pinctrl_adc13_default: adc13_default {
652 pinctrl_adc14_default: adc14_default {
657 pinctrl_adc15_default: adc15_default {
662 pinctrl_adc2_default: adc2_default {
667 pinctrl_adc3_default: adc3_default {
672 pinctrl_adc4_default: adc4_default {
677 pinctrl_adc5_default: adc5_default {
682 pinctrl_adc6_default: adc6_default {
687 pinctrl_adc7_default: adc7_default {
692 pinctrl_adc8_default: adc8_default {
697 pinctrl_adc9_default: adc9_default {
702 pinctrl_bmcint_default: bmcint_default {
707 pinctrl_ddcclk_default: ddcclk_default {
712 pinctrl_ddcdat_default: ddcdat_default {
717 pinctrl_extrst_default: extrst_default {
722 pinctrl_flack_default: flack_default {
727 pinctrl_flbusy_default: flbusy_default {
732 pinctrl_flwp_default: flwp_default {
737 pinctrl_gpid_default: gpid_default {
742 pinctrl_gpid0_default: gpid0_default {
747 pinctrl_gpid2_default: gpid2_default {
752 pinctrl_gpid4_default: gpid4_default {
757 pinctrl_gpid6_default: gpid6_default {
762 pinctrl_gpie0_default: gpie0_default {
767 pinctrl_gpie2_default: gpie2_default {
772 pinctrl_gpie4_default: gpie4_default {
777 pinctrl_gpie6_default: gpie6_default {
782 pinctrl_i2c10_default: i2c10_default {
787 pinctrl_i2c11_default: i2c11_default {
792 pinctrl_i2c12_default: i2c12_default {
797 pinctrl_i2c13_default: i2c13_default {
802 pinctrl_i2c14_default: i2c14_default {
807 pinctrl_i2c3_default: i2c3_default {
812 pinctrl_i2c4_default: i2c4_default {
817 pinctrl_i2c5_default: i2c5_default {
822 pinctrl_i2c6_default: i2c6_default {
827 pinctrl_i2c7_default: i2c7_default {
832 pinctrl_i2c8_default: i2c8_default {
837 pinctrl_i2c9_default: i2c9_default {
842 pinctrl_lpcpd_default: lpcpd_default {
847 pinctrl_lpcpme_default: lpcpme_default {
852 pinctrl_lpcrst_default: lpcrst_default {
857 pinctrl_lpcsmi_default: lpcsmi_default {
862 pinctrl_mac1link_default: mac1link_default {
863 function = "MAC1LINK";
867 pinctrl_mac2link_default: mac2link_default {
868 function = "MAC2LINK";
872 pinctrl_mdio1_default: mdio1_default {
877 pinctrl_mdio2_default: mdio2_default {
882 pinctrl_ncts1_default: ncts1_default {
887 pinctrl_ncts2_default: ncts2_default {
892 pinctrl_ncts3_default: ncts3_default {
897 pinctrl_ncts4_default: ncts4_default {
902 pinctrl_ndcd1_default: ndcd1_default {
907 pinctrl_ndcd2_default: ndcd2_default {
912 pinctrl_ndcd3_default: ndcd3_default {
917 pinctrl_ndcd4_default: ndcd4_default {
922 pinctrl_ndsr1_default: ndsr1_default {
927 pinctrl_ndsr2_default: ndsr2_default {
932 pinctrl_ndsr3_default: ndsr3_default {
937 pinctrl_ndsr4_default: ndsr4_default {
942 pinctrl_ndtr1_default: ndtr1_default {
947 pinctrl_ndtr2_default: ndtr2_default {
952 pinctrl_ndtr3_default: ndtr3_default {
957 pinctrl_ndtr4_default: ndtr4_default {
962 pinctrl_ndts4_default: ndts4_default {
967 pinctrl_nri1_default: nri1_default {
972 pinctrl_nri2_default: nri2_default {
977 pinctrl_nri3_default: nri3_default {
982 pinctrl_nri4_default: nri4_default {
987 pinctrl_nrts1_default: nrts1_default {
992 pinctrl_nrts2_default: nrts2_default {
997 pinctrl_nrts3_default: nrts3_default {
1002 pinctrl_oscclk_default: oscclk_default {
1003 function = "OSCCLK";
1007 pinctrl_pwm0_default: pwm0_default {
1012 pinctrl_pwm1_default: pwm1_default {
1017 pinctrl_pwm2_default: pwm2_default {
1022 pinctrl_pwm3_default: pwm3_default {
1027 pinctrl_pwm4_default: pwm4_default {
1032 pinctrl_pwm5_default: pwm5_default {
1037 pinctrl_pwm6_default: pwm6_default {
1042 pinctrl_pwm7_default: pwm7_default {
1047 pinctrl_rgmii1_default: rgmii1_default {
1048 function = "RGMII1";
1052 pinctrl_rgmii2_default: rgmii2_default {
1053 function = "RGMII2";
1057 pinctrl_rmii1_default: rmii1_default {
1062 pinctrl_rmii2_default: rmii2_default {
1067 pinctrl_rom16_default: rom16_default {
1072 pinctrl_rom8_default: rom8_default {
1077 pinctrl_romcs1_default: romcs1_default {
1078 function = "ROMCS1";
1082 pinctrl_romcs2_default: romcs2_default {
1083 function = "ROMCS2";
1087 pinctrl_romcs3_default: romcs3_default {
1088 function = "ROMCS3";
1092 pinctrl_romcs4_default: romcs4_default {
1093 function = "ROMCS4";
1097 pinctrl_rxd1_default: rxd1_default {
1102 pinctrl_rxd2_default: rxd2_default {
1107 pinctrl_rxd3_default: rxd3_default {
1112 pinctrl_rxd4_default: rxd4_default {
1117 pinctrl_salt1_default: salt1_default {
1122 pinctrl_salt2_default: salt2_default {
1127 pinctrl_salt3_default: salt3_default {
1132 pinctrl_salt4_default: salt4_default {
1137 pinctrl_sd1_default: sd1_default {
1142 pinctrl_sd2_default: sd2_default {
1147 pinctrl_sgpmck_default: sgpmck_default {
1148 function = "SGPMCK";
1152 pinctrl_sgpmi_default: sgpmi_default {
1157 pinctrl_sgpmld_default: sgpmld_default {
1158 function = "SGPMLD";
1162 pinctrl_sgpmo_default: sgpmo_default {
1167 pinctrl_sgpsck_default: sgpsck_default {
1168 function = "SGPSCK";
1172 pinctrl_sgpsi0_default: sgpsi0_default {
1173 function = "SGPSI0";
1177 pinctrl_sgpsi1_default: sgpsi1_default {
1178 function = "SGPSI1";
1182 pinctrl_sgpsld_default: sgpsld_default {
1183 function = "SGPSLD";
1187 pinctrl_sioonctrl_default: sioonctrl_default {
1188 function = "SIOONCTRL";
1189 groups = "SIOONCTRL";
1192 pinctrl_siopbi_default: siopbi_default {
1193 function = "SIOPBI";
1197 pinctrl_siopbo_default: siopbo_default {
1198 function = "SIOPBO";
1202 pinctrl_siopwreq_default: siopwreq_default {
1203 function = "SIOPWREQ";
1204 groups = "SIOPWREQ";
1207 pinctrl_siopwrgd_default: siopwrgd_default {
1208 function = "SIOPWRGD";
1209 groups = "SIOPWRGD";
1212 pinctrl_sios3_default: sios3_default {
1217 pinctrl_sios5_default: sios5_default {
1222 pinctrl_siosci_default: siosci_default {
1223 function = "SIOSCI";
1227 pinctrl_spi1_default: spi1_default {
1232 pinctrl_spi1debug_default: spi1debug_default {
1233 function = "SPI1DEBUG";
1234 groups = "SPI1DEBUG";
1237 pinctrl_spi1passthru_default: spi1passthru_default {
1238 function = "SPI1PASSTHRU";
1239 groups = "SPI1PASSTHRU";
1242 pinctrl_spics1_default: spics1_default {
1243 function = "SPICS1";
1247 pinctrl_timer3_default: timer3_default {
1248 function = "TIMER3";
1252 pinctrl_timer4_default: timer4_default {
1253 function = "TIMER4";
1257 pinctrl_timer5_default: timer5_default {
1258 function = "TIMER5";
1262 pinctrl_timer6_default: timer6_default {
1263 function = "TIMER6";
1267 pinctrl_timer7_default: timer7_default {
1268 function = "TIMER7";
1272 pinctrl_timer8_default: timer8_default {
1273 function = "TIMER8";
1277 pinctrl_txd1_default: txd1_default {
1282 pinctrl_txd2_default: txd2_default {
1287 pinctrl_txd3_default: txd3_default {
1292 pinctrl_txd4_default: txd4_default {
1297 pinctrl_uart6_default: uart6_default {
1302 pinctrl_usbcki_default: usbcki_default {
1303 function = "USBCKI";
1307 pinctrl_usb2h_default: usb2h_default {
1308 function = "USB2H1";
1312 pinctrl_usb2d_default: usb2d_default {
1313 function = "USB2D1";
1317 pinctrl_vgabios_rom_default: vgabios_rom_default {
1318 function = "VGABIOS_ROM";
1319 groups = "VGABIOS_ROM";
1322 pinctrl_vgahs_default: vgahs_default {
1327 pinctrl_vgavs_default: vgavs_default {
1332 pinctrl_vpi18_default: vpi18_default {
1337 pinctrl_vpi24_default: vpi24_default {
1342 pinctrl_vpi30_default: vpi30_default {
1347 pinctrl_vpo12_default: vpo12_default {
1352 pinctrl_vpo24_default: vpo24_default {
1357 pinctrl_wdtrst1_default: wdtrst1_default {
1358 function = "WDTRST1";
1362 pinctrl_wdtrst2_default: wdtrst2_default {
1363 function = "WDTRST2";