arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/bus/ti-sysc.h>
  11 #include <dt-bindings/clock/dra7.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/pinctrl/dra.h>
  14 #include <dt-bindings/clock/dra7.h>
  15
  16 #define MAX_SOURCES 400
  17
  18 / {
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         compatible = "ti,dra7xx";
  23         interrupt-parent = <&crossbar_mpu>;
  24         chosen { };
  25
  26         aliases {
  27                 i2c0 = &i2c1;
  28                 i2c1 = &i2c2;
  29                 i2c2 = &i2c3;
  30                 i2c3 = &i2c4;
  31                 i2c4 = &i2c5;
  32                 serial0 = &uart1;
  33                 serial1 = &uart2;
  34                 serial2 = &uart3;
  35                 serial3 = &uart4;
  36                 serial4 = &uart5;
  37                 serial5 = &uart6;
  38                 serial6 = &uart7;
  39                 serial7 = &uart8;
  40                 serial8 = &uart9;
  41                 serial9 = &uart10;
  42                 ethernet0 = &cpsw_emac0;
  43                 ethernet1 = &cpsw_emac1;
  44                 d_can0 = &dcan1;
  45                 d_can1 = &dcan2;
  46                 spi0 = &qspi;
  47         };
  48
  49         timer {
  50                 compatible = "arm,armv7-timer";
  51                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  52                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  53                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  54                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  55                 interrupt-parent = <&gic>;
  56         };
  57
  58         gic: interrupt-controller@48211000 {
  59                 compatible = "arm,cortex-a15-gic";
  60                 interrupt-controller;
  61                 #interrupt-cells = <3>;
  62                 reg = <0x0 0x48211000 0x0 0x1000>,
  63                       <0x0 0x48212000 0x0 0x2000>,
  64                       <0x0 0x48214000 0x0 0x2000>,
  65                       <0x0 0x48216000 0x0 0x2000>;
  66                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  67                 interrupt-parent = <&gic>;
  68         };
  69
  70         wakeupgen: interrupt-controller@48281000 {
  71                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  72                 interrupt-controller;
  73                 #interrupt-cells = <3>;
  74                 reg = <0x0 0x48281000 0x0 0x1000>;
  75                 interrupt-parent = <&gic>;
  76         };
  77
  78         cpus {
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 cpu0: cpu@0 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a15";
  85                         reg = <0>;
  86
  87                         operating-points-v2 = <&cpu0_opp_table>;
  88
  89                         clocks = <&dpll_mpu_ck>;
  90                         clock-names = "cpu";
  91
  92                         clock-latency = <300000>; /* From omap-cpufreq driver */
  93
  94                         /* cooling options */
  95                         #cooling-cells = <2>; /* min followed by max */
  96
  97                         vbb-supply = <&abb_mpu>;
  98                 };
  99         };
 100
 101         cpu0_opp_table: opp-table {
 102                 compatible = "operating-points-v2-ti-cpu";
 103                 syscon = <&scm_wkup>;
 104
 105                 opp_nom-1000000000 {
 106                         opp-hz = /bits/ 64 <1000000000>;
 107                         opp-microvolt = <1060000 850000 1150000>,
 108                                         <1060000 850000 1150000>;
 109                         opp-supported-hw = <0xFF 0x01>;
 110                         opp-suspend;
 111                 };
 112
 113                 opp_od-1176000000 {
 114                         opp-hz = /bits/ 64 <1176000000>;
 115                         opp-microvolt = <1160000 885000 1160000>,
 116                                         <1160000 885000 1160000>;
 117
 118                         opp-supported-hw = <0xFF 0x02>;
 119                 };
 120
 121                 opp_high@1500000000 {
 122                         opp-hz = /bits/ 64 <1500000000>;
 123                         opp-microvolt = <1210000 950000 1250000>,
 124                                         <1210000 950000 1250000>;
 125                         opp-supported-hw = <0xFF 0x04>;
 126                 };
 127         };
 128
 129         /*
 130          * The soc node represents the soc top level view. It is used for IPs
 131          * that are not memory mapped in the MPU view or for the MPU itself.
 132          */
 133         soc {
 134                 compatible = "ti,omap-infra";
 135                 mpu {
 136                         compatible = "ti,omap5-mpu";
 137                         ti,hwmods = "mpu";
 138                 };
 139         };
 140
 141         /*
 142          * XXX: Use a flat representation of the SOC interconnect.
 143          * The real OMAP interconnect network is quite complex.
 144          * Since it will not bring real advantage to represent that in DT for
 145          * the moment, just use a fake OCP bus entry to represent the whole bus
 146          * hierarchy.
 147          */
 148         ocp {
 149                 compatible = "ti,dra7-l3-noc", "simple-bus";
 150                 #address-cells = <1>;
 151                 #size-cells = <1>;
 152                 ranges = <0x0 0x0 0x0 0xc0000000>;
 153                 ti,hwmods = "l3_main_1", "l3_main_2";
 154                 reg = <0x0 0x44000000 0x0 0x1000000>,
 155                       <0x0 0x45000000 0x0 0x1000>;
 156                 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 157                                       <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 158
 159                 l4_cfg: l4@4a000000 {
 160                         compatible = "ti,dra7-l4-cfg", "simple-bus";
 161                         #address-cells = <1>;
 162                         #size-cells = <1>;
 163                         ranges = <0 0x4a000000 0x22c000>;
 164
 165                         scm: scm@2000 {
 166                                 compatible = "ti,dra7-scm-core", "simple-bus";
 167                                 reg = <0x2000 0x2000>;
 168                                 #address-cells = <1>;
 169                                 #size-cells = <1>;
 170                                 ranges = <0 0x2000 0x2000>;
 171
 172                                 scm_conf: scm_conf@0 {
 173                                         compatible = "syscon", "simple-bus";
 174                                         reg = <0x0 0x1400>;
 175                                         #address-cells = <1>;
 176                                         #size-cells = <1>;
 177                                         ranges = <0 0x0 0x1400>;
 178
 179                                         pbias_regulator: pbias_regulator@e00 {
 180                                                 compatible = "ti,pbias-dra7", "ti,pbias-omap";
 181                                                 reg = <0xe00 0x4>;
 182                                                 syscon = <&scm_conf>;
 183                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 184                                                         regulator-name = "pbias_mmc_omap5";
 185                                                         regulator-min-microvolt = <1800000>;
 186                                                         regulator-max-microvolt = <3300000>;
 187                                                 };
 188                                         };
 189
 190                                         scm_conf_clocks: clocks {
 191                                                 #address-cells = <1>;
 192                                                 #size-cells = <0>;
 193                                         };
 194                                 };
 195
 196                                 dra7_pmx_core: pinmux@1400 {
 197                                         compatible = "ti,dra7-padconf",
 198                                                      "pinctrl-single";
 199                                         reg = <0x1400 0x0468>;
 200                                         #address-cells = <1>;
 201                                         #size-cells = <0>;
 202                                         #pinctrl-cells = <1>;
 203                                         #interrupt-cells = <1>;
 204                                         interrupt-controller;
 205                                         pinctrl-single,register-width = <32>;
 206                                         pinctrl-single,function-mask = <0x3fffffff>;
 207                                 };
 208
 209                                 scm_conf1: scm_conf@1c04 {
 210                                         compatible = "syscon";
 211                                         reg = <0x1c04 0x0020>;
 212                                         #syscon-cells = <2>;
 213                                 };
 214
 215                                 scm_conf_pcie: scm_conf@1c24 {
 216                                         compatible = "syscon";
 217                                         reg = <0x1c24 0x0024>;
 218                                 };
 219
 220                                 sdma_xbar: dma-router@b78 {
 221                                         compatible = "ti,dra7-dma-crossbar";
 222                                         reg = <0xb78 0xfc>;
 223                                         #dma-cells = <1>;
 224                                         dma-requests = <205>;
 225                                         ti,dma-safe-map = <0>;
 226                                         dma-masters = <&sdma>;
 227                                 };
 228
 229                                 edma_xbar: dma-router@c78 {
 230                                         compatible = "ti,dra7-dma-crossbar";
 231                                         reg = <0xc78 0x7c>;
 232                                         #dma-cells = <2>;
 233                                         dma-requests = <204>;
 234                                         ti,dma-safe-map = <0>;
 235                                         dma-masters = <&edma>;
 236                                 };
 237                         };
 238
 239                         cm_core_aon: cm_core_aon@5000 {
 240                                 compatible = "ti,dra7-cm-core-aon",
 241                                               "simple-bus";
 242                                 #address-cells = <1>;
 243                                 #size-cells = <1>;
 244                                 reg = <0x5000 0x2000>;
 245                                 ranges = <0 0x5000 0x2000>;
 246
 247                                 cm_core_aon_clocks: clocks {
 248                                         #address-cells = <1>;
 249                                         #size-cells = <0>;
 250                                 };
 251
 252                                 cm_core_aon_clockdomains: clockdomains {
 253                                 };
 254                         };
 255
 256                         cm_core: cm_core@8000 {
 257                                 compatible = "ti,dra7-cm-core", "simple-bus";
 258                                 #address-cells = <1>;
 259                                 #size-cells = <1>;
 260                                 reg = <0x8000 0x3000>;
 261                                 ranges = <0 0x8000 0x3000>;
 262
 263                                 cm_core_clocks: clocks {
 264                                         #address-cells = <1>;
 265                                         #size-cells = <0>;
 266                                 };
 267
 268                                 cm_core_clockdomains: clockdomains {
 269                                 };
 270                         };
 271                 };
 272
 273                 l4_wkup: l4@4ae00000 {
 274                         compatible = "ti,dra7-l4-wkup", "simple-bus";
 275                         #address-cells = <1>;
 276                         #size-cells = <1>;
 277                         ranges = <0 0x4ae00000 0x3f000>;
 278
 279                         counter32k: counter@4000 {
 280                                 compatible = "ti,omap-counter32k";
 281                                 reg = <0x4000 0x40>;
 282                                 ti,hwmods = "counter_32k";
 283                         };
 284
 285                         prm: prm@6000 {
 286                                 compatible = "ti,dra7-prm", "simple-bus";
 287                                 reg = <0x6000 0x3000>;
 288                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 289                                 #address-cells = <1>;
 290                                 #size-cells = <1>;
 291                                 ranges = <0 0x6000 0x3000>;
 292
 293                                 prm_clocks: clocks {
 294                                         #address-cells = <1>;
 295                                         #size-cells = <0>;
 296                                 };
 297
 298                                 prm_clockdomains: clockdomains {
 299                                 };
 300                         };
 301
 302                         scm_wkup: scm_conf@c000 {
 303                                 compatible = "syscon";
 304                                 reg = <0xc000 0x1000>;
 305                         };
 306                 };
 307
 308                 axi@0 {
 309                         compatible = "simple-bus";
 310                         #size-cells = <1>;
 311                         #address-cells = <1>;
 312                         ranges = <0x51000000 0x51000000 0x3000
 313                                   0x0        0x20000000 0x10000000>;
 314                         /**
 315                          * To enable PCI endpoint mode, disable the pcie1_rc
 316                          * node and enable pcie1_ep mode.
 317                          */
 318                         pcie1_rc: pcie@51000000 {
 319                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 320                                 reg-names = "rc_dbics", "ti_conf", "config";
 321                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 322                                 #address-cells = <3>;
 323                                 #size-cells = <2>;
 324                                 device_type = "pci";
 325                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 326                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 327                                 bus-range = <0x00 0xff>;
 328                                 #interrupt-cells = <1>;
 329                                 num-lanes = <1>;
 330                                 linux,pci-domain = <0>;
 331                                 ti,hwmods = "pcie1";
 332                                 phys = <&pcie1_phy>;
 333                                 phy-names = "pcie-phy0";
 334                                 interrupt-map-mask = <0 0 0 7>;
 335                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 336                                                 <0 0 0 2 &pcie1_intc 2>,
 337                                                 <0 0 0 3 &pcie1_intc 3>,
 338                                                 <0 0 0 4 &pcie1_intc 4>;
 339                                 status = "disabled";
 340                                 pcie1_intc: interrupt-controller {
 341                                         interrupt-controller;
 342                                         #address-cells = <0>;
 343                                         #interrupt-cells = <1>;
 344                                 };
 345                         };
 346
 347                         pcie1_ep: pcie_ep@51000000 {
 348                                 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
 349                                 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
 350                                 interrupts = <0 232 0x4>;
 351                                 num-lanes = <1>;
 352                                 num-ib-windows = <4>;
 353                                 num-ob-windows = <16>;
 354                                 ti,hwmods = "pcie1";
 355                                 phys = <&pcie1_phy>;
 356                                 phy-names = "pcie-phy0";
 357                                 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
 358                                 status = "disabled";
 359                         };
 360                 };
 361
 362                 axi@1 {
 363                         compatible = "simple-bus";
 364                         #size-cells = <1>;
 365                         #address-cells = <1>;
 366                         ranges = <0x51800000 0x51800000 0x3000
 367                                   0x0        0x30000000 0x10000000>;
 368                         status = "disabled";
 369                         pcie2_rc: pcie@51800000 {
 370                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 371                                 reg-names = "rc_dbics", "ti_conf", "config";
 372                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 373                                 #address-cells = <3>;
 374                                 #size-cells = <2>;
 375                                 device_type = "pci";
 376                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 377                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 378                                 bus-range = <0x00 0xff>;
 379                                 #interrupt-cells = <1>;
 380                                 num-lanes = <1>;
 381                                 linux,pci-domain = <1>;
 382                                 ti,hwmods = "pcie2";
 383                                 phys = <&pcie2_phy>;
 384                                 phy-names = "pcie-phy0";
 385                                 interrupt-map-mask = <0 0 0 7>;
 386                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 387                                                 <0 0 0 2 &pcie2_intc 2>,
 388                                                 <0 0 0 3 &pcie2_intc 3>,
 389                                                 <0 0 0 4 &pcie2_intc 4>;
 390                                 pcie2_intc: interrupt-controller {
 391                                         interrupt-controller;
 392                                         #address-cells = <0>;
 393                                         #interrupt-cells = <1>;
 394                                 };
 395                         };
 396                 };
 397
 398                 ocmcram1: ocmcram@40300000 {
 399                         compatible = "mmio-sram";
 400                         reg = <0x40300000 0x80000>;
 401                         ranges = <0x0 0x40300000 0x80000>;
 402                         #address-cells = <1>;
 403                         #size-cells = <1>;
 404                         /*
 405                          * This is a placeholder for an optional reserved
 406                          * region for use by secure software. The size
 407                          * of this region is not known until runtime so it
 408                          * is set as zero to either be updated to reserve
 409                          * space or left unchanged to leave all SRAM for use.
 410                          * On HS parts that that require the reserved region
 411                          * either the bootloader can update the size to
 412                          * the required amount or the node can be overridden
 413                          * from the board dts file for the secure platform.
 414                          */
 415                         sram-hs@0 {
 416                                 compatible = "ti,secure-ram";
 417                                 reg = <0x0 0x0>;
 418                         };
 419                 };
 420
 421                 /*
 422                  * NOTE: ocmcram2 and ocmcram3 are not available on all
 423                  * DRA7xx and AM57xx variants. Confirm availability in
 424                  * the data manual for the exact part number in use
 425                  * before enabling these nodes in the board dts file.
 426                  */
 427                 ocmcram2: ocmcram@40400000 {
 428                         status = "disabled";
 429                         compatible = "mmio-sram";
 430                         reg = <0x40400000 0x100000>;
 431                         ranges = <0x0 0x40400000 0x100000>;
 432                         #address-cells = <1>;
 433                         #size-cells = <1>;
 434                 };
 435
 436                 ocmcram3: ocmcram@40500000 {
 437                         status = "disabled";
 438                         compatible = "mmio-sram";
 439                         reg = <0x40500000 0x100000>;
 440                         ranges = <0x0 0x40500000 0x100000>;
 441                         #address-cells = <1>;
 442                         #size-cells = <1>;
 443                 };
 444
 445                 bandgap: bandgap@4a0021e0 {
 446                         reg = <0x4a0021e0 0xc
 447                                 0x4a00232c 0xc
 448                                 0x4a002380 0x2c
 449                                 0x4a0023C0 0x3c
 450                                 0x4a002564 0x8
 451                                 0x4a002574 0x50>;
 452                                 compatible = "ti,dra752-bandgap";
 453                                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 454                                 #thermal-sensor-cells = <1>;
 455                 };
 456
 457                 dsp1_system: dsp_system@40d00000 {
 458                         compatible = "syscon";
 459                         reg = <0x40d00000 0x100>;
 460                 };
 461
 462                 dra7_iodelay_core: padconf@4844a000 {
 463                         compatible = "ti,dra7-iodelay";
 464                         reg = <0x4844a000 0x0d1c>;
 465                         #address-cells = <1>;
 466                         #size-cells = <0>;
 467                         #pinctrl-cells = <2>;
 468                 };
 469
 470                 sdma: dma-controller@4a056000 {
 471                         compatible = "ti,omap4430-sdma";
 472                         reg = <0x4a056000 0x1000>;
 473                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 474                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 475                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 476                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 477                         #dma-cells = <1>;
 478                         dma-channels = <32>;
 479                         dma-requests = <127>;
 480                         ti,hwmods = "dma_system";
 481                 };
 482
 483                 edma: edma@43300000 {
 484                         compatible = "ti,edma3-tpcc";
 485                         ti,hwmods = "tpcc";
 486                         reg = <0x43300000 0x100000>;
 487                         reg-names = "edma3_cc";
 488                         interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 489                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
 490                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
 491                         interrupt-names = "edma3_ccint", "edma3_mperr",
 492                                           "edma3_ccerrint";
 493                         dma-requests = <64>;
 494                         #dma-cells = <2>;
 495
 496                         ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
 497
 498                         /*
 499                          * memcpy is disabled, can be enabled with:
 500                          * ti,edma-memcpy-channels = <20 21>;
 501                          * for example. Note that these channels need to be
 502                          * masked in the xbar as well.
 503                          */
 504                 };
 505
 506                 edma_tptc0: tptc@43400000 {
 507                         compatible = "ti,edma3-tptc";
 508                         ti,hwmods = "tptc0";
 509                         reg =   <0x43400000 0x100000>;
 510                         interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
 511                         interrupt-names = "edma3_tcerrint";
 512                 };
 513
 514                 edma_tptc1: tptc@43500000 {
 515                         compatible = "ti,edma3-tptc";
 516                         ti,hwmods = "tptc1";
 517                         reg =   <0x43500000 0x100000>;
 518                         interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
 519                         interrupt-names = "edma3_tcerrint";
 520                 };
 521
 522                 gpio1: gpio@4ae10000 {
 523                         compatible = "ti,omap4-gpio";
 524                         reg = <0x4ae10000 0x200>;
 525                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 526                         ti,hwmods = "gpio1";
 527                         gpio-controller;
 528                         #gpio-cells = <2>;
 529                         interrupt-controller;
 530                         #interrupt-cells = <2>;
 531                 };
 532
 533                 gpio2: gpio@48055000 {
 534                         compatible = "ti,omap4-gpio";
 535                         reg = <0x48055000 0x200>;
 536                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 537                         ti,hwmods = "gpio2";
 538                         gpio-controller;
 539                         #gpio-cells = <2>;
 540                         interrupt-controller;
 541                         #interrupt-cells = <2>;
 542                 };
 543
 544                 gpio3: gpio@48057000 {
 545                         compatible = "ti,omap4-gpio";
 546                         reg = <0x48057000 0x200>;
 547                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 548                         ti,hwmods = "gpio3";
 549                         gpio-controller;
 550                         #gpio-cells = <2>;
 551                         interrupt-controller;
 552                         #interrupt-cells = <2>;
 553                 };
 554
 555                 gpio4: gpio@48059000 {
 556                         compatible = "ti,omap4-gpio";
 557                         reg = <0x48059000 0x200>;
 558                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 559                         ti,hwmods = "gpio4";
 560                         gpio-controller;
 561                         #gpio-cells = <2>;
 562                         interrupt-controller;
 563                         #interrupt-cells = <2>;
 564                 };
 565
 566                 gpio5: gpio@4805b000 {
 567                         compatible = "ti,omap4-gpio";
 568                         reg = <0x4805b000 0x200>;
 569                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 570                         ti,hwmods = "gpio5";
 571                         gpio-controller;
 572                         #gpio-cells = <2>;
 573                         interrupt-controller;
 574                         #interrupt-cells = <2>;
 575                 };
 576
 577                 gpio6: gpio@4805d000 {
 578                         compatible = "ti,omap4-gpio";
 579                         reg = <0x4805d000 0x200>;
 580                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 581                         ti,hwmods = "gpio6";
 582                         gpio-controller;
 583                         #gpio-cells = <2>;
 584                         interrupt-controller;
 585                         #interrupt-cells = <2>;
 586                 };
 587
 588                 gpio7: gpio@48051000 {
 589                         compatible = "ti,omap4-gpio";
 590                         reg = <0x48051000 0x200>;
 591                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 592                         ti,hwmods = "gpio7";
 593                         gpio-controller;
 594                         #gpio-cells = <2>;
 595                         interrupt-controller;
 596                         #interrupt-cells = <2>;
 597                 };
 598
 599                 gpio8: gpio@48053000 {
 600                         compatible = "ti,omap4-gpio";
 601                         reg = <0x48053000 0x200>;
 602                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 603                         ti,hwmods = "gpio8";
 604                         gpio-controller;
 605                         #gpio-cells = <2>;
 606                         interrupt-controller;
 607                         #interrupt-cells = <2>;
 608                 };
 609
 610                 uart1: serial@4806a000 {
 611                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 612                         reg = <0x4806a000 0x100>;
 613                         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 614                         ti,hwmods = "uart1";
 615                         clock-frequency = <48000000>;
 616                         status = "disabled";
 617                         dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
 618                         dma-names = "tx", "rx";
 619                 };
 620
 621                 uart2: serial@4806c000 {
 622                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 623                         reg = <0x4806c000 0x100>;
 624                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 625                         ti,hwmods = "uart2";
 626                         clock-frequency = <48000000>;
 627                         status = "disabled";
 628                         dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
 629                         dma-names = "tx", "rx";
 630                 };
 631
 632                 uart3: serial@48020000 {
 633                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 634                         reg = <0x48020000 0x100>;
 635                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 636                         ti,hwmods = "uart3";
 637                         clock-frequency = <48000000>;
 638                         status = "disabled";
 639                         dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
 640                         dma-names = "tx", "rx";
 641                 };
 642
 643                 uart4: serial@4806e000 {
 644                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 645                         reg = <0x4806e000 0x100>;
 646                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 647                         ti,hwmods = "uart4";
 648                         clock-frequency = <48000000>;
 649                         status = "disabled";
 650                         dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
 651                         dma-names = "tx", "rx";
 652                 };
 653
 654                 uart5: serial@48066000 {
 655                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 656                         reg = <0x48066000 0x100>;
 657                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 658                         ti,hwmods = "uart5";
 659                         clock-frequency = <48000000>;
 660                         status = "disabled";
 661                         dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
 662                         dma-names = "tx", "rx";
 663                 };
 664
 665                 uart6: serial@48068000 {
 666                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 667                         reg = <0x48068000 0x100>;
 668                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 669                         ti,hwmods = "uart6";
 670                         clock-frequency = <48000000>;
 671                         status = "disabled";
 672                         dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
 673                         dma-names = "tx", "rx";
 674                 };
 675
 676                 uart7: serial@48420000 {
 677                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 678                         reg = <0x48420000 0x100>;
 679                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 680                         ti,hwmods = "uart7";
 681                         clock-frequency = <48000000>;
 682                         status = "disabled";
 683                 };
 684
 685                 uart8: serial@48422000 {
 686                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 687                         reg = <0x48422000 0x100>;
 688                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 689                         ti,hwmods = "uart8";
 690                         clock-frequency = <48000000>;
 691                         status = "disabled";
 692                 };
 693
 694                 uart9: serial@48424000 {
 695                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 696                         reg = <0x48424000 0x100>;
 697                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 698                         ti,hwmods = "uart9";
 699                         clock-frequency = <48000000>;
 700                         status = "disabled";
 701                 };
 702
 703                 uart10: serial@4ae2b000 {
 704                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 705                         reg = <0x4ae2b000 0x100>;
 706                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 707                         ti,hwmods = "uart10";
 708                         clock-frequency = <48000000>;
 709                         status = "disabled";
 710                 };
 711
 712                 mailbox1: mailbox@4a0f4000 {
 713                         compatible = "ti,omap4-mailbox";
 714                         reg = <0x4a0f4000 0x200>;
 715                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 716                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 717                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 718                         ti,hwmods = "mailbox1";
 719                         #mbox-cells = <1>;
 720                         ti,mbox-num-users = <3>;
 721                         ti,mbox-num-fifos = <8>;
 722                         status = "disabled";
 723                 };
 724
 725                 mailbox2: mailbox@4883a000 {
 726                         compatible = "ti,omap4-mailbox";
 727                         reg = <0x4883a000 0x200>;
 728                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 729                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 730                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 731                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 732                         ti,hwmods = "mailbox2";
 733                         #mbox-cells = <1>;
 734                         ti,mbox-num-users = <4>;
 735                         ti,mbox-num-fifos = <12>;
 736                         status = "disabled";
 737                 };
 738
 739                 mailbox3: mailbox@4883c000 {
 740                         compatible = "ti,omap4-mailbox";
 741                         reg = <0x4883c000 0x200>;
 742                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 743                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 744                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 745                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 746                         ti,hwmods = "mailbox3";
 747                         #mbox-cells = <1>;
 748                         ti,mbox-num-users = <4>;
 749                         ti,mbox-num-fifos = <12>;
 750                         status = "disabled";
 751                 };
 752
 753                 mailbox4: mailbox@4883e000 {
 754                         compatible = "ti,omap4-mailbox";
 755                         reg = <0x4883e000 0x200>;
 756                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 757                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 758                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 759                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 760                         ti,hwmods = "mailbox4";
 761                         #mbox-cells = <1>;
 762                         ti,mbox-num-users = <4>;
 763                         ti,mbox-num-fifos = <12>;
 764                         status = "disabled";
 765                 };
 766
 767                 mailbox5: mailbox@48840000 {
 768                         compatible = "ti,omap4-mailbox";
 769                         reg = <0x48840000 0x200>;
 770                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 771                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 772                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 773                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 774                         ti,hwmods = "mailbox5";
 775                         #mbox-cells = <1>;
 776                         ti,mbox-num-users = <4>;
 777                         ti,mbox-num-fifos = <12>;
 778                         status = "disabled";
 779                 };
 780
 781                 mailbox6: mailbox@48842000 {
 782                         compatible = "ti,omap4-mailbox";
 783                         reg = <0x48842000 0x200>;
 784                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 785                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 786                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 787                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 788                         ti,hwmods = "mailbox6";
 789                         #mbox-cells = <1>;
 790                         ti,mbox-num-users = <4>;
 791                         ti,mbox-num-fifos = <12>;
 792                         status = "disabled";
 793                 };
 794
 795                 mailbox7: mailbox@48844000 {
 796                         compatible = "ti,omap4-mailbox";
 797                         reg = <0x48844000 0x200>;
 798                         interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 799                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 800                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 801                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 802                         ti,hwmods = "mailbox7";
 803                         #mbox-cells = <1>;
 804                         ti,mbox-num-users = <4>;
 805                         ti,mbox-num-fifos = <12>;
 806                         status = "disabled";
 807                 };
 808
 809                 mailbox8: mailbox@48846000 {
 810                         compatible = "ti,omap4-mailbox";
 811                         reg = <0x48846000 0x200>;
 812                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 813                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 814                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 815                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 816                         ti,hwmods = "mailbox8";
 817                         #mbox-cells = <1>;
 818                         ti,mbox-num-users = <4>;
 819                         ti,mbox-num-fifos = <12>;
 820                         status = "disabled";
 821                 };
 822
 823                 mailbox9: mailbox@4885e000 {
 824                         compatible = "ti,omap4-mailbox";
 825                         reg = <0x4885e000 0x200>;
 826                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 827                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 828                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 829                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 830                         ti,hwmods = "mailbox9";
 831                         #mbox-cells = <1>;
 832                         ti,mbox-num-users = <4>;
 833                         ti,mbox-num-fifos = <12>;
 834                         status = "disabled";
 835                 };
 836
 837                 mailbox10: mailbox@48860000 {
 838                         compatible = "ti,omap4-mailbox";
 839                         reg = <0x48860000 0x200>;
 840                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 841                                      <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 842                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 843                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 844                         ti,hwmods = "mailbox10";
 845                         #mbox-cells = <1>;
 846                         ti,mbox-num-users = <4>;
 847                         ti,mbox-num-fifos = <12>;
 848                         status = "disabled";
 849                 };
 850
 851                 mailbox11: mailbox@48862000 {
 852                         compatible = "ti,omap4-mailbox";
 853                         reg = <0x48862000 0x200>;
 854                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 855                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 856                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 857                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
 858                         ti,hwmods = "mailbox11";
 859                         #mbox-cells = <1>;
 860                         ti,mbox-num-users = <4>;
 861                         ti,mbox-num-fifos = <12>;
 862                         status = "disabled";
 863                 };
 864
 865                 mailbox12: mailbox@48864000 {
 866                         compatible = "ti,omap4-mailbox";
 867                         reg = <0x48864000 0x200>;
 868                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 869                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 870                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 871                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 872                         ti,hwmods = "mailbox12";
 873                         #mbox-cells = <1>;
 874                         ti,mbox-num-users = <4>;
 875                         ti,mbox-num-fifos = <12>;
 876                         status = "disabled";
 877                 };
 878
 879                 mailbox13: mailbox@48802000 {
 880                         compatible = "ti,omap4-mailbox";
 881                         reg = <0x48802000 0x200>;
 882                         interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 883                                      <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 884                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 885                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
 886                         ti,hwmods = "mailbox13";
 887                         #mbox-cells = <1>;
 888                         ti,mbox-num-users = <4>;
 889                         ti,mbox-num-fifos = <12>;
 890                         status = "disabled";
 891                 };
 892
 893                 timer1: timer@4ae18000 {
 894                         compatible = "ti,omap5430-timer";
 895                         reg = <0x4ae18000 0x80>;
 896                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 897                         ti,hwmods = "timer1";
 898                         ti,timer-alwon;
 899                         clock-names = "fck";
 900                         clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
 901                 };
 902
 903                 timer2: timer@48032000 {
 904                         compatible = "ti,omap5430-timer";
 905                         reg = <0x48032000 0x80>;
 906                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 907                         ti,hwmods = "timer2";
 908                 };
 909
 910                 timer3: timer@48034000 {
 911                         compatible = "ti,omap5430-timer";
 912                         reg = <0x48034000 0x80>;
 913                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 914                         ti,hwmods = "timer3";
 915                 };
 916
 917                 timer4: timer@48036000 {
 918                         compatible = "ti,omap5430-timer";
 919                         reg = <0x48036000 0x80>;
 920                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 921                         ti,hwmods = "timer4";
 922                 };
 923
 924                 timer5: timer@48820000 {
 925                         compatible = "ti,omap5430-timer";
 926                         reg = <0x48820000 0x80>;
 927                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 928                         ti,hwmods = "timer5";
 929                 };
 930
 931                 timer6: timer@48822000 {
 932                         compatible = "ti,omap5430-timer";
 933                         reg = <0x48822000 0x80>;
 934                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 935                         ti,hwmods = "timer6";
 936                 };
 937
 938                 timer7: timer@48824000 {
 939                         compatible = "ti,omap5430-timer";
 940                         reg = <0x48824000 0x80>;
 941                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 942                         ti,hwmods = "timer7";
 943                 };
 944
 945                 timer8: timer@48826000 {
 946                         compatible = "ti,omap5430-timer";
 947                         reg = <0x48826000 0x80>;
 948                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 949                         ti,hwmods = "timer8";
 950                 };
 951
 952                 timer9: timer@4803e000 {
 953                         compatible = "ti,omap5430-timer";
 954                         reg = <0x4803e000 0x80>;
 955                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 956                         ti,hwmods = "timer9";
 957                 };
 958
 959                 timer10: timer@48086000 {
 960                         compatible = "ti,omap5430-timer";
 961                         reg = <0x48086000 0x80>;
 962                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 963                         ti,hwmods = "timer10";
 964                 };
 965
 966                 timer11: timer@48088000 {
 967                         compatible = "ti,omap5430-timer";
 968                         reg = <0x48088000 0x80>;
 969                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 970                         ti,hwmods = "timer11";
 971                 };
 972
 973                 timer12: timer@4ae20000 {
 974                         compatible = "ti,omap5430-timer";
 975                         reg = <0x4ae20000 0x80>;
 976                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 977                         ti,hwmods = "timer12";
 978                         ti,timer-alwon;
 979                         ti,timer-secure;
 980                 };
 981
 982                 timer13: timer@48828000 {
 983                         compatible = "ti,omap5430-timer";
 984                         reg = <0x48828000 0x80>;
 985                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 986                         ti,hwmods = "timer13";
 987                 };
 988
 989                 timer14: timer@4882a000 {
 990                         compatible = "ti,omap5430-timer";
 991                         reg = <0x4882a000 0x80>;
 992                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 993                         ti,hwmods = "timer14";
 994                 };
 995
 996                 timer15: timer@4882c000 {
 997                         compatible = "ti,omap5430-timer";
 998                         reg = <0x4882c000 0x80>;
 999                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
1000                         ti,hwmods = "timer15";
1001                 };
1002
1003                 timer16: timer@4882e000 {
1004                         compatible = "ti,omap5430-timer";
1005                         reg = <0x4882e000 0x80>;
1006                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
1007                         ti,hwmods = "timer16";
1008                 };
1009
1010                 wdt2: wdt@4ae14000 {
1011                         compatible = "ti,omap3-wdt";
1012                         reg = <0x4ae14000 0x80>;
1013                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1014                         ti,hwmods = "wd_timer2";
1015                 };
1016
1017                 hwspinlock: spinlock@4a0f6000 {
1018                         compatible = "ti,omap4-hwspinlock";
1019                         reg = <0x4a0f6000 0x1000>;
1020                         ti,hwmods = "spinlock";
1021                         #hwlock-cells = <1>;
1022                 };
1023
1024                 dmm@4e000000 {
1025                         compatible = "ti,omap5-dmm";
1026                         reg = <0x4e000000 0x800>;
1027                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1028                         ti,hwmods = "dmm";
1029                 };
1030
1031                 i2c1: i2c@48070000 {
1032                         compatible = "ti,omap4-i2c";
1033                         reg = <0x48070000 0x100>;
1034                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1035                         #address-cells = <1>;
1036                         #size-cells = <0>;
1037                         ti,hwmods = "i2c1";
1038                         status = "disabled";
1039                 };
1040
1041                 i2c2: i2c@48072000 {
1042                         compatible = "ti,omap4-i2c";
1043                         reg = <0x48072000 0x100>;
1044                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1045                         #address-cells = <1>;
1046                         #size-cells = <0>;
1047                         ti,hwmods = "i2c2";
1048                         status = "disabled";
1049                 };
1050
1051                 i2c3: i2c@48060000 {
1052                         compatible = "ti,omap4-i2c";
1053                         reg = <0x48060000 0x100>;
1054                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1055                         #address-cells = <1>;
1056                         #size-cells = <0>;
1057                         ti,hwmods = "i2c3";
1058                         status = "disabled";
1059                 };
1060
1061                 i2c4: i2c@4807a000 {
1062                         compatible = "ti,omap4-i2c";
1063                         reg = <0x4807a000 0x100>;
1064                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1065                         #address-cells = <1>;
1066                         #size-cells = <0>;
1067                         ti,hwmods = "i2c4";
1068                         status = "disabled";
1069                 };
1070
1071                 i2c5: i2c@4807c000 {
1072                         compatible = "ti,omap4-i2c";
1073                         reg = <0x4807c000 0x100>;
1074                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1075                         #address-cells = <1>;
1076                         #size-cells = <0>;
1077                         ti,hwmods = "i2c5";
1078                         status = "disabled";
1079                 };
1080
1081                 mmc1: mmc@4809c000 {
1082                         compatible = "ti,dra7-sdhci";
1083                         reg = <0x4809c000 0x400>;
1084                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1085                         ti,hwmods = "mmc1";
1086                         status = "disabled";
1087                         pbias-supply = <&pbias_mmc_reg>;
1088                         max-frequency = <192000000>;
1089                 };
1090
1091                 hdqw1w: 1w@480b2000 {
1092                         compatible = "ti,omap3-1w";
1093                         reg = <0x480b2000 0x1000>;
1094                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1095                         ti,hwmods = "hdq1w";
1096                 };
1097
1098                 mmc2: mmc@480b4000 {
1099                         compatible = "ti,dra7-sdhci";
1100                         reg = <0x480b4000 0x400>;
1101                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1102                         ti,hwmods = "mmc2";
1103                         status = "disabled";
1104                         max-frequency = <192000000>;
1105                         /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
1106                         sdhci-caps-mask = <0x7 0x0>;
1107                 };
1108
1109                 mmc3: mmc@480ad000 {
1110                         compatible = "ti,dra7-sdhci";
1111                         reg = <0x480ad000 0x400>;
1112                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1113                         ti,hwmods = "mmc3";
1114                         status = "disabled";
1115                         /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
1116                         max-frequency = <64000000>;
1117                         /* SDMA is not supported */
1118                         sdhci-caps-mask = <0x0 0x400000>;
1119                 };
1120
1121                 mmc4: mmc@480d1000 {
1122                         compatible = "ti,dra7-sdhci";
1123                         reg = <0x480d1000 0x400>;
1124                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1125                         ti,hwmods = "mmc4";
1126                         status = "disabled";
1127                         max-frequency = <192000000>;
1128                         /* SDMA is not supported */
1129                         sdhci-caps-mask = <0x0 0x400000>;
1130                 };
1131
1132                 mmu0_dsp1: mmu@40d01000 {
1133                         compatible = "ti,dra7-dsp-iommu";
1134                         reg = <0x40d01000 0x100>;
1135                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1136                         ti,hwmods = "mmu0_dsp1";
1137                         #iommu-cells = <0>;
1138                         ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1139                         status = "disabled";
1140                 };
1141
1142                 mmu1_dsp1: mmu@40d02000 {
1143                         compatible = "ti,dra7-dsp-iommu";
1144                         reg = <0x40d02000 0x100>;
1145                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1146                         ti,hwmods = "mmu1_dsp1";
1147                         #iommu-cells = <0>;
1148                         ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1149                         status = "disabled";
1150                 };
1151
1152                 mmu_ipu1: mmu@58882000 {
1153                         compatible = "ti,dra7-iommu";
1154                         reg = <0x58882000 0x100>;
1155                         interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1156                         ti,hwmods = "mmu_ipu1";
1157                         #iommu-cells = <0>;
1158                         ti,iommu-bus-err-back;
1159                         status = "disabled";
1160                 };
1161
1162                 mmu_ipu2: mmu@55082000 {
1163                         compatible = "ti,dra7-iommu";
1164                         reg = <0x55082000 0x100>;
1165                         interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1166                         ti,hwmods = "mmu_ipu2";
1167                         #iommu-cells = <0>;
1168                         ti,iommu-bus-err-back;
1169                         status = "disabled";
1170                 };
1171
1172                 abb_mpu: regulator-abb-mpu {
1173                         compatible = "ti,abb-v3";
1174                         regulator-name = "abb_mpu";
1175                         #address-cells = <0>;
1176                         #size-cells = <0>;
1177                         clocks = <&sys_clkin1>;
1178                         ti,settling-time = <50>;
1179                         ti,clock-cycles = <16>;
1180
1181                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1182                               <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1183                               <0x4ae0c158 0x4>;
1184                         reg-names = "setup-address", "control-address",
1185                                     "int-address", "efuse-address",
1186                                     "ldo-address";
1187                         ti,tranxdone-status-mask = <0x80>;
1188                         /* LDOVBBMPU_FBB_MUX_CTRL */
1189                         ti,ldovbb-override-mask = <0x400>;
1190                         /* LDOVBBMPU_FBB_VSET_OUT */
1191                         ti,ldovbb-vset-mask = <0x1F>;
1192
1193                         /*
1194                          * NOTE: only FBB mode used but actual vset will
1195                          * determine final biasing
1196                          */
1197                         ti,abb_info = <
1198                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1199                         1060000         0       0x0     0 0x02000000 0x01F00000
1200                         1160000         0       0x4     0 0x02000000 0x01F00000
1201                         1210000         0       0x8     0 0x02000000 0x01F00000
1202                         >;
1203                 };
1204
1205                 abb_ivahd: regulator-abb-ivahd {
1206                         compatible = "ti,abb-v3";
1207                         regulator-name = "abb_ivahd";
1208                         #address-cells = <0>;
1209                         #size-cells = <0>;
1210                         clocks = <&sys_clkin1>;
1211                         ti,settling-time = <50>;
1212                         ti,clock-cycles = <16>;
1213
1214                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1215                               <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1216                               <0x4a002470 0x4>;
1217                         reg-names = "setup-address", "control-address",
1218                                     "int-address", "efuse-address",
1219                                     "ldo-address";
1220                         ti,tranxdone-status-mask = <0x40000000>;
1221                         /* LDOVBBIVA_FBB_MUX_CTRL */
1222                         ti,ldovbb-override-mask = <0x400>;
1223                         /* LDOVBBIVA_FBB_VSET_OUT */
1224                         ti,ldovbb-vset-mask = <0x1F>;
1225
1226                         /*
1227                          * NOTE: only FBB mode used but actual vset will
1228                          * determine final biasing
1229                          */
1230                         ti,abb_info = <
1231                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1232                         1055000         0       0x0     0 0x02000000 0x01F00000
1233                         1150000         0       0x4     0 0x02000000 0x01F00000
1234                         1250000         0       0x8     0 0x02000000 0x01F00000
1235                         >;
1236                 };
1237
1238                 abb_dspeve: regulator-abb-dspeve {
1239                         compatible = "ti,abb-v3";
1240                         regulator-name = "abb_dspeve";
1241                         #address-cells = <0>;
1242                         #size-cells = <0>;
1243                         clocks = <&sys_clkin1>;
1244                         ti,settling-time = <50>;
1245                         ti,clock-cycles = <16>;
1246
1247                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1248                               <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1249                               <0x4a00246c 0x4>;
1250                         reg-names = "setup-address", "control-address",
1251                                     "int-address", "efuse-address",
1252                                     "ldo-address";
1253                         ti,tranxdone-status-mask = <0x20000000>;
1254                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1255                         ti,ldovbb-override-mask = <0x400>;
1256                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
1257                         ti,ldovbb-vset-mask = <0x1F>;
1258
1259                         /*
1260                          * NOTE: only FBB mode used but actual vset will
1261                          * determine final biasing
1262                          */
1263                         ti,abb_info = <
1264                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1265                         1055000         0       0x0     0 0x02000000 0x01F00000
1266                         1150000         0       0x4     0 0x02000000 0x01F00000
1267                         1250000         0       0x8     0 0x02000000 0x01F00000
1268                         >;
1269                 };
1270
1271                 abb_gpu: regulator-abb-gpu {
1272                         compatible = "ti,abb-v3";
1273                         regulator-name = "abb_gpu";
1274                         #address-cells = <0>;
1275                         #size-cells = <0>;
1276                         clocks = <&sys_clkin1>;
1277                         ti,settling-time = <50>;
1278                         ti,clock-cycles = <16>;
1279
1280                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1281                               <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1282                               <0x4ae0c154 0x4>;
1283                         reg-names = "setup-address", "control-address",
1284                                     "int-address", "efuse-address",
1285                                     "ldo-address";
1286                         ti,tranxdone-status-mask = <0x10000000>;
1287                         /* LDOVBBGPU_FBB_MUX_CTRL */
1288                         ti,ldovbb-override-mask = <0x400>;
1289                         /* LDOVBBGPU_FBB_VSET_OUT */
1290                         ti,ldovbb-vset-mask = <0x1F>;
1291
1292                         /*
1293                          * NOTE: only FBB mode used but actual vset will
1294                          * determine final biasing
1295                          */
1296                         ti,abb_info = <
1297                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1298                         1090000         0       0x0     0 0x02000000 0x01F00000
1299                         1210000         0       0x4     0 0x02000000 0x01F00000
1300                         1280000         0       0x8     0 0x02000000 0x01F00000
1301                         >;
1302                 };
1303
1304                 mcspi1: spi@48098000 {
1305                         compatible = "ti,omap4-mcspi";
1306                         reg = <0x48098000 0x200>;
1307                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1308                         #address-cells = <1>;
1309                         #size-cells = <0>;
1310                         ti,hwmods = "mcspi1";
1311                         ti,spi-num-cs = <4>;
1312                         dmas = <&sdma_xbar 35>,
1313                                <&sdma_xbar 36>,
1314                                <&sdma_xbar 37>,
1315                                <&sdma_xbar 38>,
1316                                <&sdma_xbar 39>,
1317                                <&sdma_xbar 40>,
1318                                <&sdma_xbar 41>,
1319                                <&sdma_xbar 42>;
1320                         dma-names = "tx0", "rx0", "tx1", "rx1",
1321                                     "tx2", "rx2", "tx3", "rx3";
1322                         status = "disabled";
1323                 };
1324
1325                 mcspi2: spi@4809a000 {
1326                         compatible = "ti,omap4-mcspi";
1327                         reg = <0x4809a000 0x200>;
1328                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1329                         #address-cells = <1>;
1330                         #size-cells = <0>;
1331                         ti,hwmods = "mcspi2";
1332                         ti,spi-num-cs = <2>;
1333                         dmas = <&sdma_xbar 43>,
1334                                <&sdma_xbar 44>,
1335                                <&sdma_xbar 45>,
1336                                <&sdma_xbar 46>;
1337                         dma-names = "tx0", "rx0", "tx1", "rx1";
1338                         status = "disabled";
1339                 };
1340
1341                 mcspi3: spi@480b8000 {
1342                         compatible = "ti,omap4-mcspi";
1343                         reg = <0x480b8000 0x200>;
1344                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1345                         #address-cells = <1>;
1346                         #size-cells = <0>;
1347                         ti,hwmods = "mcspi3";
1348                         ti,spi-num-cs = <2>;
1349                         dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1350                         dma-names = "tx0", "rx0";
1351                         status = "disabled";
1352                 };
1353
1354                 mcspi4: spi@480ba000 {
1355                         compatible = "ti,omap4-mcspi";
1356                         reg = <0x480ba000 0x200>;
1357                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1358                         #address-cells = <1>;
1359                         #size-cells = <0>;
1360                         ti,hwmods = "mcspi4";
1361                         ti,spi-num-cs = <1>;
1362                         dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1363                         dma-names = "tx0", "rx0";
1364                         status = "disabled";
1365                 };
1366
1367                 qspi: qspi@4b300000 {
1368                         compatible = "ti,dra7xxx-qspi";
1369                         reg = <0x4b300000 0x100>,
1370                               <0x5c000000 0x4000000>;
1371                         reg-names = "qspi_base", "qspi_mmap";
1372                         syscon-chipselects = <&scm_conf 0x558>;
1373                         #address-cells = <1>;
1374                         #size-cells = <0>;
1375                         ti,hwmods = "qspi";
1376                         clocks = <&l4per_clkctrl DRA7_QSPI_CLKCTRL 25>;
1377                         clock-names = "fck";
1378                         num-cs = <4>;
1379                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1380                         status = "disabled";
1381                 };
1382
1383                 /* OCP2SCP3 */
1384                 ocp2scp@4a090000 {
1385                         compatible = "ti,omap-ocp2scp";
1386                         #address-cells = <1>;
1387                         #size-cells = <1>;
1388                         ranges;
1389                         reg = <0x4a090000 0x20>;
1390                         ti,hwmods = "ocp2scp3";
1391                         sata_phy: phy@4a096000 {
1392                                 compatible = "ti,phy-pipe3-sata";
1393                                 reg = <0x4A096000 0x80>, /* phy_rx */
1394                                       <0x4A096400 0x64>, /* phy_tx */
1395                                       <0x4A096800 0x40>; /* pll_ctrl */
1396                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1397                                 syscon-phy-power = <&scm_conf 0x374>;
1398                                 clocks = <&sys_clkin1>,
1399                                          <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
1400                                 clock-names = "sysclk", "refclk";
1401                                 syscon-pllreset = <&scm_conf 0x3fc>;
1402                                 #phy-cells = <0>;
1403                         };
1404
1405                         pcie1_phy: pciephy@4a094000 {
1406                                 compatible = "ti,phy-pipe3-pcie";
1407                                 reg = <0x4a094000 0x80>, /* phy_rx */
1408                                       <0x4a094400 0x64>; /* phy_tx */
1409                                 reg-names = "phy_rx", "phy_tx";
1410                                 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1411                                 syscon-pcs = <&scm_conf_pcie 0x10>;
1412                                 clocks = <&dpll_pcie_ref_ck>,
1413                                          <&dpll_pcie_ref_m2ldo_ck>,
1414                                          <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 8>,
1415                                          <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 9>,
1416                                          <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 10>,
1417                                          <&optfclk_pciephy_div>,
1418                                          <&sys_clkin1>;
1419                                 clock-names = "dpll_ref", "dpll_ref_m2",
1420                                               "wkupclk", "refclk",
1421                                               "div-clk", "phy-div", "sysclk";
1422                                 #phy-cells = <0>;
1423                         };
1424
1425                         pcie2_phy: pciephy@4a095000 {
1426                                 compatible = "ti,phy-pipe3-pcie";
1427                                 reg = <0x4a095000 0x80>, /* phy_rx */
1428                                       <0x4a095400 0x64>; /* phy_tx */
1429                                 reg-names = "phy_rx", "phy_tx";
1430                                 syscon-phy-power = <&scm_conf_pcie 0x20>;
1431                                 syscon-pcs = <&scm_conf_pcie 0x10>;
1432                                 clocks = <&dpll_pcie_ref_ck>,
1433                                          <&dpll_pcie_ref_m2ldo_ck>,
1434                                          <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 8>,
1435                                          <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 9>,
1436                                          <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 10>,
1437                                          <&optfclk_pciephy_div>,
1438                                          <&sys_clkin1>;
1439                                 clock-names = "dpll_ref", "dpll_ref_m2",
1440                                               "wkupclk", "refclk",
1441                                               "div-clk", "phy-div", "sysclk";
1442                                 #phy-cells = <0>;
1443                                 status = "disabled";
1444                         };
1445                 };
1446
1447                 sata: sata@4a141100 {
1448                         compatible = "snps,dwc-ahci";
1449                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1450                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1451                         phys = <&sata_phy>;
1452                         phy-names = "sata-phy";
1453                         clocks = <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
1454                         ti,hwmods = "sata";
1455                         ports-implemented = <0x1>;
1456                 };
1457
1458                 rtc: rtc@48838000 {
1459                         compatible = "ti,am3352-rtc";
1460                         reg = <0x48838000 0x100>;
1461                         interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1462                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1463                         ti,hwmods = "rtcss";
1464                         clocks = <&sys_32k_ck>;
1465                 };
1466
1467                 /* OCP2SCP1 */
1468                 ocp2scp@4a080000 {
1469                         compatible = "ti,omap-ocp2scp";
1470                         #address-cells = <1>;
1471                         #size-cells = <1>;
1472                         ranges;
1473                         reg = <0x4a080000 0x20>;
1474                         ti,hwmods = "ocp2scp1";
1475
1476                         usb2_phy1: phy@4a084000 {
1477                                 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
1478                                 reg = <0x4a084000 0x400>;
1479                                 syscon-phy-power = <&scm_conf 0x300>;
1480                                 clocks = <&usb_phy1_always_on_clk32k>,
1481                                          <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
1482                                 clock-names =   "wkupclk",
1483                                                 "refclk";
1484                                 #phy-cells = <0>;
1485                         };
1486
1487                         usb2_phy2: phy@4a085000 {
1488                                 compatible = "ti,dra7x-usb2-phy2",
1489                                              "ti,omap-usb2";
1490                                 reg = <0x4a085000 0x400>;
1491                                 syscon-phy-power = <&scm_conf 0xe74>;
1492                                 clocks = <&usb_phy2_always_on_clk32k>,
1493                                          <&l3init_clkctrl DRA7_USB_OTG_SS2_CLKCTRL 8>;
1494                                 clock-names =   "wkupclk",
1495                                                 "refclk";
1496                                 #phy-cells = <0>;
1497                         };
1498
1499                         usb3_phy1: phy@4a084400 {
1500                                 compatible = "ti,omap-usb3";
1501                                 reg = <0x4a084400 0x80>,
1502                                       <0x4a084800 0x64>,
1503                                       <0x4a084c00 0x40>;
1504                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1505                                 syscon-phy-power = <&scm_conf 0x370>;
1506                                 clocks = <&usb_phy3_always_on_clk32k>,
1507                                          <&sys_clkin1>,
1508                                          <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
1509                                 clock-names =   "wkupclk",
1510                                                 "sysclk",
1511                                                 "refclk";
1512                                 #phy-cells = <0>;
1513                         };
1514                 };
1515
1516                 target-module@4a0dd000 {
1517                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
1518                         ti,hwmods = "smartreflex_core";
1519                         reg = <0x4a0dd038 0x4>;
1520                         reg-names = "sysc";
1521                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
1522                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1523                                         <SYSC_IDLE_NO>,
1524                                         <SYSC_IDLE_SMART>,
1525                                         <SYSC_IDLE_SMART_WKUP>;
1526                         clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_CORE_CLKCTRL 0>;
1527                         clock-names = "fck";
1528                         #address-cells = <1>;
1529                         #size-cells = <1>;
1530                         ranges = <0 0x4a0dd000 0x001000>;
1531
1532                         /* SmartReflex child device marked reserved in TRM */
1533                 };
1534
1535                 target-module@4a0d9000 {
1536                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
1537                         ti,hwmods = "smartreflex_mpu";
1538                         reg = <0x4a0d9038 0x4>;
1539                         reg-names = "sysc";
1540                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
1541                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1542                                         <SYSC_IDLE_NO>,
1543                                         <SYSC_IDLE_SMART>,
1544                                         <SYSC_IDLE_SMART_WKUP>;
1545                         clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_MPU_CLKCTRL 0>;
1546                         clock-names = "fck";
1547                         #address-cells = <1>;
1548                         #size-cells = <1>;
1549                         ranges = <0 0x4a0d9000 0x001000>;
1550
1551                         /* SmartReflex child device marked reserved in TRM */
1552                 };
1553
1554                 omap_dwc3_1: omap_dwc3_1@48880000 {
1555                         compatible = "ti,dwc3";
1556                         ti,hwmods = "usb_otg_ss1";
1557                         reg = <0x48880000 0x10000>;
1558                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1559                         #address-cells = <1>;
1560                         #size-cells = <1>;
1561                         utmi-mode = <2>;
1562                         ranges;
1563                         usb1: usb@48890000 {
1564                                 compatible = "snps,dwc3";
1565                                 reg = <0x48890000 0x17000>;
1566                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1567                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1568                                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1569                                 interrupt-names = "peripheral",
1570                                                   "host",
1571                                                   "otg";
1572                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1573                                 phy-names = "usb2-phy", "usb3-phy";
1574                                 maximum-speed = "super-speed";
1575                                 dr_mode = "otg";
1576                                 snps,dis_u3_susphy_quirk;
1577                                 snps,dis_u2_susphy_quirk;
1578                                 snps,dis_metastability_quirk;
1579                         };
1580                 };
1581
1582                 omap_dwc3_2: omap_dwc3_2@488c0000 {
1583                         compatible = "ti,dwc3";
1584                         ti,hwmods = "usb_otg_ss2";
1585                         reg = <0x488c0000 0x10000>;
1586                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1587                         #address-cells = <1>;
1588                         #size-cells = <1>;
1589                         utmi-mode = <2>;
1590                         ranges;
1591                         usb2: usb@488d0000 {
1592                                 compatible = "snps,dwc3";
1593                                 reg = <0x488d0000 0x17000>;
1594                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1595                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1596                                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1597                                 interrupt-names = "peripheral",
1598                                                   "host",
1599                                                   "otg";
1600                                 phys = <&usb2_phy2>;
1601                                 phy-names = "usb2-phy";
1602                                 maximum-speed = "high-speed";
1603                                 dr_mode = "otg";
1604                                 snps,dis_u3_susphy_quirk;
1605                                 snps,dis_u2_susphy_quirk;
1606                         };
1607                 };
1608
1609                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1610                 omap_dwc3_3: omap_dwc3_3@48900000 {
1611                         compatible = "ti,dwc3";
1612                         ti,hwmods = "usb_otg_ss3";
1613                         reg = <0x48900000 0x10000>;
1614                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1615                         #address-cells = <1>;
1616                         #size-cells = <1>;
1617                         utmi-mode = <2>;
1618                         ranges;
1619                         status = "disabled";
1620                         usb3: usb@48910000 {
1621                                 compatible = "snps,dwc3";
1622                                 reg = <0x48910000 0x17000>;
1623                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1624                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1625                                              <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1626                                 interrupt-names = "peripheral",
1627                                                   "host",
1628                                                   "otg";
1629                                 maximum-speed = "high-speed";
1630                                 dr_mode = "otg";
1631                                 snps,dis_u3_susphy_quirk;
1632                                 snps,dis_u2_susphy_quirk;
1633                         };
1634                 };
1635
1636                 elm: elm@48078000 {
1637                         compatible = "ti,am3352-elm";
1638                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1639                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1640                         ti,hwmods = "elm";
1641                         status = "disabled";
1642                 };
1643
1644                 gpmc: gpmc@50000000 {
1645                         compatible = "ti,am3352-gpmc";
1646                         ti,hwmods = "gpmc";
1647                         reg = <0x50000000 0x37c>;      /* device IO registers */
1648                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1649                         dmas = <&edma_xbar 4 0>;
1650                         dma-names = "rxtx";
1651                         gpmc,num-cs = <8>;
1652                         gpmc,num-waitpins = <2>;
1653                         #address-cells = <2>;
1654                         #size-cells = <1>;
1655                         interrupt-controller;
1656                         #interrupt-cells = <2>;
1657                         gpio-controller;
1658                         #gpio-cells = <2>;
1659                         status = "disabled";
1660                 };
1661
1662                 atl: atl@4843c000 {
1663                         compatible = "ti,dra7-atl";
1664                         reg = <0x4843c000 0x3ff>;
1665                         ti,hwmods = "atl";
1666                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1667                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1668                         clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
1669                         clock-names = "fck";
1670                         status = "disabled";
1671                 };
1672
1673                 mcasp1: mcasp@48460000 {
1674                         compatible = "ti,dra7-mcasp-audio";
1675                         ti,hwmods = "mcasp1";
1676                         reg = <0x48460000 0x2000>,
1677                               <0x45800000 0x1000>;
1678                         reg-names = "mpu","dat";
1679                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1680                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1681                         interrupt-names = "tx", "rx";
1682                         dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1683                         dma-names = "tx", "rx";
1684                         clocks = <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 24>,
1685                                  <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 28>;
1686                         clock-names = "fck", "ahclkx", "ahclkr";
1687                         status = "disabled";
1688                 };
1689
1690                 mcasp2: mcasp@48464000 {
1691                         compatible = "ti,dra7-mcasp-audio";
1692                         ti,hwmods = "mcasp2";
1693                         reg = <0x48464000 0x2000>,
1694                               <0x45c00000 0x1000>;
1695                         reg-names = "mpu","dat";
1696                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1697                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1698                         interrupt-names = "tx", "rx";
1699                         dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1700                         dma-names = "tx", "rx";
1701                         clocks = <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 22>,
1702                                  <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 24>,
1703                                  <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 28>;
1704                         clock-names = "fck", "ahclkx", "ahclkr";
1705                         status = "disabled";
1706                 };
1707
1708                 mcasp3: mcasp@48468000 {
1709                         compatible = "ti,dra7-mcasp-audio";
1710                         ti,hwmods = "mcasp3";
1711                         reg = <0x48468000 0x2000>,
1712                               <0x46000000 0x1000>;
1713                         reg-names = "mpu","dat";
1714                         interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1715                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1716                         interrupt-names = "tx", "rx";
1717                         dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1718                         dma-names = "tx", "rx";
1719                         clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>,
1720                                  <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
1721                         clock-names = "fck", "ahclkx";
1722                         status = "disabled";
1723                 };
1724
1725                 mcasp4: mcasp@4846c000 {
1726                         compatible = "ti,dra7-mcasp-audio";
1727                         ti,hwmods = "mcasp4";
1728                         reg = <0x4846c000 0x2000>,
1729                               <0x48436000 0x1000>;
1730                         reg-names = "mpu","dat";
1731                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1732                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1733                         interrupt-names = "tx", "rx";
1734                         dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1735                         dma-names = "tx", "rx";
1736                         clocks = <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 22>,
1737                                  <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 24>;
1738                         clock-names = "fck", "ahclkx";
1739                         status = "disabled";
1740                 };
1741
1742                 mcasp5: mcasp@48470000 {
1743                         compatible = "ti,dra7-mcasp-audio";
1744                         ti,hwmods = "mcasp5";
1745                         reg = <0x48470000 0x2000>,
1746                               <0x4843a000 0x1000>;
1747                         reg-names = "mpu","dat";
1748                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1749                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1750                         interrupt-names = "tx", "rx";
1751                         dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1752                         dma-names = "tx", "rx";
1753                         clocks = <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 22>,
1754                                  <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 24>;
1755                         clock-names = "fck", "ahclkx";
1756                         status = "disabled";
1757                 };
1758
1759                 mcasp6: mcasp@48474000 {
1760                         compatible = "ti,dra7-mcasp-audio";
1761                         ti,hwmods = "mcasp6";
1762                         reg = <0x48474000 0x2000>,
1763                               <0x4844c000 0x1000>;
1764                         reg-names = "mpu","dat";
1765                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1766                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1767                         interrupt-names = "tx", "rx";
1768                         dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1769                         dma-names = "tx", "rx";
1770                         clocks = <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 22>,
1771                                  <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 24>;
1772                         clock-names = "fck", "ahclkx";
1773                         status = "disabled";
1774                 };
1775
1776                 mcasp7: mcasp@48478000 {
1777                         compatible = "ti,dra7-mcasp-audio";
1778                         ti,hwmods = "mcasp7";
1779                         reg = <0x48478000 0x2000>,
1780                               <0x48450000 0x1000>;
1781                         reg-names = "mpu","dat";
1782                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1783                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1784                         interrupt-names = "tx", "rx";
1785                         dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1786                         dma-names = "tx", "rx";
1787                         clocks = <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 22>,
1788                                  <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 24>;
1789                         clock-names = "fck", "ahclkx";
1790                         status = "disabled";
1791                 };
1792
1793                 mcasp8: mcasp@4847c000 {
1794                         compatible = "ti,dra7-mcasp-audio";
1795                         ti,hwmods = "mcasp8";
1796                         reg = <0x4847c000 0x2000>,
1797                               <0x48454000 0x1000>;
1798                         reg-names = "mpu","dat";
1799                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1800                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1801                         interrupt-names = "tx", "rx";
1802                         dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1803                         dma-names = "tx", "rx";
1804                         clocks = <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 22>,
1805                                  <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 24>;
1806                         clock-names = "fck", "ahclkx";
1807                         status = "disabled";
1808                 };
1809
1810                 crossbar_mpu: crossbar@4a002a48 {
1811                         compatible = "ti,irq-crossbar";
1812                         reg = <0x4a002a48 0x130>;
1813                         interrupt-controller;
1814                         interrupt-parent = <&wakeupgen>;
1815                         #interrupt-cells = <3>;
1816                         ti,max-irqs = <160>;
1817                         ti,max-crossbar-sources = <MAX_SOURCES>;
1818                         ti,reg-size = <2>;
1819                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1820                         ti,irqs-skip = <10 133 139 140>;
1821                         ti,irqs-safe-map = <0>;
1822                 };
1823
1824                 mac: ethernet@48484000 {
1825                         compatible = "ti,dra7-cpsw","ti,cpsw";
1826                         ti,hwmods = "gmac";
1827                         clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>;
1828                         clock-names = "fck", "cpts";
1829                         cpdma_channels = <8>;
1830                         ale_entries = <1024>;
1831                         bd_ram_size = <0x2000>;
1832                         mac_control = <0x20>;
1833                         slaves = <2>;
1834                         active_slave = <0>;
1835                         cpts_clock_mult = <0x784CFE14>;
1836                         cpts_clock_shift = <29>;
1837                         reg = <0x48484000 0x1000
1838                                0x48485200 0x2E00>;
1839                         #address-cells = <1>;
1840                         #size-cells = <1>;
1841
1842                         /*
1843                          * Do not allow gating of cpsw clock as workaround
1844                          * for errata i877. Keeping internal clock disabled
1845                          * causes the device switching characteristics
1846                          * to degrade over time and eventually fail to meet
1847                          * the data manual delay time/skew specs.
1848                          */
1849                         ti,no-idle;
1850
1851                         /*
1852                          * rx_thresh_pend
1853                          * rx_pend
1854                          * tx_pend
1855                          * misc_pend
1856                          */
1857                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1858                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1859                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1860                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1861                         ranges;
1862                         syscon = <&scm_conf>;
1863                         status = "disabled";
1864
1865                         davinci_mdio: mdio@48485000 {
1866                                 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1867                                 #address-cells = <1>;
1868                                 #size-cells = <0>;
1869                                 ti,hwmods = "davinci_mdio";
1870                                 bus_freq = <1000000>;
1871                                 reg = <0x48485000 0x100>;
1872                         };
1873
1874                         cpsw_emac0: slave@48480200 {
1875                                 /* Filled in by U-Boot */
1876                                 mac-address = [ 00 00 00 00 00 00 ];
1877                         };
1878
1879                         cpsw_emac1: slave@48480300 {
1880                                 /* Filled in by U-Boot */
1881                                 mac-address = [ 00 00 00 00 00 00 ];
1882                         };
1883
1884                         phy_sel: cpsw-phy-sel@4a002554 {
1885                                 compatible = "ti,dra7xx-cpsw-phy-sel";
1886                                 reg= <0x4a002554 0x4>;
1887                                 reg-names = "gmii-sel";
1888                         };
1889                 };
1890
1891                 dcan1: can@481cc000 {
1892                         compatible = "ti,dra7-d_can";
1893                         ti,hwmods = "dcan1";
1894                         reg = <0x4ae3c000 0x2000>;
1895                         syscon-raminit = <&scm_conf 0x558 0>;
1896                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1897                         clocks = <&wkupaon_clkctrl DRA7_DCAN1_CLKCTRL 24>;
1898                         status = "disabled";
1899                 };
1900
1901                 dcan2: can@481d0000 {
1902                         compatible = "ti,dra7-d_can";
1903                         ti,hwmods = "dcan2";
1904                         reg = <0x48480000 0x2000>;
1905                         syscon-raminit = <&scm_conf 0x558 1>;
1906                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1907                         clocks = <&sys_clkin1>;
1908                         status = "disabled";
1909                 };
1910
1911                 dss: dss@58000000 {
1912                         compatible = "ti,dra7-dss";
1913                         /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1914                         /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1915                         status = "disabled";
1916                         ti,hwmods = "dss_core";
1917                         /* CTRL_CORE_DSS_PLL_CONTROL */
1918                         syscon-pll-ctrl = <&scm_conf 0x538>;
1919                         #address-cells = <1>;
1920                         #size-cells = <1>;
1921                         ranges;
1922
1923                         dispc@58001000 {
1924                                 compatible = "ti,dra7-dispc";
1925                                 reg = <0x58001000 0x1000>;
1926                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1927                                 ti,hwmods = "dss_dispc";
1928                                 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
1929                                 clock-names = "fck";
1930                                 /* CTRL_CORE_SMA_SW_1 */
1931                                 syscon-pol = <&scm_conf 0x534>;
1932                         };
1933
1934                         hdmi: encoder@58060000 {
1935                                 compatible = "ti,dra7-hdmi";
1936                                 reg = <0x58040000 0x200>,
1937                                       <0x58040200 0x80>,
1938                                       <0x58040300 0x80>,
1939                                       <0x58060000 0x19000>;
1940                                 reg-names = "wp", "pll", "phy", "core";
1941                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1942                                 status = "disabled";
1943                                 ti,hwmods = "dss_hdmi";
1944                                 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
1945                                          <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>;
1946                                 clock-names = "fck", "sys_clk";
1947                                 dmas = <&sdma_xbar 76>;
1948                                 dma-names = "audio_tx";
1949                         };
1950                 };
1951
1952                 epwmss0: epwmss@4843e000 {
1953                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1954                         reg = <0x4843e000 0x30>;
1955                         ti,hwmods = "epwmss0";
1956                         #address-cells = <1>;
1957                         #size-cells = <1>;
1958                         status = "disabled";
1959                         ranges;
1960
1961                         ehrpwm0: pwm@4843e200 {
1962                                 compatible = "ti,dra746-ehrpwm",
1963                                              "ti,am3352-ehrpwm";
1964                                 #pwm-cells = <3>;
1965                                 reg = <0x4843e200 0x80>;
1966                                 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1967                                 clock-names = "tbclk", "fck";
1968                                 status = "disabled";
1969                         };
1970
1971                         ecap0: ecap@4843e100 {
1972                                 compatible = "ti,dra746-ecap",
1973                                              "ti,am3352-ecap";
1974                                 #pwm-cells = <3>;
1975                                 reg = <0x4843e100 0x80>;
1976                                 clocks = <&l4_root_clk_div>;
1977                                 clock-names = "fck";
1978                                 status = "disabled";
1979                         };
1980                 };
1981
1982                 epwmss1: epwmss@48440000 {
1983                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1984                         reg = <0x48440000 0x30>;
1985                         ti,hwmods = "epwmss1";
1986                         #address-cells = <1>;
1987                         #size-cells = <1>;
1988                         status = "disabled";
1989                         ranges;
1990
1991                         ehrpwm1: pwm@48440200 {
1992                                 compatible = "ti,dra746-ehrpwm",
1993                                              "ti,am3352-ehrpwm";
1994                                 #pwm-cells = <3>;
1995                                 reg = <0x48440200 0x80>;
1996                                 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
1997                                 clock-names = "tbclk", "fck";
1998                                 status = "disabled";
1999                         };
2000
2001                         ecap1: ecap@48440100 {
2002                                 compatible = "ti,dra746-ecap",
2003                                              "ti,am3352-ecap";
2004                                 #pwm-cells = <3>;
2005                                 reg = <0x48440100 0x80>;
2006                                 clocks = <&l4_root_clk_div>;
2007                                 clock-names = "fck";
2008                                 status = "disabled";
2009                         };
2010                 };
2011
2012                 epwmss2: epwmss@48442000 {
2013                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2014                         reg = <0x48442000 0x30>;
2015                         ti,hwmods = "epwmss2";
2016                         #address-cells = <1>;
2017                         #size-cells = <1>;
2018                         status = "disabled";
2019                         ranges;
2020
2021                         ehrpwm2: pwm@48442200 {
2022                                 compatible = "ti,dra746-ehrpwm",
2023                                              "ti,am3352-ehrpwm";
2024                                 #pwm-cells = <3>;
2025                                 reg = <0x48442200 0x80>;
2026                                 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
2027                                 clock-names = "tbclk", "fck";
2028                                 status = "disabled";
2029                         };
2030
2031                         ecap2: ecap@48442100 {
2032                                 compatible = "ti,dra746-ecap",
2033                                              "ti,am3352-ecap";
2034                                 #pwm-cells = <3>;
2035                                 reg = <0x48442100 0x80>;
2036                                 clocks = <&l4_root_clk_div>;
2037                                 clock-names = "fck";
2038                                 status = "disabled";
2039                         };
2040                 };
2041
2042                 aes1: aes@4b500000 {
2043                         compatible = "ti,omap4-aes";
2044                         ti,hwmods = "aes1";
2045                         reg = <0x4b500000 0xa0>;
2046                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
2047                         dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
2048                         dma-names = "tx", "rx";
2049                         clocks = <&l3_iclk_div>;
2050                         clock-names = "fck";
2051                 };
2052
2053                 aes2: aes@4b700000 {
2054                         compatible = "ti,omap4-aes";
2055                         ti,hwmods = "aes2";
2056                         reg = <0x4b700000 0xa0>;
2057                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
2058                         dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
2059                         dma-names = "tx", "rx";
2060                         clocks = <&l3_iclk_div>;
2061                         clock-names = "fck";
2062                 };
2063
2064                 des: des@480a5000 {
2065                         compatible = "ti,omap4-des";
2066                         ti,hwmods = "des";
2067                         reg = <0x480a5000 0xa0>;
2068                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
2069                         dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
2070                         dma-names = "tx", "rx";
2071                         clocks = <&l3_iclk_div>;
2072                         clock-names = "fck";
2073                 };
2074
2075                 sham: sham@53100000 {
2076                         compatible = "ti,omap5-sham";
2077                         ti,hwmods = "sham";
2078                         reg = <0x4b101000 0x300>;
2079                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
2080                         dmas = <&edma_xbar 119 0>;
2081                         dma-names = "rx";
2082                         clocks = <&l3_iclk_div>;
2083                         clock-names = "fck";
2084                 };
2085
2086                 rng: rng@48090000 {
2087                         compatible = "ti,omap4-rng";
2088                         ti,hwmods = "rng";
2089                         reg = <0x48090000 0x2000>;
2090                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2091                         clocks = <&l3_iclk_div>;
2092                         clock-names = "fck";
2093                 };
2094
2095                 opp_supply_mpu: opp-supply@4a003b20 {
2096                         compatible = "ti,omap5-opp-supply";
2097                         reg = <0x4a003b20 0xc>;
2098                         ti,efuse-settings = <
2099                         /* uV   offset */
2100                         1060000 0x0
2101                         1160000 0x4
2102                         1210000 0x8
2103                         >;
2104                         ti,absolute-max-voltage-uv = <1500000>;
2105                 };
2106
2107         };
2108
2109         thermal_zones: thermal-zones {
2110                 #include "omap4-cpu-thermal.dtsi"
2111                 #include "omap5-gpu-thermal.dtsi"
2112                 #include "omap5-core-thermal.dtsi"
2113                 #include "dra7-dspeve-thermal.dtsi"
2114                 #include "dra7-iva-thermal.dtsi"
2115         };
2116
2117 };
2118
2119 &cpu_thermal {
2120         polling-delay = <500>; /* milliseconds */
2121         coefficients = <0 2000>;
2122 };
2123
2124 &gpu_thermal {
2125         coefficients = <0 2000>;
2126 };
2127
2128 &core_thermal {
2129         coefficients = <0 2000>;
2130 };
2131
2132 &dspeve_thermal {
2133         coefficients = <0 2000>;
2134 };
2135
2136 &iva_thermal {
2137         coefficients = <0 2000>;
2138 };
2139
2140 &cpu_crit {
2141         temperature = <120000>; /* milli Celsius */
2142 };
2143
2144 #include "dra7xx-clocks.dtsi"
2145
2146 &core_crit {
2147         temperature = <120000>; /* milli Celsius */
2148 };
2149
2150 &gpu_crit {
2151         temperature = <120000>; /* milli Celsius */
2152 };
2153
2154 &dspeve_crit {
2155         temperature = <120000>; /* milli Celsius */
2156 };
2157
2158 &iva_crit {
2159         temperature = <120000>; /* milli Celsius */
2160 };