2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
13 #define MAX_SOURCES 400
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&crossbar_mpu>;
39 ethernet0 = &cpsw_emac0;
40 ethernet1 = &cpsw_emac1;
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&gic>;
55 gic: interrupt-controller@48211000 {
56 compatible = "arm,cortex-a15-gic";
58 #interrupt-cells = <3>;
59 reg = <0x0 0x48211000 0x0 0x1000>,
60 <0x0 0x48212000 0x0 0x2000>,
61 <0x0 0x48214000 0x0 0x2000>,
62 <0x0 0x48216000 0x0 0x2000>;
63 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
64 interrupt-parent = <&gic>;
67 wakeupgen: interrupt-controller@48281000 {
68 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 #interrupt-cells = <3>;
71 reg = <0x0 0x48281000 0x0 0x1000>;
72 interrupt-parent = <&gic>;
81 compatible = "arm,cortex-a15";
90 clocks = <&dpll_mpu_ck>;
93 clock-latency = <300000>; /* From omap-cpufreq driver */
96 cooling-min-level = <0>;
97 cooling-max-level = <2>;
98 #cooling-cells = <2>; /* min followed by max */
103 * The soc node represents the soc top level view. It is used for IPs
104 * that are not memory mapped in the MPU view or for the MPU itself.
107 compatible = "ti,omap-infra";
109 compatible = "ti,omap5-mpu";
115 * XXX: Use a flat representation of the SOC interconnect.
116 * The real OMAP interconnect network is quite complex.
117 * Since it will not bring real advantage to represent that in DT for
118 * the moment, just use a fake OCP bus entry to represent the whole bus
122 compatible = "ti,dra7-l3-noc", "simple-bus";
123 #address-cells = <1>;
125 ranges = <0x0 0x0 0x0 0xc0000000>;
126 ti,hwmods = "l3_main_1", "l3_main_2";
127 reg = <0x0 0x44000000 0x0 0x1000000>,
128 <0x0 0x45000000 0x0 0x1000>;
129 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
130 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
132 l4_cfg: l4@4a000000 {
133 compatible = "ti,dra7-l4-cfg", "simple-bus";
134 #address-cells = <1>;
136 ranges = <0 0x4a000000 0x22c000>;
139 compatible = "ti,dra7-scm-core", "simple-bus";
140 reg = <0x2000 0x2000>;
141 #address-cells = <1>;
143 ranges = <0 0x2000 0x2000>;
145 scm_conf: scm_conf@0 {
146 compatible = "syscon", "simple-bus";
148 #address-cells = <1>;
150 ranges = <0 0x0 0x1400>;
152 pbias_regulator: pbias_regulator@e00 {
153 compatible = "ti,pbias-dra7", "ti,pbias-omap";
155 syscon = <&scm_conf>;
156 pbias_mmc_reg: pbias_mmc_omap5 {
157 regulator-name = "pbias_mmc_omap5";
158 regulator-min-microvolt = <1800000>;
159 regulator-max-microvolt = <3000000>;
163 scm_conf_clocks: clocks {
164 #address-cells = <1>;
169 dra7_pmx_core: pinmux@1400 {
170 compatible = "ti,dra7-padconf",
172 reg = <0x1400 0x0468>;
173 #address-cells = <1>;
175 #pinctrl-cells = <1>;
176 #interrupt-cells = <1>;
177 interrupt-controller;
178 pinctrl-single,register-width = <32>;
179 pinctrl-single,function-mask = <0x3fffffff>;
182 scm_conf1: scm_conf@1c04 {
183 compatible = "syscon";
184 reg = <0x1c04 0x0020>;
187 scm_conf_pcie: scm_conf@1c24 {
188 compatible = "syscon";
189 reg = <0x1c24 0x0024>;
192 sdma_xbar: dma-router@b78 {
193 compatible = "ti,dra7-dma-crossbar";
196 dma-requests = <205>;
197 ti,dma-safe-map = <0>;
198 dma-masters = <&sdma>;
201 edma_xbar: dma-router@c78 {
202 compatible = "ti,dra7-dma-crossbar";
205 dma-requests = <204>;
206 ti,dma-safe-map = <0>;
207 dma-masters = <&edma>;
211 cm_core_aon: cm_core_aon@5000 {
212 compatible = "ti,dra7-cm-core-aon";
213 reg = <0x5000 0x2000>;
215 cm_core_aon_clocks: clocks {
216 #address-cells = <1>;
220 cm_core_aon_clockdomains: clockdomains {
224 cm_core: cm_core@8000 {
225 compatible = "ti,dra7-cm-core";
226 reg = <0x8000 0x3000>;
228 cm_core_clocks: clocks {
229 #address-cells = <1>;
233 cm_core_clockdomains: clockdomains {
238 l4_wkup: l4@4ae00000 {
239 compatible = "ti,dra7-l4-wkup", "simple-bus";
240 #address-cells = <1>;
242 ranges = <0 0x4ae00000 0x3f000>;
244 counter32k: counter@4000 {
245 compatible = "ti,omap-counter32k";
247 ti,hwmods = "counter_32k";
251 compatible = "ti,dra7-prm";
252 reg = <0x6000 0x3000>;
253 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
256 #address-cells = <1>;
260 prm_clockdomains: clockdomains {
264 scm_wkup: scm_conf@c000 {
265 compatible = "syscon";
266 reg = <0xc000 0x1000>;
271 compatible = "simple-bus";
273 #address-cells = <1>;
274 ranges = <0x51000000 0x51000000 0x3000
275 0x0 0x20000000 0x10000000>;
276 pcie1: pcie@51000000 {
277 compatible = "ti,dra7-pcie";
278 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
279 reg-names = "rc_dbics", "ti_conf", "config";
280 interrupts = <0 232 0x4>, <0 233 0x4>;
281 #address-cells = <3>;
284 ranges = <0x81000000 0 0 0x03000 0 0x00010000
285 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
286 bus-range = <0x00 0xff>;
287 #interrupt-cells = <1>;
289 linux,pci-domain = <0>;
292 phy-names = "pcie-phy0";
293 interrupt-map-mask = <0 0 0 7>;
294 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
295 <0 0 0 2 &pcie1_intc 2>,
296 <0 0 0 3 &pcie1_intc 3>,
297 <0 0 0 4 &pcie1_intc 4>;
298 pcie1_intc: interrupt-controller {
299 interrupt-controller;
300 #address-cells = <0>;
301 #interrupt-cells = <1>;
307 compatible = "simple-bus";
309 #address-cells = <1>;
310 ranges = <0x51800000 0x51800000 0x3000
311 0x0 0x30000000 0x10000000>;
314 compatible = "ti,dra7-pcie";
315 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
316 reg-names = "rc_dbics", "ti_conf", "config";
317 interrupts = <0 355 0x4>, <0 356 0x4>;
318 #address-cells = <3>;
321 ranges = <0x81000000 0 0 0x03000 0 0x00010000
322 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
323 bus-range = <0x00 0xff>;
324 #interrupt-cells = <1>;
326 linux,pci-domain = <1>;
329 phy-names = "pcie-phy0";
330 interrupt-map-mask = <0 0 0 7>;
331 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
332 <0 0 0 2 &pcie2_intc 2>,
333 <0 0 0 3 &pcie2_intc 3>,
334 <0 0 0 4 &pcie2_intc 4>;
335 pcie2_intc: interrupt-controller {
336 interrupt-controller;
337 #address-cells = <0>;
338 #interrupt-cells = <1>;
343 ocmcram1: ocmcram@40300000 {
344 compatible = "mmio-sram";
345 reg = <0x40300000 0x80000>;
346 ranges = <0x0 0x40300000 0x80000>;
347 #address-cells = <1>;
350 * This is a placeholder for an optional reserved
351 * region for use by secure software. The size
352 * of this region is not known until runtime so it
353 * is set as zero to either be updated to reserve
354 * space or left unchanged to leave all SRAM for use.
355 * On HS parts that that require the reserved region
356 * either the bootloader can update the size to
357 * the required amount or the node can be overridden
358 * from the board dts file for the secure platform.
361 compatible = "ti,secure-ram";
367 * NOTE: ocmcram2 and ocmcram3 are not available on all
368 * DRA7xx and AM57xx variants. Confirm availability in
369 * the data manual for the exact part number in use
370 * before enabling these nodes in the board dts file.
372 ocmcram2: ocmcram@40400000 {
374 compatible = "mmio-sram";
375 reg = <0x40400000 0x100000>;
376 ranges = <0x0 0x40400000 0x100000>;
377 #address-cells = <1>;
381 ocmcram3: ocmcram@40500000 {
383 compatible = "mmio-sram";
384 reg = <0x40500000 0x100000>;
385 ranges = <0x0 0x40500000 0x100000>;
386 #address-cells = <1>;
390 bandgap: bandgap@4a0021e0 {
391 reg = <0x4a0021e0 0xc
397 compatible = "ti,dra752-bandgap";
398 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
399 #thermal-sensor-cells = <1>;
402 dsp1_system: dsp_system@40d00000 {
403 compatible = "syscon";
404 reg = <0x40d00000 0x100>;
407 sdma: dma-controller@4a056000 {
408 compatible = "ti,omap4430-sdma";
409 reg = <0x4a056000 0x1000>;
410 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
416 dma-requests = <127>;
419 edma: edma@43300000 {
420 compatible = "ti,edma3-tpcc";
422 reg = <0x43300000 0x100000>;
423 reg-names = "edma3_cc";
424 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
427 interrupt-names = "edma3_ccint", "edma3_mperr",
432 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
435 * memcpy is disabled, can be enabled with:
436 * ti,edma-memcpy-channels = <20 21>;
437 * for example. Note that these channels need to be
438 * masked in the xbar as well.
442 edma_tptc0: tptc@43400000 {
443 compatible = "ti,edma3-tptc";
445 reg = <0x43400000 0x100000>;
446 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "edma3_tcerrint";
450 edma_tptc1: tptc@43500000 {
451 compatible = "ti,edma3-tptc";
453 reg = <0x43500000 0x100000>;
454 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
455 interrupt-names = "edma3_tcerrint";
458 gpio1: gpio@4ae10000 {
459 compatible = "ti,omap4-gpio";
460 reg = <0x4ae10000 0x200>;
461 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
465 interrupt-controller;
466 #interrupt-cells = <2>;
469 gpio2: gpio@48055000 {
470 compatible = "ti,omap4-gpio";
471 reg = <0x48055000 0x200>;
472 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
480 gpio3: gpio@48057000 {
481 compatible = "ti,omap4-gpio";
482 reg = <0x48057000 0x200>;
483 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
491 gpio4: gpio@48059000 {
492 compatible = "ti,omap4-gpio";
493 reg = <0x48059000 0x200>;
494 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
498 interrupt-controller;
499 #interrupt-cells = <2>;
502 gpio5: gpio@4805b000 {
503 compatible = "ti,omap4-gpio";
504 reg = <0x4805b000 0x200>;
505 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
509 interrupt-controller;
510 #interrupt-cells = <2>;
513 gpio6: gpio@4805d000 {
514 compatible = "ti,omap4-gpio";
515 reg = <0x4805d000 0x200>;
516 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
520 interrupt-controller;
521 #interrupt-cells = <2>;
524 gpio7: gpio@48051000 {
525 compatible = "ti,omap4-gpio";
526 reg = <0x48051000 0x200>;
527 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
531 interrupt-controller;
532 #interrupt-cells = <2>;
535 gpio8: gpio@48053000 {
536 compatible = "ti,omap4-gpio";
537 reg = <0x48053000 0x200>;
538 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
542 interrupt-controller;
543 #interrupt-cells = <2>;
546 uart1: serial@4806a000 {
547 compatible = "ti,dra742-uart", "ti,omap4-uart";
548 reg = <0x4806a000 0x100>;
549 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
551 clock-frequency = <48000000>;
553 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
554 dma-names = "tx", "rx";
557 uart2: serial@4806c000 {
558 compatible = "ti,dra742-uart", "ti,omap4-uart";
559 reg = <0x4806c000 0x100>;
560 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
562 clock-frequency = <48000000>;
564 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
565 dma-names = "tx", "rx";
568 uart3: serial@48020000 {
569 compatible = "ti,dra742-uart", "ti,omap4-uart";
570 reg = <0x48020000 0x100>;
571 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
573 clock-frequency = <48000000>;
575 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
576 dma-names = "tx", "rx";
579 uart4: serial@4806e000 {
580 compatible = "ti,dra742-uart", "ti,omap4-uart";
581 reg = <0x4806e000 0x100>;
582 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
584 clock-frequency = <48000000>;
586 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
587 dma-names = "tx", "rx";
590 uart5: serial@48066000 {
591 compatible = "ti,dra742-uart", "ti,omap4-uart";
592 reg = <0x48066000 0x100>;
593 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
595 clock-frequency = <48000000>;
597 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
598 dma-names = "tx", "rx";
601 uart6: serial@48068000 {
602 compatible = "ti,dra742-uart", "ti,omap4-uart";
603 reg = <0x48068000 0x100>;
604 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
606 clock-frequency = <48000000>;
608 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
609 dma-names = "tx", "rx";
612 uart7: serial@48420000 {
613 compatible = "ti,dra742-uart", "ti,omap4-uart";
614 reg = <0x48420000 0x100>;
615 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
617 clock-frequency = <48000000>;
621 uart8: serial@48422000 {
622 compatible = "ti,dra742-uart", "ti,omap4-uart";
623 reg = <0x48422000 0x100>;
624 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
626 clock-frequency = <48000000>;
630 uart9: serial@48424000 {
631 compatible = "ti,dra742-uart", "ti,omap4-uart";
632 reg = <0x48424000 0x100>;
633 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
635 clock-frequency = <48000000>;
639 uart10: serial@4ae2b000 {
640 compatible = "ti,dra742-uart", "ti,omap4-uart";
641 reg = <0x4ae2b000 0x100>;
642 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
643 ti,hwmods = "uart10";
644 clock-frequency = <48000000>;
648 mailbox1: mailbox@4a0f4000 {
649 compatible = "ti,omap4-mailbox";
650 reg = <0x4a0f4000 0x200>;
651 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
654 ti,hwmods = "mailbox1";
656 ti,mbox-num-users = <3>;
657 ti,mbox-num-fifos = <8>;
661 mailbox2: mailbox@4883a000 {
662 compatible = "ti,omap4-mailbox";
663 reg = <0x4883a000 0x200>;
664 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
668 ti,hwmods = "mailbox2";
670 ti,mbox-num-users = <4>;
671 ti,mbox-num-fifos = <12>;
675 mailbox3: mailbox@4883c000 {
676 compatible = "ti,omap4-mailbox";
677 reg = <0x4883c000 0x200>;
678 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
682 ti,hwmods = "mailbox3";
684 ti,mbox-num-users = <4>;
685 ti,mbox-num-fifos = <12>;
689 mailbox4: mailbox@4883e000 {
690 compatible = "ti,omap4-mailbox";
691 reg = <0x4883e000 0x200>;
692 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
696 ti,hwmods = "mailbox4";
698 ti,mbox-num-users = <4>;
699 ti,mbox-num-fifos = <12>;
703 mailbox5: mailbox@48840000 {
704 compatible = "ti,omap4-mailbox";
705 reg = <0x48840000 0x200>;
706 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
710 ti,hwmods = "mailbox5";
712 ti,mbox-num-users = <4>;
713 ti,mbox-num-fifos = <12>;
717 mailbox6: mailbox@48842000 {
718 compatible = "ti,omap4-mailbox";
719 reg = <0x48842000 0x200>;
720 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
724 ti,hwmods = "mailbox6";
726 ti,mbox-num-users = <4>;
727 ti,mbox-num-fifos = <12>;
731 mailbox7: mailbox@48844000 {
732 compatible = "ti,omap4-mailbox";
733 reg = <0x48844000 0x200>;
734 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
738 ti,hwmods = "mailbox7";
740 ti,mbox-num-users = <4>;
741 ti,mbox-num-fifos = <12>;
745 mailbox8: mailbox@48846000 {
746 compatible = "ti,omap4-mailbox";
747 reg = <0x48846000 0x200>;
748 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
752 ti,hwmods = "mailbox8";
754 ti,mbox-num-users = <4>;
755 ti,mbox-num-fifos = <12>;
759 mailbox9: mailbox@4885e000 {
760 compatible = "ti,omap4-mailbox";
761 reg = <0x4885e000 0x200>;
762 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
766 ti,hwmods = "mailbox9";
768 ti,mbox-num-users = <4>;
769 ti,mbox-num-fifos = <12>;
773 mailbox10: mailbox@48860000 {
774 compatible = "ti,omap4-mailbox";
775 reg = <0x48860000 0x200>;
776 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
780 ti,hwmods = "mailbox10";
782 ti,mbox-num-users = <4>;
783 ti,mbox-num-fifos = <12>;
787 mailbox11: mailbox@48862000 {
788 compatible = "ti,omap4-mailbox";
789 reg = <0x48862000 0x200>;
790 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
794 ti,hwmods = "mailbox11";
796 ti,mbox-num-users = <4>;
797 ti,mbox-num-fifos = <12>;
801 mailbox12: mailbox@48864000 {
802 compatible = "ti,omap4-mailbox";
803 reg = <0x48864000 0x200>;
804 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
808 ti,hwmods = "mailbox12";
810 ti,mbox-num-users = <4>;
811 ti,mbox-num-fifos = <12>;
815 mailbox13: mailbox@48802000 {
816 compatible = "ti,omap4-mailbox";
817 reg = <0x48802000 0x200>;
818 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
819 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
822 ti,hwmods = "mailbox13";
824 ti,mbox-num-users = <4>;
825 ti,mbox-num-fifos = <12>;
829 timer1: timer@4ae18000 {
830 compatible = "ti,omap5430-timer";
831 reg = <0x4ae18000 0x80>;
832 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
833 ti,hwmods = "timer1";
837 timer2: timer@48032000 {
838 compatible = "ti,omap5430-timer";
839 reg = <0x48032000 0x80>;
840 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
841 ti,hwmods = "timer2";
844 timer3: timer@48034000 {
845 compatible = "ti,omap5430-timer";
846 reg = <0x48034000 0x80>;
847 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
848 ti,hwmods = "timer3";
851 timer4: timer@48036000 {
852 compatible = "ti,omap5430-timer";
853 reg = <0x48036000 0x80>;
854 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
855 ti,hwmods = "timer4";
858 timer5: timer@48820000 {
859 compatible = "ti,omap5430-timer";
860 reg = <0x48820000 0x80>;
861 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
862 ti,hwmods = "timer5";
865 timer6: timer@48822000 {
866 compatible = "ti,omap5430-timer";
867 reg = <0x48822000 0x80>;
868 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
869 ti,hwmods = "timer6";
872 timer7: timer@48824000 {
873 compatible = "ti,omap5430-timer";
874 reg = <0x48824000 0x80>;
875 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
876 ti,hwmods = "timer7";
879 timer8: timer@48826000 {
880 compatible = "ti,omap5430-timer";
881 reg = <0x48826000 0x80>;
882 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
883 ti,hwmods = "timer8";
886 timer9: timer@4803e000 {
887 compatible = "ti,omap5430-timer";
888 reg = <0x4803e000 0x80>;
889 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
890 ti,hwmods = "timer9";
893 timer10: timer@48086000 {
894 compatible = "ti,omap5430-timer";
895 reg = <0x48086000 0x80>;
896 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
897 ti,hwmods = "timer10";
900 timer11: timer@48088000 {
901 compatible = "ti,omap5430-timer";
902 reg = <0x48088000 0x80>;
903 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
904 ti,hwmods = "timer11";
907 timer12: timer@4ae20000 {
908 compatible = "ti,omap5430-timer";
909 reg = <0x4ae20000 0x80>;
910 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
911 ti,hwmods = "timer12";
916 timer13: timer@48828000 {
917 compatible = "ti,omap5430-timer";
918 reg = <0x48828000 0x80>;
919 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
920 ti,hwmods = "timer13";
923 timer14: timer@4882a000 {
924 compatible = "ti,omap5430-timer";
925 reg = <0x4882a000 0x80>;
926 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
927 ti,hwmods = "timer14";
930 timer15: timer@4882c000 {
931 compatible = "ti,omap5430-timer";
932 reg = <0x4882c000 0x80>;
933 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
934 ti,hwmods = "timer15";
937 timer16: timer@4882e000 {
938 compatible = "ti,omap5430-timer";
939 reg = <0x4882e000 0x80>;
940 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
941 ti,hwmods = "timer16";
945 compatible = "ti,omap3-wdt";
946 reg = <0x4ae14000 0x80>;
947 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
948 ti,hwmods = "wd_timer2";
951 hwspinlock: spinlock@4a0f6000 {
952 compatible = "ti,omap4-hwspinlock";
953 reg = <0x4a0f6000 0x1000>;
954 ti,hwmods = "spinlock";
959 compatible = "ti,omap5-dmm";
960 reg = <0x4e000000 0x800>;
961 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
966 compatible = "ti,omap4-i2c";
967 reg = <0x48070000 0x100>;
968 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
969 #address-cells = <1>;
976 compatible = "ti,omap4-i2c";
977 reg = <0x48072000 0x100>;
978 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
979 #address-cells = <1>;
986 compatible = "ti,omap4-i2c";
987 reg = <0x48060000 0x100>;
988 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
989 #address-cells = <1>;
996 compatible = "ti,omap4-i2c";
997 reg = <0x4807a000 0x100>;
998 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
999 #address-cells = <1>;
1002 status = "disabled";
1005 i2c5: i2c@4807c000 {
1006 compatible = "ti,omap4-i2c";
1007 reg = <0x4807c000 0x100>;
1008 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1009 #address-cells = <1>;
1012 status = "disabled";
1015 mmc1: mmc@4809c000 {
1016 compatible = "ti,omap4-hsmmc";
1017 reg = <0x4809c000 0x400>;
1018 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1021 ti,needs-special-reset;
1022 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
1023 dma-names = "tx", "rx";
1024 status = "disabled";
1025 pbias-supply = <&pbias_mmc_reg>;
1028 mmc2: mmc@480b4000 {
1029 compatible = "ti,omap4-hsmmc";
1030 reg = <0x480b4000 0x400>;
1031 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1033 ti,needs-special-reset;
1034 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
1035 dma-names = "tx", "rx";
1036 status = "disabled";
1039 mmc3: mmc@480ad000 {
1040 compatible = "ti,omap4-hsmmc";
1041 reg = <0x480ad000 0x400>;
1042 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1044 ti,needs-special-reset;
1045 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
1046 dma-names = "tx", "rx";
1047 status = "disabled";
1050 mmc4: mmc@480d1000 {
1051 compatible = "ti,omap4-hsmmc";
1052 reg = <0x480d1000 0x400>;
1053 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1055 ti,needs-special-reset;
1056 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
1057 dma-names = "tx", "rx";
1058 status = "disabled";
1061 mmu0_dsp1: mmu@40d01000 {
1062 compatible = "ti,dra7-dsp-iommu";
1063 reg = <0x40d01000 0x100>;
1064 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1065 ti,hwmods = "mmu0_dsp1";
1067 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1068 status = "disabled";
1071 mmu1_dsp1: mmu@40d02000 {
1072 compatible = "ti,dra7-dsp-iommu";
1073 reg = <0x40d02000 0x100>;
1074 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1075 ti,hwmods = "mmu1_dsp1";
1077 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1078 status = "disabled";
1081 mmu_ipu1: mmu@58882000 {
1082 compatible = "ti,dra7-iommu";
1083 reg = <0x58882000 0x100>;
1084 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1085 ti,hwmods = "mmu_ipu1";
1087 ti,iommu-bus-err-back;
1088 status = "disabled";
1091 mmu_ipu2: mmu@55082000 {
1092 compatible = "ti,dra7-iommu";
1093 reg = <0x55082000 0x100>;
1094 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1095 ti,hwmods = "mmu_ipu2";
1097 ti,iommu-bus-err-back;
1098 status = "disabled";
1101 abb_mpu: regulator-abb-mpu {
1102 compatible = "ti,abb-v3";
1103 regulator-name = "abb_mpu";
1104 #address-cells = <0>;
1106 clocks = <&sys_clkin1>;
1107 ti,settling-time = <50>;
1108 ti,clock-cycles = <16>;
1110 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1111 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1113 reg-names = "setup-address", "control-address",
1114 "int-address", "efuse-address",
1116 ti,tranxdone-status-mask = <0x80>;
1117 /* LDOVBBMPU_FBB_MUX_CTRL */
1118 ti,ldovbb-override-mask = <0x400>;
1119 /* LDOVBBMPU_FBB_VSET_OUT */
1120 ti,ldovbb-vset-mask = <0x1F>;
1123 * NOTE: only FBB mode used but actual vset will
1124 * determine final biasing
1127 /*uV ABB efuse rbb_m fbb_m vset_m*/
1128 1060000 0 0x0 0 0x02000000 0x01F00000
1129 1160000 0 0x4 0 0x02000000 0x01F00000
1130 1210000 0 0x8 0 0x02000000 0x01F00000
1134 abb_ivahd: regulator-abb-ivahd {
1135 compatible = "ti,abb-v3";
1136 regulator-name = "abb_ivahd";
1137 #address-cells = <0>;
1139 clocks = <&sys_clkin1>;
1140 ti,settling-time = <50>;
1141 ti,clock-cycles = <16>;
1143 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1144 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1146 reg-names = "setup-address", "control-address",
1147 "int-address", "efuse-address",
1149 ti,tranxdone-status-mask = <0x40000000>;
1150 /* LDOVBBIVA_FBB_MUX_CTRL */
1151 ti,ldovbb-override-mask = <0x400>;
1152 /* LDOVBBIVA_FBB_VSET_OUT */
1153 ti,ldovbb-vset-mask = <0x1F>;
1156 * NOTE: only FBB mode used but actual vset will
1157 * determine final biasing
1160 /*uV ABB efuse rbb_m fbb_m vset_m*/
1161 1055000 0 0x0 0 0x02000000 0x01F00000
1162 1150000 0 0x4 0 0x02000000 0x01F00000
1163 1250000 0 0x8 0 0x02000000 0x01F00000
1167 abb_dspeve: regulator-abb-dspeve {
1168 compatible = "ti,abb-v3";
1169 regulator-name = "abb_dspeve";
1170 #address-cells = <0>;
1172 clocks = <&sys_clkin1>;
1173 ti,settling-time = <50>;
1174 ti,clock-cycles = <16>;
1176 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1177 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1179 reg-names = "setup-address", "control-address",
1180 "int-address", "efuse-address",
1182 ti,tranxdone-status-mask = <0x20000000>;
1183 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1184 ti,ldovbb-override-mask = <0x400>;
1185 /* LDOVBBDSPEVE_FBB_VSET_OUT */
1186 ti,ldovbb-vset-mask = <0x1F>;
1189 * NOTE: only FBB mode used but actual vset will
1190 * determine final biasing
1193 /*uV ABB efuse rbb_m fbb_m vset_m*/
1194 1055000 0 0x0 0 0x02000000 0x01F00000
1195 1150000 0 0x4 0 0x02000000 0x01F00000
1196 1250000 0 0x8 0 0x02000000 0x01F00000
1200 abb_gpu: regulator-abb-gpu {
1201 compatible = "ti,abb-v3";
1202 regulator-name = "abb_gpu";
1203 #address-cells = <0>;
1205 clocks = <&sys_clkin1>;
1206 ti,settling-time = <50>;
1207 ti,clock-cycles = <16>;
1209 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1210 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1212 reg-names = "setup-address", "control-address",
1213 "int-address", "efuse-address",
1215 ti,tranxdone-status-mask = <0x10000000>;
1216 /* LDOVBBGPU_FBB_MUX_CTRL */
1217 ti,ldovbb-override-mask = <0x400>;
1218 /* LDOVBBGPU_FBB_VSET_OUT */
1219 ti,ldovbb-vset-mask = <0x1F>;
1222 * NOTE: only FBB mode used but actual vset will
1223 * determine final biasing
1226 /*uV ABB efuse rbb_m fbb_m vset_m*/
1227 1090000 0 0x0 0 0x02000000 0x01F00000
1228 1210000 0 0x4 0 0x02000000 0x01F00000
1229 1280000 0 0x8 0 0x02000000 0x01F00000
1233 mcspi1: spi@48098000 {
1234 compatible = "ti,omap4-mcspi";
1235 reg = <0x48098000 0x200>;
1236 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1237 #address-cells = <1>;
1239 ti,hwmods = "mcspi1";
1240 ti,spi-num-cs = <4>;
1241 dmas = <&sdma_xbar 35>,
1249 dma-names = "tx0", "rx0", "tx1", "rx1",
1250 "tx2", "rx2", "tx3", "rx3";
1251 status = "disabled";
1254 mcspi2: spi@4809a000 {
1255 compatible = "ti,omap4-mcspi";
1256 reg = <0x4809a000 0x200>;
1257 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1258 #address-cells = <1>;
1260 ti,hwmods = "mcspi2";
1261 ti,spi-num-cs = <2>;
1262 dmas = <&sdma_xbar 43>,
1266 dma-names = "tx0", "rx0", "tx1", "rx1";
1267 status = "disabled";
1270 mcspi3: spi@480b8000 {
1271 compatible = "ti,omap4-mcspi";
1272 reg = <0x480b8000 0x200>;
1273 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1274 #address-cells = <1>;
1276 ti,hwmods = "mcspi3";
1277 ti,spi-num-cs = <2>;
1278 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1279 dma-names = "tx0", "rx0";
1280 status = "disabled";
1283 mcspi4: spi@480ba000 {
1284 compatible = "ti,omap4-mcspi";
1285 reg = <0x480ba000 0x200>;
1286 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1287 #address-cells = <1>;
1289 ti,hwmods = "mcspi4";
1290 ti,spi-num-cs = <1>;
1291 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1292 dma-names = "tx0", "rx0";
1293 status = "disabled";
1296 qspi: qspi@4b300000 {
1297 compatible = "ti,dra7xxx-qspi";
1298 reg = <0x4b300000 0x100>,
1299 <0x5c000000 0x4000000>;
1300 reg-names = "qspi_base", "qspi_mmap";
1301 syscon-chipselects = <&scm_conf 0x558>;
1302 #address-cells = <1>;
1305 clocks = <&qspi_gfclk_div>;
1306 clock-names = "fck";
1308 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1309 status = "disabled";
1314 compatible = "ti,omap-ocp2scp";
1315 #address-cells = <1>;
1318 reg = <0x4a090000 0x20>;
1319 ti,hwmods = "ocp2scp3";
1320 sata_phy: phy@4A096000 {
1321 compatible = "ti,phy-pipe3-sata";
1322 reg = <0x4A096000 0x80>, /* phy_rx */
1323 <0x4A096400 0x64>, /* phy_tx */
1324 <0x4A096800 0x40>; /* pll_ctrl */
1325 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1326 syscon-phy-power = <&scm_conf 0x374>;
1327 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1328 clock-names = "sysclk", "refclk";
1329 syscon-pllreset = <&scm_conf 0x3fc>;
1333 pcie1_phy: pciephy@4a094000 {
1334 compatible = "ti,phy-pipe3-pcie";
1335 reg = <0x4a094000 0x80>, /* phy_rx */
1336 <0x4a094400 0x64>; /* phy_tx */
1337 reg-names = "phy_rx", "phy_tx";
1338 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1339 syscon-pcs = <&scm_conf_pcie 0x10>;
1340 clocks = <&dpll_pcie_ref_ck>,
1341 <&dpll_pcie_ref_m2ldo_ck>,
1342 <&optfclk_pciephy1_32khz>,
1343 <&optfclk_pciephy1_clk>,
1344 <&optfclk_pciephy1_div_clk>,
1345 <&optfclk_pciephy_div>,
1347 clock-names = "dpll_ref", "dpll_ref_m2",
1348 "wkupclk", "refclk",
1349 "div-clk", "phy-div", "sysclk";
1353 pcie2_phy: pciephy@4a095000 {
1354 compatible = "ti,phy-pipe3-pcie";
1355 reg = <0x4a095000 0x80>, /* phy_rx */
1356 <0x4a095400 0x64>; /* phy_tx */
1357 reg-names = "phy_rx", "phy_tx";
1358 syscon-phy-power = <&scm_conf_pcie 0x20>;
1359 syscon-pcs = <&scm_conf_pcie 0x10>;
1360 clocks = <&dpll_pcie_ref_ck>,
1361 <&dpll_pcie_ref_m2ldo_ck>,
1362 <&optfclk_pciephy2_32khz>,
1363 <&optfclk_pciephy2_clk>,
1364 <&optfclk_pciephy2_div_clk>,
1365 <&optfclk_pciephy_div>,
1367 clock-names = "dpll_ref", "dpll_ref_m2",
1368 "wkupclk", "refclk",
1369 "div-clk", "phy-div", "sysclk";
1371 status = "disabled";
1375 sata: sata@4a141100 {
1376 compatible = "snps,dwc-ahci";
1377 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1378 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1380 phy-names = "sata-phy";
1381 clocks = <&sata_ref_clk>;
1383 ports-implemented = <0x1>;
1387 compatible = "ti,am3352-rtc";
1388 reg = <0x48838000 0x100>;
1389 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1390 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1391 ti,hwmods = "rtcss";
1392 clocks = <&sys_32k_ck>;
1397 compatible = "ti,omap-ocp2scp";
1398 #address-cells = <1>;
1401 reg = <0x4a080000 0x20>;
1402 ti,hwmods = "ocp2scp1";
1404 usb2_phy1: phy@4a084000 {
1405 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
1406 reg = <0x4a084000 0x400>;
1407 syscon-phy-power = <&scm_conf 0x300>;
1408 clocks = <&usb_phy1_always_on_clk32k>,
1409 <&usb_otg_ss1_refclk960m>;
1410 clock-names = "wkupclk",
1415 usb2_phy2: phy@4a085000 {
1416 compatible = "ti,dra7x-usb2-phy2",
1418 reg = <0x4a085000 0x400>;
1419 syscon-phy-power = <&scm_conf 0xe74>;
1420 clocks = <&usb_phy2_always_on_clk32k>,
1421 <&usb_otg_ss2_refclk960m>;
1422 clock-names = "wkupclk",
1427 usb3_phy1: phy@4a084400 {
1428 compatible = "ti,omap-usb3";
1429 reg = <0x4a084400 0x80>,
1432 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1433 syscon-phy-power = <&scm_conf 0x370>;
1434 clocks = <&usb_phy3_always_on_clk32k>,
1436 <&usb_otg_ss1_refclk960m>;
1437 clock-names = "wkupclk",
1444 omap_dwc3_1: omap_dwc3_1@48880000 {
1445 compatible = "ti,dwc3";
1446 ti,hwmods = "usb_otg_ss1";
1447 reg = <0x48880000 0x10000>;
1448 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1449 #address-cells = <1>;
1453 usb1: usb@48890000 {
1454 compatible = "snps,dwc3";
1455 reg = <0x48890000 0x17000>;
1456 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1457 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1458 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1459 interrupt-names = "peripheral",
1462 phys = <&usb2_phy1>, <&usb3_phy1>;
1463 phy-names = "usb2-phy", "usb3-phy";
1464 maximum-speed = "super-speed";
1466 snps,dis_u3_susphy_quirk;
1467 snps,dis_u2_susphy_quirk;
1471 omap_dwc3_2: omap_dwc3_2@488c0000 {
1472 compatible = "ti,dwc3";
1473 ti,hwmods = "usb_otg_ss2";
1474 reg = <0x488c0000 0x10000>;
1475 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1476 #address-cells = <1>;
1480 usb2: usb@488d0000 {
1481 compatible = "snps,dwc3";
1482 reg = <0x488d0000 0x17000>;
1483 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1484 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1485 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1486 interrupt-names = "peripheral",
1489 phys = <&usb2_phy2>;
1490 phy-names = "usb2-phy";
1491 maximum-speed = "high-speed";
1493 snps,dis_u3_susphy_quirk;
1494 snps,dis_u2_susphy_quirk;
1498 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1499 omap_dwc3_3: omap_dwc3_3@48900000 {
1500 compatible = "ti,dwc3";
1501 ti,hwmods = "usb_otg_ss3";
1502 reg = <0x48900000 0x10000>;
1503 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1504 #address-cells = <1>;
1508 status = "disabled";
1509 usb3: usb@48910000 {
1510 compatible = "snps,dwc3";
1511 reg = <0x48910000 0x17000>;
1512 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1513 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1514 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1515 interrupt-names = "peripheral",
1518 maximum-speed = "high-speed";
1520 snps,dis_u3_susphy_quirk;
1521 snps,dis_u2_susphy_quirk;
1526 compatible = "ti,am3352-elm";
1527 reg = <0x48078000 0xfc0>; /* device IO registers */
1528 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1530 status = "disabled";
1533 gpmc: gpmc@50000000 {
1534 compatible = "ti,am3352-gpmc";
1536 reg = <0x50000000 0x37c>; /* device IO registers */
1537 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1538 dmas = <&edma_xbar 4 0>;
1541 gpmc,num-waitpins = <2>;
1542 #address-cells = <2>;
1544 interrupt-controller;
1545 #interrupt-cells = <2>;
1548 status = "disabled";
1552 compatible = "ti,dra7-atl";
1553 reg = <0x4843c000 0x3ff>;
1555 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1556 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1557 clocks = <&atl_gfclk_mux>;
1558 clock-names = "fck";
1559 status = "disabled";
1562 mcasp1: mcasp@48460000 {
1563 compatible = "ti,dra7-mcasp-audio";
1564 ti,hwmods = "mcasp1";
1565 reg = <0x48460000 0x2000>,
1566 <0x45800000 0x1000>;
1567 reg-names = "mpu","dat";
1568 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1569 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1570 interrupt-names = "tx", "rx";
1571 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1572 dma-names = "tx", "rx";
1573 clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
1574 <&mcasp1_ahclkr_mux>;
1575 clock-names = "fck", "ahclkx", "ahclkr";
1576 status = "disabled";
1579 mcasp2: mcasp@48464000 {
1580 compatible = "ti,dra7-mcasp-audio";
1581 ti,hwmods = "mcasp2";
1582 reg = <0x48464000 0x2000>,
1583 <0x45c00000 0x1000>;
1584 reg-names = "mpu","dat";
1585 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1586 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1587 interrupt-names = "tx", "rx";
1588 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1589 dma-names = "tx", "rx";
1590 clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
1591 <&mcasp2_ahclkr_mux>;
1592 clock-names = "fck", "ahclkx", "ahclkr";
1593 status = "disabled";
1596 mcasp3: mcasp@48468000 {
1597 compatible = "ti,dra7-mcasp-audio";
1598 ti,hwmods = "mcasp3";
1599 reg = <0x48468000 0x2000>,
1600 <0x46000000 0x1000>;
1601 reg-names = "mpu","dat";
1602 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1603 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1604 interrupt-names = "tx", "rx";
1605 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1606 dma-names = "tx", "rx";
1607 clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
1608 clock-names = "fck", "ahclkx";
1609 status = "disabled";
1612 mcasp4: mcasp@4846c000 {
1613 compatible = "ti,dra7-mcasp-audio";
1614 ti,hwmods = "mcasp4";
1615 reg = <0x4846c000 0x2000>,
1616 <0x48436000 0x1000>;
1617 reg-names = "mpu","dat";
1618 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1619 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1620 interrupt-names = "tx", "rx";
1621 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1622 dma-names = "tx", "rx";
1623 clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
1624 clock-names = "fck", "ahclkx";
1625 status = "disabled";
1628 mcasp5: mcasp@48470000 {
1629 compatible = "ti,dra7-mcasp-audio";
1630 ti,hwmods = "mcasp5";
1631 reg = <0x48470000 0x2000>,
1632 <0x4843a000 0x1000>;
1633 reg-names = "mpu","dat";
1634 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1635 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1636 interrupt-names = "tx", "rx";
1637 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1638 dma-names = "tx", "rx";
1639 clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
1640 clock-names = "fck", "ahclkx";
1641 status = "disabled";
1644 mcasp6: mcasp@48474000 {
1645 compatible = "ti,dra7-mcasp-audio";
1646 ti,hwmods = "mcasp6";
1647 reg = <0x48474000 0x2000>,
1648 <0x4844c000 0x1000>;
1649 reg-names = "mpu","dat";
1650 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1651 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1652 interrupt-names = "tx", "rx";
1653 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1654 dma-names = "tx", "rx";
1655 clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
1656 clock-names = "fck", "ahclkx";
1657 status = "disabled";
1660 mcasp7: mcasp@48478000 {
1661 compatible = "ti,dra7-mcasp-audio";
1662 ti,hwmods = "mcasp7";
1663 reg = <0x48478000 0x2000>,
1664 <0x48450000 0x1000>;
1665 reg-names = "mpu","dat";
1666 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1667 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1668 interrupt-names = "tx", "rx";
1669 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1670 dma-names = "tx", "rx";
1671 clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
1672 clock-names = "fck", "ahclkx";
1673 status = "disabled";
1676 mcasp8: mcasp@4847c000 {
1677 compatible = "ti,dra7-mcasp-audio";
1678 ti,hwmods = "mcasp8";
1679 reg = <0x4847c000 0x2000>,
1680 <0x48454000 0x1000>;
1681 reg-names = "mpu","dat";
1682 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1683 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1684 interrupt-names = "tx", "rx";
1685 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1686 dma-names = "tx", "rx";
1687 clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
1688 clock-names = "fck", "ahclkx";
1689 status = "disabled";
1692 crossbar_mpu: crossbar@4a002a48 {
1693 compatible = "ti,irq-crossbar";
1694 reg = <0x4a002a48 0x130>;
1695 interrupt-controller;
1696 interrupt-parent = <&wakeupgen>;
1697 #interrupt-cells = <3>;
1698 ti,max-irqs = <160>;
1699 ti,max-crossbar-sources = <MAX_SOURCES>;
1701 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1702 ti,irqs-skip = <10 133 139 140>;
1703 ti,irqs-safe-map = <0>;
1706 mac: ethernet@48484000 {
1707 compatible = "ti,dra7-cpsw","ti,cpsw";
1709 clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
1710 clock-names = "fck", "cpts";
1711 cpdma_channels = <8>;
1712 ale_entries = <1024>;
1713 bd_ram_size = <0x2000>;
1714 mac_control = <0x20>;
1717 cpts_clock_mult = <0x784CFE14>;
1718 cpts_clock_shift = <29>;
1719 reg = <0x48484000 0x1000
1721 #address-cells = <1>;
1725 * Do not allow gating of cpsw clock as workaround
1726 * for errata i877. Keeping internal clock disabled
1727 * causes the device switching characteristics
1728 * to degrade over time and eventually fail to meet
1729 * the data manual delay time/skew specs.
1739 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1744 syscon = <&scm_conf>;
1745 status = "disabled";
1747 davinci_mdio: mdio@48485000 {
1748 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1749 #address-cells = <1>;
1751 ti,hwmods = "davinci_mdio";
1752 bus_freq = <1000000>;
1753 reg = <0x48485000 0x100>;
1756 cpsw_emac0: slave@48480200 {
1757 /* Filled in by U-Boot */
1758 mac-address = [ 00 00 00 00 00 00 ];
1761 cpsw_emac1: slave@48480300 {
1762 /* Filled in by U-Boot */
1763 mac-address = [ 00 00 00 00 00 00 ];
1766 phy_sel: cpsw-phy-sel@4a002554 {
1767 compatible = "ti,dra7xx-cpsw-phy-sel";
1768 reg= <0x4a002554 0x4>;
1769 reg-names = "gmii-sel";
1773 dcan1: can@481cc000 {
1774 compatible = "ti,dra7-d_can";
1775 ti,hwmods = "dcan1";
1776 reg = <0x4ae3c000 0x2000>;
1777 syscon-raminit = <&scm_conf 0x558 0>;
1778 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1779 clocks = <&dcan1_sys_clk_mux>;
1780 status = "disabled";
1783 dcan2: can@481d0000 {
1784 compatible = "ti,dra7-d_can";
1785 ti,hwmods = "dcan2";
1786 reg = <0x48480000 0x2000>;
1787 syscon-raminit = <&scm_conf 0x558 1>;
1788 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1789 clocks = <&sys_clkin1>;
1790 status = "disabled";
1794 compatible = "ti,dra7-dss";
1795 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1796 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1797 status = "disabled";
1798 ti,hwmods = "dss_core";
1799 /* CTRL_CORE_DSS_PLL_CONTROL */
1800 syscon-pll-ctrl = <&scm_conf 0x538>;
1801 #address-cells = <1>;
1806 compatible = "ti,dra7-dispc";
1807 reg = <0x58001000 0x1000>;
1808 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1809 ti,hwmods = "dss_dispc";
1810 clocks = <&dss_dss_clk>;
1811 clock-names = "fck";
1812 /* CTRL_CORE_SMA_SW_1 */
1813 syscon-pol = <&scm_conf 0x534>;
1816 hdmi: encoder@58060000 {
1817 compatible = "ti,dra7-hdmi";
1818 reg = <0x58040000 0x200>,
1821 <0x58060000 0x19000>;
1822 reg-names = "wp", "pll", "phy", "core";
1823 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1824 status = "disabled";
1825 ti,hwmods = "dss_hdmi";
1826 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1827 clock-names = "fck", "sys_clk";
1831 epwmss0: epwmss@4843e000 {
1832 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1833 reg = <0x4843e000 0x30>;
1834 ti,hwmods = "epwmss0";
1835 #address-cells = <1>;
1837 status = "disabled";
1840 ehrpwm0: pwm@4843e200 {
1841 compatible = "ti,dra746-ehrpwm",
1844 reg = <0x4843e200 0x80>;
1845 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1846 clock-names = "tbclk", "fck";
1847 status = "disabled";
1850 ecap0: ecap@4843e100 {
1851 compatible = "ti,dra746-ecap",
1854 reg = <0x4843e100 0x80>;
1855 clocks = <&l4_root_clk_div>;
1856 clock-names = "fck";
1857 status = "disabled";
1861 epwmss1: epwmss@48440000 {
1862 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1863 reg = <0x48440000 0x30>;
1864 ti,hwmods = "epwmss1";
1865 #address-cells = <1>;
1867 status = "disabled";
1870 ehrpwm1: pwm@48440200 {
1871 compatible = "ti,dra746-ehrpwm",
1874 reg = <0x48440200 0x80>;
1875 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
1876 clock-names = "tbclk", "fck";
1877 status = "disabled";
1880 ecap1: ecap@48440100 {
1881 compatible = "ti,dra746-ecap",
1884 reg = <0x48440100 0x80>;
1885 clocks = <&l4_root_clk_div>;
1886 clock-names = "fck";
1887 status = "disabled";
1891 epwmss2: epwmss@48442000 {
1892 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1893 reg = <0x48442000 0x30>;
1894 ti,hwmods = "epwmss2";
1895 #address-cells = <1>;
1897 status = "disabled";
1900 ehrpwm2: pwm@48442200 {
1901 compatible = "ti,dra746-ehrpwm",
1904 reg = <0x48442200 0x80>;
1905 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
1906 clock-names = "tbclk", "fck";
1907 status = "disabled";
1910 ecap2: ecap@48442100 {
1911 compatible = "ti,dra746-ecap",
1914 reg = <0x48442100 0x80>;
1915 clocks = <&l4_root_clk_div>;
1916 clock-names = "fck";
1917 status = "disabled";
1921 aes1: aes@4b500000 {
1922 compatible = "ti,omap4-aes";
1924 reg = <0x4b500000 0xa0>;
1925 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1926 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
1927 dma-names = "tx", "rx";
1928 clocks = <&l3_iclk_div>;
1929 clock-names = "fck";
1932 aes2: aes@4b700000 {
1933 compatible = "ti,omap4-aes";
1935 reg = <0x4b700000 0xa0>;
1936 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1937 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1938 dma-names = "tx", "rx";
1939 clocks = <&l3_iclk_div>;
1940 clock-names = "fck";
1944 compatible = "ti,omap4-des";
1946 reg = <0x480a5000 0xa0>;
1947 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1948 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
1949 dma-names = "tx", "rx";
1950 clocks = <&l3_iclk_div>;
1951 clock-names = "fck";
1954 sham: sham@53100000 {
1955 compatible = "ti,omap5-sham";
1957 reg = <0x4b101000 0x300>;
1958 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1959 dmas = <&edma_xbar 119 0>;
1961 clocks = <&l3_iclk_div>;
1962 clock-names = "fck";
1966 compatible = "ti,omap4-rng";
1968 reg = <0x48090000 0x2000>;
1969 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1970 clocks = <&l3_iclk_div>;
1971 clock-names = "fck";
1975 thermal_zones: thermal-zones {
1976 #include "omap4-cpu-thermal.dtsi"
1977 #include "omap5-gpu-thermal.dtsi"
1978 #include "omap5-core-thermal.dtsi"
1979 #include "dra7-dspeve-thermal.dtsi"
1980 #include "dra7-iva-thermal.dtsi"
1986 polling-delay = <500>; /* milliseconds */
1989 /include/ "dra7xx-clocks.dtsi"