2 * Copyright 2012 Sascha Hauer, Pengutronix
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include "imx27-pinfunc.h"
14 #include <dt-bindings/clock/imx27-clock.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
23 * The decompressor and also some bootloaders rely on a
24 * pre-existing /chosen node to be available to insert the
25 * command line and merge other ATAGS info.
26 * Also for U-Boot there must be a pre-existing /memory node.
29 memory { device_type = "memory"; reg = <0 0>; };
52 aitc: aitc-interrupt-controller@e0000000 {
53 compatible = "fsl,imx27-aitc", "fsl,avic";
55 #interrupt-cells = <1>;
56 reg = <0x10040000 0x1000>;
64 compatible = "fsl,imx-osc26m", "fixed-clock";
66 clock-frequency = <26000000>;
76 compatible = "arm,arm926ej-s";
82 clock-latency = <62500>;
83 clocks = <&clks IMX27_CLK_CPU_DIV>;
84 voltage-tolerance = <5>;
91 compatible = "simple-bus";
92 interrupt-parent = <&aitc>;
95 aipi@10000000 { /* AIPI1 */
96 compatible = "fsl,aipi-bus", "simple-bus";
99 reg = <0x10000000 0x20000>;
103 compatible = "fsl,imx27-dma";
104 reg = <0x10001000 0x1000>;
106 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
107 <&clks IMX27_CLK_DMA_AHB_GATE>;
108 clock-names = "ipg", "ahb";
110 #dma-channels = <16>;
113 wdog: wdog@10002000 {
114 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
115 reg = <0x10002000 0x1000>;
117 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
120 gpt1: timer@10003000 {
121 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
122 reg = <0x10003000 0x1000>;
124 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
125 <&clks IMX27_CLK_PER1_GATE>;
126 clock-names = "ipg", "per";
129 gpt2: timer@10004000 {
130 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
131 reg = <0x10004000 0x1000>;
133 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
134 <&clks IMX27_CLK_PER1_GATE>;
135 clock-names = "ipg", "per";
138 gpt3: timer@10005000 {
139 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
140 reg = <0x10005000 0x1000>;
142 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
143 <&clks IMX27_CLK_PER1_GATE>;
144 clock-names = "ipg", "per";
149 compatible = "fsl,imx27-pwm";
150 reg = <0x10006000 0x1000>;
152 clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
153 <&clks IMX27_CLK_PER1_GATE>;
154 clock-names = "ipg", "per";
158 compatible = "fsl,imx21-rtc";
159 reg = <0x10007000 0x1000>;
161 clocks = <&clks IMX27_CLK_CKIL>,
162 <&clks IMX27_CLK_RTC_IPG_GATE>;
163 clock-names = "ref", "ipg";
167 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
168 reg = <0x10008000 0x1000>;
170 clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
174 owire: owire@10009000 {
175 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
176 reg = <0x10009000 0x1000>;
177 clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
181 uart1: serial@1000a000 {
182 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
183 reg = <0x1000a000 0x1000>;
185 clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
186 <&clks IMX27_CLK_PER1_GATE>;
187 clock-names = "ipg", "per";
191 uart2: serial@1000b000 {
192 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
193 reg = <0x1000b000 0x1000>;
195 clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
196 <&clks IMX27_CLK_PER1_GATE>;
197 clock-names = "ipg", "per";
201 uart3: serial@1000c000 {
202 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
203 reg = <0x1000c000 0x1000>;
205 clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
206 <&clks IMX27_CLK_PER1_GATE>;
207 clock-names = "ipg", "per";
211 uart4: serial@1000d000 {
212 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
213 reg = <0x1000d000 0x1000>;
215 clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
216 <&clks IMX27_CLK_PER1_GATE>;
217 clock-names = "ipg", "per";
221 cspi1: cspi@1000e000 {
222 #address-cells = <1>;
224 compatible = "fsl,imx27-cspi";
225 reg = <0x1000e000 0x1000>;
227 clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
228 <&clks IMX27_CLK_PER2_GATE>;
229 clock-names = "ipg", "per";
233 cspi2: cspi@1000f000 {
234 #address-cells = <1>;
236 compatible = "fsl,imx27-cspi";
237 reg = <0x1000f000 0x1000>;
239 clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
240 <&clks IMX27_CLK_PER2_GATE>;
241 clock-names = "ipg", "per";
246 #sound-dai-cells = <0>;
247 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
248 reg = <0x10010000 0x1000>;
250 clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
251 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
252 dma-names = "rx0", "tx0", "rx1", "tx1";
253 fsl,fifo-depth = <8>;
258 #sound-dai-cells = <0>;
259 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
260 reg = <0x10011000 0x1000>;
262 clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
263 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
264 dma-names = "rx0", "tx0", "rx1", "tx1";
265 fsl,fifo-depth = <8>;
270 #address-cells = <1>;
272 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
273 reg = <0x10012000 0x1000>;
275 clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
279 sdhci1: sdhci@10013000 {
280 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
281 reg = <0x10013000 0x1000>;
283 clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
284 <&clks IMX27_CLK_PER2_GATE>;
285 clock-names = "ipg", "per";
291 sdhci2: sdhci@10014000 {
292 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
293 reg = <0x10014000 0x1000>;
295 clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
296 <&clks IMX27_CLK_PER2_GATE>;
297 clock-names = "ipg", "per";
303 iomuxc: iomuxc@10015000 {
304 compatible = "fsl,imx27-iomuxc";
305 reg = <0x10015000 0x600>;
306 #address-cells = <1>;
310 gpio1: gpio@10015000 {
311 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
312 reg = <0x10015000 0x100>;
313 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
317 interrupt-controller;
318 #interrupt-cells = <2>;
321 gpio2: gpio@10015100 {
322 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
323 reg = <0x10015100 0x100>;
324 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
332 gpio3: gpio@10015200 {
333 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
334 reg = <0x10015200 0x100>;
335 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
339 interrupt-controller;
340 #interrupt-cells = <2>;
343 gpio4: gpio@10015300 {
344 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
345 reg = <0x10015300 0x100>;
346 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
354 gpio5: gpio@10015400 {
355 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
356 reg = <0x10015400 0x100>;
357 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
361 interrupt-controller;
362 #interrupt-cells = <2>;
365 gpio6: gpio@10015500 {
366 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
367 reg = <0x10015500 0x100>;
368 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
372 interrupt-controller;
373 #interrupt-cells = <2>;
377 audmux: audmux@10016000 {
378 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
379 reg = <0x10016000 0x1000>;
380 clocks = <&clks IMX27_CLK_DUMMY>;
381 clock-names = "audmux";
385 cspi3: cspi@10017000 {
386 #address-cells = <1>;
388 compatible = "fsl,imx27-cspi";
389 reg = <0x10017000 0x1000>;
391 clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
392 <&clks IMX27_CLK_PER2_GATE>;
393 clock-names = "ipg", "per";
397 gpt4: timer@10019000 {
398 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
399 reg = <0x10019000 0x1000>;
401 clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
402 <&clks IMX27_CLK_PER1_GATE>;
403 clock-names = "ipg", "per";
406 gpt5: timer@1001a000 {
407 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
408 reg = <0x1001a000 0x1000>;
410 clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
411 <&clks IMX27_CLK_PER1_GATE>;
412 clock-names = "ipg", "per";
415 uart5: serial@1001b000 {
416 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
417 reg = <0x1001b000 0x1000>;
419 clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
420 <&clks IMX27_CLK_PER1_GATE>;
421 clock-names = "ipg", "per";
425 uart6: serial@1001c000 {
426 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
427 reg = <0x1001c000 0x1000>;
429 clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
430 <&clks IMX27_CLK_PER1_GATE>;
431 clock-names = "ipg", "per";
436 #address-cells = <1>;
438 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
439 reg = <0x1001d000 0x1000>;
441 clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
445 sdhci3: sdhci@1001e000 {
446 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
447 reg = <0x1001e000 0x1000>;
449 clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
450 <&clks IMX27_CLK_PER2_GATE>;
451 clock-names = "ipg", "per";
457 gpt6: timer@1001f000 {
458 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
459 reg = <0x1001f000 0x1000>;
461 clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
462 <&clks IMX27_CLK_PER1_GATE>;
463 clock-names = "ipg", "per";
467 aipi@10020000 { /* AIPI2 */
468 compatible = "fsl,aipi-bus", "simple-bus";
469 #address-cells = <1>;
471 reg = <0x10020000 0x20000>;
475 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
477 reg = <0x10021000 0x1000>;
478 clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
479 <&clks IMX27_CLK_LCDC_AHB_GATE>,
480 <&clks IMX27_CLK_PER3_GATE>;
481 clock-names = "ipg", "ahb", "per";
485 coda: coda@10023000 {
486 compatible = "fsl,imx27-vpu", "cnm,codadx6";
487 reg = <0x10023000 0x0200>;
489 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
490 <&clks IMX27_CLK_VPU_AHB_GATE>;
491 clock-names = "per", "ahb";
495 usbotg: usb@10024000 {
496 compatible = "fsl,imx27-usb";
497 reg = <0x10024000 0x200>;
499 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
500 <&clks IMX27_CLK_USB_AHB_GATE>,
501 <&clks IMX27_CLK_USB_DIV>;
502 clock-names = "ipg", "ahb", "per";
503 fsl,usbmisc = <&usbmisc 0>;
507 usbh1: usb@10024200 {
508 compatible = "fsl,imx27-usb";
509 reg = <0x10024200 0x200>;
511 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
512 <&clks IMX27_CLK_USB_AHB_GATE>,
513 <&clks IMX27_CLK_USB_DIV>;
514 clock-names = "ipg", "ahb", "per";
515 fsl,usbmisc = <&usbmisc 1>;
520 usbh2: usb@10024400 {
521 compatible = "fsl,imx27-usb";
522 reg = <0x10024400 0x200>;
524 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
525 <&clks IMX27_CLK_USB_AHB_GATE>,
526 <&clks IMX27_CLK_USB_DIV>;
527 clock-names = "ipg", "ahb", "per";
528 fsl,usbmisc = <&usbmisc 2>;
533 usbmisc: usbmisc@10024600 {
535 compatible = "fsl,imx27-usbmisc";
536 reg = <0x10024600 0x200>;
539 sahara2: sahara@10025000 {
540 compatible = "fsl,imx27-sahara";
541 reg = <0x10025000 0x1000>;
543 clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
544 <&clks IMX27_CLK_SAHARA_AHB_GATE>;
545 clock-names = "ipg", "ahb";
549 compatible = "fsl,imx27-ccm";
550 reg = <0x10027000 0x1000>;
555 compatible = "fsl,imx27-iim";
556 reg = <0x10028000 0x1000>;
558 clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
561 fec: ethernet@1002b000 {
562 compatible = "fsl,imx27-fec";
563 reg = <0x1002b000 0x1000>;
565 clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
566 <&clks IMX27_CLK_FEC_AHB_GATE>;
567 clock-names = "ipg", "ahb";
573 #address-cells = <1>;
575 compatible = "fsl,imx27-nand";
576 reg = <0xd8000000 0x1000>;
578 clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
582 weim: weim@d8002000 {
583 #address-cells = <2>;
585 compatible = "fsl,imx27-weim";
586 reg = <0xd8002000 0x1000>;
587 clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
589 0 0 0xc0000000 0x08000000
590 1 0 0xc8000000 0x08000000
591 2 0 0xd0000000 0x02000000
592 3 0 0xd2000000 0x02000000
593 4 0 0xd4000000 0x02000000
594 5 0 0xd6000000 0x02000000
599 iram: iram@ffff4c00 {
600 compatible = "mmio-sram";
601 reg = <0xffff4c00 0xb400>;