2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <dt-bindings/gpio/gpio.h>
13 #include "imx28-pinfunc.h"
19 interrupt-parent = <&icoll>;
47 compatible = "arm,arm926ej-s";
53 compatible = "simple-bus";
56 reg = <0x80000000 0x80000>;
60 compatible = "simple-bus";
63 reg = <0x80000000 0x3c900>;
66 icoll: interrupt-controller@80000000 {
67 compatible = "fsl,imx28-icoll", "fsl,icoll";
69 #interrupt-cells = <1>;
70 reg = <0x80000000 0x2000>;
73 hsadc: hsadc@80002000 {
74 reg = <0x80002000 0x2000>;
76 dmas = <&dma_apbh 12>;
81 dma_apbh: dma-apbh@80004000 {
82 compatible = "fsl,imx28-dma-apbh";
83 reg = <0x80004000 0x2000>;
84 interrupts = <82 83 84 85
88 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
89 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
90 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
91 "hsadc", "lcdif", "empty", "empty";
97 perfmon: perfmon@80006000 {
98 reg = <0x80006000 0x800>;
103 gpmi: gpmi-nand@8000c000 {
104 compatible = "fsl,imx28-gpmi-nand";
105 #address-cells = <1>;
107 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
108 reg-names = "gpmi-nand", "bch";
110 interrupt-names = "bch";
112 clock-names = "gpmi_io";
113 dmas = <&dma_apbh 4>;
119 #address-cells = <1>;
121 reg = <0x80010000 0x2000>;
124 dmas = <&dma_apbh 0>;
130 #address-cells = <1>;
132 reg = <0x80012000 0x2000>;
135 dmas = <&dma_apbh 1>;
141 #address-cells = <1>;
143 reg = <0x80014000 0x2000>;
146 dmas = <&dma_apbh 2>;
152 #address-cells = <1>;
154 reg = <0x80016000 0x2000>;
157 dmas = <&dma_apbh 3>;
162 pinctrl: pinctrl@80018000 {
163 #address-cells = <1>;
165 compatible = "fsl,imx28-pinctrl", "simple-bus";
166 reg = <0x80018000 0x2000>;
169 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
174 interrupt-controller;
175 #interrupt-cells = <2>;
179 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
184 interrupt-controller;
185 #interrupt-cells = <2>;
189 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
194 interrupt-controller;
195 #interrupt-cells = <2>;
199 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
204 interrupt-controller;
205 #interrupt-cells = <2>;
209 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
214 interrupt-controller;
215 #interrupt-cells = <2>;
218 duart_pins_a: duart@0 {
221 MX28_PAD_PWM0__DUART_RX
222 MX28_PAD_PWM1__DUART_TX
224 fsl,drive-strength = <MXS_DRIVE_4mA>;
225 fsl,voltage = <MXS_VOLTAGE_HIGH>;
226 fsl,pull-up = <MXS_PULL_DISABLE>;
229 duart_pins_b: duart@1 {
232 MX28_PAD_AUART0_CTS__DUART_RX
233 MX28_PAD_AUART0_RTS__DUART_TX
235 fsl,drive-strength = <MXS_DRIVE_4mA>;
236 fsl,voltage = <MXS_VOLTAGE_HIGH>;
237 fsl,pull-up = <MXS_PULL_DISABLE>;
240 duart_4pins_a: duart-4pins@0 {
243 MX28_PAD_AUART0_CTS__DUART_RX
244 MX28_PAD_AUART0_RTS__DUART_TX
245 MX28_PAD_AUART0_RX__DUART_CTS
246 MX28_PAD_AUART0_TX__DUART_RTS
248 fsl,drive-strength = <MXS_DRIVE_4mA>;
249 fsl,voltage = <MXS_VOLTAGE_HIGH>;
250 fsl,pull-up = <MXS_PULL_DISABLE>;
253 gpmi_pins_a: gpmi-nand@0 {
256 MX28_PAD_GPMI_D00__GPMI_D0
257 MX28_PAD_GPMI_D01__GPMI_D1
258 MX28_PAD_GPMI_D02__GPMI_D2
259 MX28_PAD_GPMI_D03__GPMI_D3
260 MX28_PAD_GPMI_D04__GPMI_D4
261 MX28_PAD_GPMI_D05__GPMI_D5
262 MX28_PAD_GPMI_D06__GPMI_D6
263 MX28_PAD_GPMI_D07__GPMI_D7
264 MX28_PAD_GPMI_CE0N__GPMI_CE0N
265 MX28_PAD_GPMI_RDY0__GPMI_READY0
266 MX28_PAD_GPMI_RDN__GPMI_RDN
267 MX28_PAD_GPMI_WRN__GPMI_WRN
268 MX28_PAD_GPMI_ALE__GPMI_ALE
269 MX28_PAD_GPMI_CLE__GPMI_CLE
270 MX28_PAD_GPMI_RESETN__GPMI_RESETN
272 fsl,drive-strength = <MXS_DRIVE_4mA>;
273 fsl,voltage = <MXS_VOLTAGE_HIGH>;
274 fsl,pull-up = <MXS_PULL_DISABLE>;
277 gpmi_status_cfg: gpmi-status-cfg {
279 MX28_PAD_GPMI_RDN__GPMI_RDN
280 MX28_PAD_GPMI_WRN__GPMI_WRN
281 MX28_PAD_GPMI_RESETN__GPMI_RESETN
283 fsl,drive-strength = <MXS_DRIVE_12mA>;
286 auart0_pins_a: auart0@0 {
289 MX28_PAD_AUART0_RX__AUART0_RX
290 MX28_PAD_AUART0_TX__AUART0_TX
291 MX28_PAD_AUART0_CTS__AUART0_CTS
292 MX28_PAD_AUART0_RTS__AUART0_RTS
294 fsl,drive-strength = <MXS_DRIVE_4mA>;
295 fsl,voltage = <MXS_VOLTAGE_HIGH>;
296 fsl,pull-up = <MXS_PULL_DISABLE>;
299 auart0_2pins_a: auart0-2pins@0 {
302 MX28_PAD_AUART0_RX__AUART0_RX
303 MX28_PAD_AUART0_TX__AUART0_TX
305 fsl,drive-strength = <MXS_DRIVE_4mA>;
306 fsl,voltage = <MXS_VOLTAGE_HIGH>;
307 fsl,pull-up = <MXS_PULL_DISABLE>;
310 auart1_pins_a: auart1@0 {
313 MX28_PAD_AUART1_RX__AUART1_RX
314 MX28_PAD_AUART1_TX__AUART1_TX
315 MX28_PAD_AUART1_CTS__AUART1_CTS
316 MX28_PAD_AUART1_RTS__AUART1_RTS
318 fsl,drive-strength = <MXS_DRIVE_4mA>;
319 fsl,voltage = <MXS_VOLTAGE_HIGH>;
320 fsl,pull-up = <MXS_PULL_DISABLE>;
323 auart1_2pins_a: auart1-2pins@0 {
326 MX28_PAD_AUART1_RX__AUART1_RX
327 MX28_PAD_AUART1_TX__AUART1_TX
329 fsl,drive-strength = <MXS_DRIVE_4mA>;
330 fsl,voltage = <MXS_VOLTAGE_HIGH>;
331 fsl,pull-up = <MXS_PULL_DISABLE>;
334 auart2_2pins_a: auart2-2pins@0 {
337 MX28_PAD_SSP2_SCK__AUART2_RX
338 MX28_PAD_SSP2_MOSI__AUART2_TX
340 fsl,drive-strength = <MXS_DRIVE_4mA>;
341 fsl,voltage = <MXS_VOLTAGE_HIGH>;
342 fsl,pull-up = <MXS_PULL_DISABLE>;
345 auart2_2pins_b: auart2-2pins@1 {
348 MX28_PAD_AUART2_RX__AUART2_RX
349 MX28_PAD_AUART2_TX__AUART2_TX
351 fsl,drive-strength = <MXS_DRIVE_4mA>;
352 fsl,voltage = <MXS_VOLTAGE_HIGH>;
353 fsl,pull-up = <MXS_PULL_DISABLE>;
356 auart2_pins_a: auart2-pins@0 {
359 MX28_PAD_AUART2_RX__AUART2_RX
360 MX28_PAD_AUART2_TX__AUART2_TX
361 MX28_PAD_AUART2_CTS__AUART2_CTS
362 MX28_PAD_AUART2_RTS__AUART2_RTS
364 fsl,drive-strength = <MXS_DRIVE_4mA>;
365 fsl,voltage = <MXS_VOLTAGE_HIGH>;
366 fsl,pull-up = <MXS_PULL_DISABLE>;
369 auart3_pins_a: auart3@0 {
372 MX28_PAD_AUART3_RX__AUART3_RX
373 MX28_PAD_AUART3_TX__AUART3_TX
374 MX28_PAD_AUART3_CTS__AUART3_CTS
375 MX28_PAD_AUART3_RTS__AUART3_RTS
377 fsl,drive-strength = <MXS_DRIVE_4mA>;
378 fsl,voltage = <MXS_VOLTAGE_HIGH>;
379 fsl,pull-up = <MXS_PULL_DISABLE>;
382 auart3_2pins_a: auart3-2pins@0 {
385 MX28_PAD_SSP2_MISO__AUART3_RX
386 MX28_PAD_SSP2_SS0__AUART3_TX
388 fsl,drive-strength = <MXS_DRIVE_4mA>;
389 fsl,voltage = <MXS_VOLTAGE_HIGH>;
390 fsl,pull-up = <MXS_PULL_DISABLE>;
393 auart3_2pins_b: auart3-2pins@1 {
396 MX28_PAD_AUART3_RX__AUART3_RX
397 MX28_PAD_AUART3_TX__AUART3_TX
399 fsl,drive-strength = <MXS_DRIVE_4mA>;
400 fsl,voltage = <MXS_VOLTAGE_HIGH>;
401 fsl,pull-up = <MXS_PULL_DISABLE>;
404 auart4_2pins_a: auart4@0 {
407 MX28_PAD_SSP3_SCK__AUART4_TX
408 MX28_PAD_SSP3_MOSI__AUART4_RX
410 fsl,drive-strength = <MXS_DRIVE_4mA>;
411 fsl,voltage = <MXS_VOLTAGE_HIGH>;
412 fsl,pull-up = <MXS_PULL_DISABLE>;
415 auart4_2pins_b: auart4@1 {
418 MX28_PAD_AUART0_CTS__AUART4_RX
419 MX28_PAD_AUART0_RTS__AUART4_TX
421 fsl,drive-strength = <MXS_DRIVE_4mA>;
422 fsl,voltage = <MXS_VOLTAGE_HIGH>;
423 fsl,pull-up = <MXS_PULL_DISABLE>;
426 mac0_pins_a: mac0@0 {
429 MX28_PAD_ENET0_MDC__ENET0_MDC
430 MX28_PAD_ENET0_MDIO__ENET0_MDIO
431 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
432 MX28_PAD_ENET0_RXD0__ENET0_RXD0
433 MX28_PAD_ENET0_RXD1__ENET0_RXD1
434 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
435 MX28_PAD_ENET0_TXD0__ENET0_TXD0
436 MX28_PAD_ENET0_TXD1__ENET0_TXD1
437 MX28_PAD_ENET_CLK__CLKCTRL_ENET
439 fsl,drive-strength = <MXS_DRIVE_8mA>;
440 fsl,voltage = <MXS_VOLTAGE_HIGH>;
441 fsl,pull-up = <MXS_PULL_ENABLE>;
444 mac0_pins_b: mac0@1 {
447 MX28_PAD_ENET0_MDC__ENET0_MDC
448 MX28_PAD_ENET0_MDIO__ENET0_MDIO
449 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
450 MX28_PAD_ENET0_RXD0__ENET0_RXD0
451 MX28_PAD_ENET0_RXD1__ENET0_RXD1
452 MX28_PAD_ENET0_RXD2__ENET0_RXD2
453 MX28_PAD_ENET0_RXD3__ENET0_RXD3
454 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
455 MX28_PAD_ENET0_TXD0__ENET0_TXD0
456 MX28_PAD_ENET0_TXD1__ENET0_TXD1
457 MX28_PAD_ENET0_TXD2__ENET0_TXD2
458 MX28_PAD_ENET0_TXD3__ENET0_TXD3
459 MX28_PAD_ENET_CLK__CLKCTRL_ENET
460 MX28_PAD_ENET0_COL__ENET0_COL
461 MX28_PAD_ENET0_CRS__ENET0_CRS
462 MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
463 MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
465 fsl,drive-strength = <MXS_DRIVE_8mA>;
466 fsl,voltage = <MXS_VOLTAGE_HIGH>;
467 fsl,pull-up = <MXS_PULL_ENABLE>;
470 mac1_pins_a: mac1@0 {
473 MX28_PAD_ENET0_CRS__ENET1_RX_EN
474 MX28_PAD_ENET0_RXD2__ENET1_RXD0
475 MX28_PAD_ENET0_RXD3__ENET1_RXD1
476 MX28_PAD_ENET0_COL__ENET1_TX_EN
477 MX28_PAD_ENET0_TXD2__ENET1_TXD0
478 MX28_PAD_ENET0_TXD3__ENET1_TXD1
480 fsl,drive-strength = <MXS_DRIVE_8mA>;
481 fsl,voltage = <MXS_VOLTAGE_HIGH>;
482 fsl,pull-up = <MXS_PULL_ENABLE>;
485 mmc0_8bit_pins_a: mmc0-8bit@0 {
488 MX28_PAD_SSP0_DATA0__SSP0_D0
489 MX28_PAD_SSP0_DATA1__SSP0_D1
490 MX28_PAD_SSP0_DATA2__SSP0_D2
491 MX28_PAD_SSP0_DATA3__SSP0_D3
492 MX28_PAD_SSP0_DATA4__SSP0_D4
493 MX28_PAD_SSP0_DATA5__SSP0_D5
494 MX28_PAD_SSP0_DATA6__SSP0_D6
495 MX28_PAD_SSP0_DATA7__SSP0_D7
496 MX28_PAD_SSP0_CMD__SSP0_CMD
497 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
498 MX28_PAD_SSP0_SCK__SSP0_SCK
500 fsl,drive-strength = <MXS_DRIVE_8mA>;
501 fsl,voltage = <MXS_VOLTAGE_HIGH>;
502 fsl,pull-up = <MXS_PULL_ENABLE>;
505 mmc0_4bit_pins_a: mmc0-4bit@0 {
508 MX28_PAD_SSP0_DATA0__SSP0_D0
509 MX28_PAD_SSP0_DATA1__SSP0_D1
510 MX28_PAD_SSP0_DATA2__SSP0_D2
511 MX28_PAD_SSP0_DATA3__SSP0_D3
512 MX28_PAD_SSP0_CMD__SSP0_CMD
513 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
514 MX28_PAD_SSP0_SCK__SSP0_SCK
516 fsl,drive-strength = <MXS_DRIVE_8mA>;
517 fsl,voltage = <MXS_VOLTAGE_HIGH>;
518 fsl,pull-up = <MXS_PULL_ENABLE>;
521 mmc0_cd_cfg: mmc0-cd-cfg {
523 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
525 fsl,pull-up = <MXS_PULL_DISABLE>;
528 mmc0_sck_cfg: mmc0-sck-cfg {
530 MX28_PAD_SSP0_SCK__SSP0_SCK
532 fsl,drive-strength = <MXS_DRIVE_12mA>;
533 fsl,pull-up = <MXS_PULL_DISABLE>;
536 mmc1_4bit_pins_a: mmc1-4bit@0 {
539 MX28_PAD_GPMI_D00__SSP1_D0
540 MX28_PAD_GPMI_D01__SSP1_D1
541 MX28_PAD_GPMI_D02__SSP1_D2
542 MX28_PAD_GPMI_D03__SSP1_D3
543 MX28_PAD_GPMI_RDY1__SSP1_CMD
544 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
545 MX28_PAD_GPMI_WRN__SSP1_SCK
547 fsl,drive-strength = <MXS_DRIVE_8mA>;
548 fsl,voltage = <MXS_VOLTAGE_HIGH>;
549 fsl,pull-up = <MXS_PULL_ENABLE>;
552 mmc1_cd_cfg: mmc1-cd-cfg {
554 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
556 fsl,pull-up = <MXS_PULL_DISABLE>;
559 mmc1_sck_cfg: mmc1-sck-cfg {
561 MX28_PAD_GPMI_WRN__SSP1_SCK
563 fsl,drive-strength = <MXS_DRIVE_12mA>;
564 fsl,pull-up = <MXS_PULL_DISABLE>;
568 mmc2_4bit_pins_a: mmc2-4bit@0 {
571 MX28_PAD_SSP0_DATA4__SSP2_D0
572 MX28_PAD_SSP1_SCK__SSP2_D1
573 MX28_PAD_SSP1_CMD__SSP2_D2
574 MX28_PAD_SSP0_DATA5__SSP2_D3
575 MX28_PAD_SSP0_DATA6__SSP2_CMD
576 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
577 MX28_PAD_SSP0_DATA7__SSP2_SCK
579 fsl,drive-strength = <MXS_DRIVE_8mA>;
580 fsl,voltage = <MXS_VOLTAGE_HIGH>;
581 fsl,pull-up = <MXS_PULL_ENABLE>;
584 mmc2_cd_cfg: mmc2-cd-cfg {
586 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
588 fsl,pull-up = <MXS_PULL_DISABLE>;
591 mmc2_sck_cfg: mmc2-sck-cfg {
593 MX28_PAD_SSP0_DATA7__SSP2_SCK
595 fsl,drive-strength = <MXS_DRIVE_12mA>;
596 fsl,pull-up = <MXS_PULL_DISABLE>;
599 i2c0_pins_a: i2c0@0 {
602 MX28_PAD_I2C0_SCL__I2C0_SCL
603 MX28_PAD_I2C0_SDA__I2C0_SDA
605 fsl,drive-strength = <MXS_DRIVE_8mA>;
606 fsl,voltage = <MXS_VOLTAGE_HIGH>;
607 fsl,pull-up = <MXS_PULL_ENABLE>;
610 i2c0_pins_b: i2c0@1 {
613 MX28_PAD_AUART0_RX__I2C0_SCL
614 MX28_PAD_AUART0_TX__I2C0_SDA
616 fsl,drive-strength = <MXS_DRIVE_8mA>;
617 fsl,voltage = <MXS_VOLTAGE_HIGH>;
618 fsl,pull-up = <MXS_PULL_ENABLE>;
621 i2c1_pins_a: i2c1@0 {
624 MX28_PAD_PWM0__I2C1_SCL
625 MX28_PAD_PWM1__I2C1_SDA
627 fsl,drive-strength = <MXS_DRIVE_8mA>;
628 fsl,voltage = <MXS_VOLTAGE_HIGH>;
629 fsl,pull-up = <MXS_PULL_ENABLE>;
632 i2c1_pins_b: i2c1@1 {
635 MX28_PAD_AUART2_CTS__I2C1_SCL
636 MX28_PAD_AUART2_RTS__I2C1_SDA
638 fsl,drive-strength = <MXS_DRIVE_8mA>;
639 fsl,voltage = <MXS_VOLTAGE_HIGH>;
640 fsl,pull-up = <MXS_PULL_ENABLE>;
643 saif0_pins_a: saif0@0 {
646 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
647 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
648 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
649 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
651 fsl,drive-strength = <MXS_DRIVE_12mA>;
652 fsl,voltage = <MXS_VOLTAGE_HIGH>;
653 fsl,pull-up = <MXS_PULL_ENABLE>;
656 saif0_pins_b: saif0@1 {
659 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
660 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
661 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
663 fsl,drive-strength = <MXS_DRIVE_12mA>;
664 fsl,voltage = <MXS_VOLTAGE_HIGH>;
665 fsl,pull-up = <MXS_PULL_ENABLE>;
668 saif1_pins_a: saif1@0 {
671 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
673 fsl,drive-strength = <MXS_DRIVE_12mA>;
674 fsl,voltage = <MXS_VOLTAGE_HIGH>;
675 fsl,pull-up = <MXS_PULL_ENABLE>;
678 pwm0_pins_a: pwm0@0 {
683 fsl,drive-strength = <MXS_DRIVE_4mA>;
684 fsl,voltage = <MXS_VOLTAGE_HIGH>;
685 fsl,pull-up = <MXS_PULL_DISABLE>;
688 pwm2_pins_a: pwm2@0 {
693 fsl,drive-strength = <MXS_DRIVE_4mA>;
694 fsl,voltage = <MXS_VOLTAGE_HIGH>;
695 fsl,pull-up = <MXS_PULL_DISABLE>;
698 pwm3_pins_a: pwm3@0 {
703 fsl,drive-strength = <MXS_DRIVE_4mA>;
704 fsl,voltage = <MXS_VOLTAGE_HIGH>;
705 fsl,pull-up = <MXS_PULL_DISABLE>;
708 pwm3_pins_b: pwm3@1 {
711 MX28_PAD_SAIF0_MCLK__PWM_3
713 fsl,drive-strength = <MXS_DRIVE_4mA>;
714 fsl,voltage = <MXS_VOLTAGE_HIGH>;
715 fsl,pull-up = <MXS_PULL_DISABLE>;
718 pwm4_pins_a: pwm4@0 {
723 fsl,drive-strength = <MXS_DRIVE_4mA>;
724 fsl,voltage = <MXS_VOLTAGE_HIGH>;
725 fsl,pull-up = <MXS_PULL_DISABLE>;
728 lcdif_24bit_pins_a: lcdif-24bit@0 {
731 MX28_PAD_LCD_D00__LCD_D0
732 MX28_PAD_LCD_D01__LCD_D1
733 MX28_PAD_LCD_D02__LCD_D2
734 MX28_PAD_LCD_D03__LCD_D3
735 MX28_PAD_LCD_D04__LCD_D4
736 MX28_PAD_LCD_D05__LCD_D5
737 MX28_PAD_LCD_D06__LCD_D6
738 MX28_PAD_LCD_D07__LCD_D7
739 MX28_PAD_LCD_D08__LCD_D8
740 MX28_PAD_LCD_D09__LCD_D9
741 MX28_PAD_LCD_D10__LCD_D10
742 MX28_PAD_LCD_D11__LCD_D11
743 MX28_PAD_LCD_D12__LCD_D12
744 MX28_PAD_LCD_D13__LCD_D13
745 MX28_PAD_LCD_D14__LCD_D14
746 MX28_PAD_LCD_D15__LCD_D15
747 MX28_PAD_LCD_D16__LCD_D16
748 MX28_PAD_LCD_D17__LCD_D17
749 MX28_PAD_LCD_D18__LCD_D18
750 MX28_PAD_LCD_D19__LCD_D19
751 MX28_PAD_LCD_D20__LCD_D20
752 MX28_PAD_LCD_D21__LCD_D21
753 MX28_PAD_LCD_D22__LCD_D22
754 MX28_PAD_LCD_D23__LCD_D23
756 fsl,drive-strength = <MXS_DRIVE_4mA>;
757 fsl,voltage = <MXS_VOLTAGE_HIGH>;
758 fsl,pull-up = <MXS_PULL_DISABLE>;
761 lcdif_18bit_pins_a: lcdif-18bit@0 {
764 MX28_PAD_LCD_D00__LCD_D0
765 MX28_PAD_LCD_D01__LCD_D1
766 MX28_PAD_LCD_D02__LCD_D2
767 MX28_PAD_LCD_D03__LCD_D3
768 MX28_PAD_LCD_D04__LCD_D4
769 MX28_PAD_LCD_D05__LCD_D5
770 MX28_PAD_LCD_D06__LCD_D6
771 MX28_PAD_LCD_D07__LCD_D7
772 MX28_PAD_LCD_D08__LCD_D8
773 MX28_PAD_LCD_D09__LCD_D9
774 MX28_PAD_LCD_D10__LCD_D10
775 MX28_PAD_LCD_D11__LCD_D11
776 MX28_PAD_LCD_D12__LCD_D12
777 MX28_PAD_LCD_D13__LCD_D13
778 MX28_PAD_LCD_D14__LCD_D14
779 MX28_PAD_LCD_D15__LCD_D15
780 MX28_PAD_LCD_D16__LCD_D16
781 MX28_PAD_LCD_D17__LCD_D17
783 fsl,drive-strength = <MXS_DRIVE_4mA>;
784 fsl,voltage = <MXS_VOLTAGE_HIGH>;
785 fsl,pull-up = <MXS_PULL_DISABLE>;
788 lcdif_16bit_pins_a: lcdif-16bit@0 {
791 MX28_PAD_LCD_D00__LCD_D0
792 MX28_PAD_LCD_D01__LCD_D1
793 MX28_PAD_LCD_D02__LCD_D2
794 MX28_PAD_LCD_D03__LCD_D3
795 MX28_PAD_LCD_D04__LCD_D4
796 MX28_PAD_LCD_D05__LCD_D5
797 MX28_PAD_LCD_D06__LCD_D6
798 MX28_PAD_LCD_D07__LCD_D7
799 MX28_PAD_LCD_D08__LCD_D8
800 MX28_PAD_LCD_D09__LCD_D9
801 MX28_PAD_LCD_D10__LCD_D10
802 MX28_PAD_LCD_D11__LCD_D11
803 MX28_PAD_LCD_D12__LCD_D12
804 MX28_PAD_LCD_D13__LCD_D13
805 MX28_PAD_LCD_D14__LCD_D14
806 MX28_PAD_LCD_D15__LCD_D15
808 fsl,drive-strength = <MXS_DRIVE_4mA>;
809 fsl,voltage = <MXS_VOLTAGE_HIGH>;
810 fsl,pull-up = <MXS_PULL_DISABLE>;
813 lcdif_sync_pins_a: lcdif-sync@0 {
816 MX28_PAD_LCD_RS__LCD_DOTCLK
817 MX28_PAD_LCD_CS__LCD_ENABLE
818 MX28_PAD_LCD_RD_E__LCD_VSYNC
819 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
821 fsl,drive-strength = <MXS_DRIVE_4mA>;
822 fsl,voltage = <MXS_VOLTAGE_HIGH>;
823 fsl,pull-up = <MXS_PULL_DISABLE>;
826 can0_pins_a: can0@0 {
829 MX28_PAD_GPMI_RDY2__CAN0_TX
830 MX28_PAD_GPMI_RDY3__CAN0_RX
832 fsl,drive-strength = <MXS_DRIVE_4mA>;
833 fsl,voltage = <MXS_VOLTAGE_HIGH>;
834 fsl,pull-up = <MXS_PULL_DISABLE>;
837 can1_pins_a: can1@0 {
840 MX28_PAD_GPMI_CE2N__CAN1_TX
841 MX28_PAD_GPMI_CE3N__CAN1_RX
843 fsl,drive-strength = <MXS_DRIVE_4mA>;
844 fsl,voltage = <MXS_VOLTAGE_HIGH>;
845 fsl,pull-up = <MXS_PULL_DISABLE>;
848 spi2_pins_a: spi2@0 {
851 MX28_PAD_SSP2_SCK__SSP2_SCK
852 MX28_PAD_SSP2_MOSI__SSP2_CMD
853 MX28_PAD_SSP2_MISO__SSP2_D0
854 MX28_PAD_SSP2_SS0__SSP2_D3
856 fsl,drive-strength = <MXS_DRIVE_8mA>;
857 fsl,voltage = <MXS_VOLTAGE_HIGH>;
858 fsl,pull-up = <MXS_PULL_ENABLE>;
861 spi3_pins_a: spi3@0 {
864 MX28_PAD_AUART2_RX__SSP3_D4
865 MX28_PAD_AUART2_TX__SSP3_D5
866 MX28_PAD_SSP3_SCK__SSP3_SCK
867 MX28_PAD_SSP3_MOSI__SSP3_CMD
868 MX28_PAD_SSP3_MISO__SSP3_D0
869 MX28_PAD_SSP3_SS0__SSP3_D3
871 fsl,drive-strength = <MXS_DRIVE_8mA>;
872 fsl,voltage = <MXS_VOLTAGE_HIGH>;
873 fsl,pull-up = <MXS_PULL_DISABLE>;
876 spi3_pins_b: spi3@1 {
879 MX28_PAD_SSP3_SCK__SSP3_SCK
880 MX28_PAD_SSP3_MOSI__SSP3_CMD
881 MX28_PAD_SSP3_MISO__SSP3_D0
882 MX28_PAD_SSP3_SS0__SSP3_D3
884 fsl,drive-strength = <MXS_DRIVE_8mA>;
885 fsl,voltage = <MXS_VOLTAGE_HIGH>;
886 fsl,pull-up = <MXS_PULL_ENABLE>;
889 usb0_pins_a: usb0@0 {
892 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
894 fsl,drive-strength = <MXS_DRIVE_12mA>;
895 fsl,voltage = <MXS_VOLTAGE_HIGH>;
896 fsl,pull-up = <MXS_PULL_DISABLE>;
899 usb0_pins_b: usb0@1 {
902 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
904 fsl,drive-strength = <MXS_DRIVE_12mA>;
905 fsl,voltage = <MXS_VOLTAGE_HIGH>;
906 fsl,pull-up = <MXS_PULL_DISABLE>;
909 usb1_pins_a: usb1@0 {
912 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
914 fsl,drive-strength = <MXS_DRIVE_12mA>;
915 fsl,voltage = <MXS_VOLTAGE_HIGH>;
916 fsl,pull-up = <MXS_PULL_DISABLE>;
919 usb0_id_pins_a: usb0id@0 {
922 MX28_PAD_AUART1_RTS__USB0_ID
924 fsl,drive-strength = <MXS_DRIVE_12mA>;
925 fsl,voltage = <MXS_VOLTAGE_HIGH>;
926 fsl,pull-up = <MXS_PULL_ENABLE>;
929 usb0_id_pins_b: usb0id1@0 {
932 MX28_PAD_PWM2__USB0_ID
934 fsl,drive-strength = <MXS_DRIVE_12mA>;
935 fsl,voltage = <MXS_VOLTAGE_HIGH>;
936 fsl,pull-up = <MXS_PULL_ENABLE>;
941 digctl: digctl@8001c000 {
942 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
943 reg = <0x8001c000 0x2000>;
949 reg = <0x80022000 0x2000>;
953 dma_apbx: dma-apbx@80024000 {
954 compatible = "fsl,imx28-dma-apbx";
955 reg = <0x80024000 0x2000>;
956 interrupts = <78 79 66 0
960 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
961 "saif0", "saif1", "i2c0", "i2c1",
962 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
963 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
970 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
971 reg = <0x80028000 0x2000>;
972 interrupts = <52 53 54>;
977 reg = <0x8002a000 0x2000>;
982 ocotp: ocotp@8002c000 {
983 compatible = "fsl,imx28-ocotp", "fsl,ocotp";
984 #address-cells = <1>;
986 reg = <0x8002c000 0x2000>;
991 reg = <0x8002e000 0x2000>;
995 lcdif: lcdif@80030000 {
996 compatible = "fsl,imx28-lcdif";
997 reg = <0x80030000 0x2000>;
1000 dmas = <&dma_apbh 13>;
1002 status = "disabled";
1005 can0: can@80032000 {
1006 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
1007 reg = <0x80032000 0x2000>;
1009 clocks = <&clks 58>, <&clks 58>;
1010 clock-names = "ipg", "per";
1011 status = "disabled";
1014 can1: can@80034000 {
1015 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
1016 reg = <0x80034000 0x2000>;
1018 clocks = <&clks 59>, <&clks 59>;
1019 clock-names = "ipg", "per";
1020 status = "disabled";
1023 simdbg: simdbg@8003c000 {
1024 reg = <0x8003c000 0x200>;
1025 status = "disabled";
1028 simgpmisel: simgpmisel@8003c200 {
1029 reg = <0x8003c200 0x100>;
1030 status = "disabled";
1033 simsspsel: simsspsel@8003c300 {
1034 reg = <0x8003c300 0x100>;
1035 status = "disabled";
1038 simmemsel: simmemsel@8003c400 {
1039 reg = <0x8003c400 0x100>;
1040 status = "disabled";
1043 gpiomon: gpiomon@8003c500 {
1044 reg = <0x8003c500 0x100>;
1045 status = "disabled";
1048 simenet: simenet@8003c700 {
1049 reg = <0x8003c700 0x100>;
1050 status = "disabled";
1053 armjtag: armjtag@8003c800 {
1054 reg = <0x8003c800 0x100>;
1055 status = "disabled";
1060 compatible = "simple-bus";
1061 #address-cells = <1>;
1063 reg = <0x80040000 0x40000>;
1066 clks: clkctrl@80040000 {
1067 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
1068 reg = <0x80040000 0x2000>;
1072 saif0: saif@80042000 {
1073 compatible = "fsl,imx28-saif";
1074 reg = <0x80042000 0x2000>;
1077 clocks = <&clks 53>;
1078 dmas = <&dma_apbx 4>;
1079 dma-names = "rx-tx";
1080 status = "disabled";
1083 power: power@80044000 {
1084 reg = <0x80044000 0x2000>;
1085 status = "disabled";
1088 saif1: saif@80046000 {
1089 compatible = "fsl,imx28-saif";
1090 reg = <0x80046000 0x2000>;
1092 clocks = <&clks 54>;
1093 dmas = <&dma_apbx 5>;
1094 dma-names = "rx-tx";
1095 status = "disabled";
1098 lradc: lradc@80050000 {
1099 compatible = "fsl,imx28-lradc";
1100 reg = <0x80050000 0x2000>;
1101 interrupts = <10 14 15 16 17 18 19
1103 status = "disabled";
1104 clocks = <&clks 41>;
1105 #io-channel-cells = <1>;
1108 spdif: spdif@80054000 {
1109 reg = <0x80054000 0x2000>;
1111 dmas = <&dma_apbx 2>;
1113 status = "disabled";
1116 mxs_rtc: rtc@80056000 {
1117 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
1118 reg = <0x80056000 0x2000>;
1122 i2c0: i2c@80058000 {
1123 #address-cells = <1>;
1125 compatible = "fsl,imx28-i2c";
1126 reg = <0x80058000 0x2000>;
1128 clock-frequency = <100000>;
1129 dmas = <&dma_apbx 6>;
1130 dma-names = "rx-tx";
1131 status = "disabled";
1134 i2c1: i2c@8005a000 {
1135 #address-cells = <1>;
1137 compatible = "fsl,imx28-i2c";
1138 reg = <0x8005a000 0x2000>;
1140 clock-frequency = <100000>;
1141 dmas = <&dma_apbx 7>;
1142 dma-names = "rx-tx";
1143 status = "disabled";
1147 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
1148 reg = <0x80064000 0x2000>;
1149 clocks = <&clks 44>;
1151 fsl,pwm-number = <8>;
1152 status = "disabled";
1155 timer: timrot@80068000 {
1156 compatible = "fsl,imx28-timrot", "fsl,timrot";
1157 reg = <0x80068000 0x2000>;
1158 interrupts = <48 49 50 51>;
1159 clocks = <&clks 26>;
1162 auart0: serial@8006a000 {
1163 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1164 reg = <0x8006a000 0x2000>;
1166 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1167 dma-names = "rx", "tx";
1168 clocks = <&clks 45>;
1169 status = "disabled";
1172 auart1: serial@8006c000 {
1173 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1174 reg = <0x8006c000 0x2000>;
1176 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1177 dma-names = "rx", "tx";
1178 clocks = <&clks 45>;
1179 status = "disabled";
1182 auart2: serial@8006e000 {
1183 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1184 reg = <0x8006e000 0x2000>;
1186 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1187 dma-names = "rx", "tx";
1188 clocks = <&clks 45>;
1189 status = "disabled";
1192 auart3: serial@80070000 {
1193 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1194 reg = <0x80070000 0x2000>;
1196 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1197 dma-names = "rx", "tx";
1198 clocks = <&clks 45>;
1199 status = "disabled";
1202 auart4: serial@80072000 {
1203 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1204 reg = <0x80072000 0x2000>;
1206 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1207 dma-names = "rx", "tx";
1208 clocks = <&clks 45>;
1209 status = "disabled";
1212 duart: serial@80074000 {
1213 compatible = "arm,pl011", "arm,primecell";
1214 reg = <0x80074000 0x1000>;
1216 clocks = <&clks 45>, <&clks 26>;
1217 clock-names = "uart", "apb_pclk";
1218 status = "disabled";
1221 usbphy0: usbphy@8007c000 {
1222 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1223 reg = <0x8007c000 0x2000>;
1224 clocks = <&clks 62>;
1225 status = "disabled";
1228 usbphy1: usbphy@8007e000 {
1229 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1230 reg = <0x8007e000 0x2000>;
1231 clocks = <&clks 63>;
1232 status = "disabled";
1238 compatible = "simple-bus";
1239 #address-cells = <1>;
1241 reg = <0x80080000 0x80000>;
1244 usb0: usb@80080000 {
1245 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1246 reg = <0x80080000 0x10000>;
1248 clocks = <&clks 60>;
1249 fsl,usbphy = <&usbphy0>;
1250 status = "disabled";
1253 usb1: usb@80090000 {
1254 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1255 reg = <0x80090000 0x10000>;
1257 clocks = <&clks 61>;
1258 fsl,usbphy = <&usbphy1>;
1260 status = "disabled";
1263 dflpt: dflpt@800c0000 {
1264 reg = <0x800c0000 0x10000>;
1265 status = "disabled";
1268 mac0: ethernet@800f0000 {
1269 compatible = "fsl,imx28-fec";
1270 reg = <0x800f0000 0x4000>;
1272 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1273 clock-names = "ipg", "ahb", "enet_out";
1274 status = "disabled";
1277 mac1: ethernet@800f4000 {
1278 compatible = "fsl,imx28-fec";
1279 reg = <0x800f4000 0x4000>;
1281 clocks = <&clks 57>, <&clks 57>;
1282 clock-names = "ipg", "ahb";
1283 status = "disabled";
1286 etn_switch: switch@800f8000 {
1287 reg = <0x800f8000 0x8000>;
1288 status = "disabled";
1293 compatible = "iio-hwmon";
1294 io-channels = <&lradc 8>;