arch/arm/boot/dts/imx50.dtsi

   1 /*
   2  * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
   3  * Copyright 2011 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #include "imx50-pinfunc.h"
  15 #include <dt-bindings/clock/imx5-clock.h>
  16
  17 / {
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         aliases {
  22                 ethernet0 = &fec;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 gpio5 = &gpio6;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39                 cpu@0 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a8";
  42                         reg = <0x0>;
  43                 };
  44         };
  45
  46         tzic: tz-interrupt-controller@0fffc000 {
  47                 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
  48                 interrupt-controller;
  49                 #interrupt-cells = <1>;
  50                 reg = <0x0fffc000 0x4000>;
  51         };
  52
  53         clocks {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56
  57                 ckil {
  58                         compatible = "fsl,imx-ckil", "fixed-clock";
  59                         #clock-cells = <0>;
  60                         clock-frequency = <32768>;
  61                 };
  62
  63                 ckih1 {
  64                         compatible = "fsl,imx-ckih1", "fixed-clock";
  65                         #clock-cells = <0>;
  66                         clock-frequency = <22579200>;
  67                 };
  68
  69                 ckih2 {
  70                         compatible = "fsl,imx-ckih2", "fixed-clock";
  71                         #clock-cells = <0>;
  72                         clock-frequency = <0>;
  73                 };
  74
  75                 osc {
  76                         compatible = "fsl,imx-osc", "fixed-clock";
  77                         #clock-cells = <0>;
  78                         clock-frequency = <24000000>;
  79                 };
  80         };
  81
  82         soc {
  83                 #address-cells = <1>;
  84                 #size-cells = <1>;
  85                 compatible = "simple-bus";
  86                 interrupt-parent = <&tzic>;
  87                 ranges;
  88
  89                 aips@50000000 { /* AIPS1 */
  90                         compatible = "fsl,aips-bus", "simple-bus";
  91                         #address-cells = <1>;
  92                         #size-cells = <1>;
  93                         reg = <0x50000000 0x10000000>;
  94                         ranges;
  95
  96                         spba@50000000 {
  97                                 compatible = "fsl,spba-bus", "simple-bus";
  98                                 #address-cells = <1>;
  99                                 #size-cells = <1>;
 100                                 reg = <0x50000000 0x40000>;
 101                                 ranges;
 102
 103                                 esdhc1: esdhc@50004000 {
 104                                         compatible = "fsl,imx50-esdhc";
 105                                         reg = <0x50004000 0x4000>;
 106                                         interrupts = <1>;
 107                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
 108                                                  <&clks IMX5_CLK_DUMMY>,
 109                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
 110                                         clock-names = "ipg", "ahb", "per";
 111                                         bus-width = <4>;
 112                                         status = "disabled";
 113                                 };
 114
 115                                 esdhc2: esdhc@50008000 {
 116                                         compatible = "fsl,imx50-esdhc";
 117                                         reg = <0x50008000 0x4000>;
 118                                         interrupts = <2>;
 119                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
 120                                                  <&clks IMX5_CLK_DUMMY>,
 121                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
 122                                         clock-names = "ipg", "ahb", "per";
 123                                         bus-width = <4>;
 124                                         status = "disabled";
 125                                 };
 126
 127                                 uart3: serial@5000c000 {
 128                                         compatible = "fsl,imx50-uart", "fsl,imx21-uart";
 129                                         reg = <0x5000c000 0x4000>;
 130                                         interrupts = <33>;
 131                                         clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
 132                                                  <&clks IMX5_CLK_UART3_PER_GATE>;
 133                                         clock-names = "ipg", "per";
 134                                         status = "disabled";
 135                                 };
 136
 137                                 ecspi1: ecspi@50010000 {
 138                                         #address-cells = <1>;
 139                                         #size-cells = <0>;
 140                                         compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
 141                                         reg = <0x50010000 0x4000>;
 142                                         interrupts = <36>;
 143                                         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
 144                                                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
 145                                         clock-names = "ipg", "per";
 146                                         status = "disabled";
 147                                 };
 148
 149                                 ssi2: ssi@50014000 {
 150                                         #sound-dai-cells = <0>;
 151                                         compatible = "fsl,imx50-ssi",
 152                                                         "fsl,imx51-ssi",
 153                                                         "fsl,imx21-ssi";
 154                                         reg = <0x50014000 0x4000>;
 155                                         interrupts = <30>;
 156                                         clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
 157                                         dmas = <&sdma 24 1 0>,
 158                                                <&sdma 25 1 0>;
 159                                         dma-names = "rx", "tx";
 160                                         fsl,fifo-depth = <15>;
 161                                         status = "disabled";
 162                                 };
 163
 164                                 esdhc3: esdhc@50020000 {
 165                                         compatible = "fsl,imx50-esdhc";
 166                                         reg = <0x50020000 0x4000>;
 167                                         interrupts = <3>;
 168                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
 169                                                  <&clks IMX5_CLK_DUMMY>,
 170                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
 171                                         clock-names = "ipg", "ahb", "per";
 172                                         bus-width = <4>;
 173                                         status = "disabled";
 174                                 };
 175
 176                                 esdhc4: esdhc@50024000 {
 177                                         compatible = "fsl,imx50-esdhc";
 178                                         reg = <0x50024000 0x4000>;
 179                                         interrupts = <4>;
 180                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
 181                                                  <&clks IMX5_CLK_DUMMY>,
 182                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
 183                                         clock-names = "ipg", "ahb", "per";
 184                                         bus-width = <4>;
 185                                         status = "disabled";
 186                                 };
 187                         };
 188
 189                         usbotg: usb@53f80000 {
 190                                 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
 191                                 reg = <0x53f80000 0x0200>;
 192                                 interrupts = <18>;
 193                                 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
 194                                 status = "disabled";
 195                         };
 196
 197                         usbh1: usb@53f80200 {
 198                                 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
 199                                 reg = <0x53f80200 0x0200>;
 200                                 interrupts = <14>;
 201                                 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
 202                                 dr_mode = "host";
 203                                 status = "disabled";
 204                         };
 205
 206                         usbh2: usb@53f80400 {
 207                                 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
 208                                 reg = <0x53f80400 0x0200>;
 209                                 interrupts = <16>;
 210                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 211                                 dr_mode = "host";
 212                                 status = "disabled";
 213                         };
 214
 215                         usbh3: usb@53f80600 {
 216                                 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
 217                                 reg = <0x53f80600 0x0200>;
 218                                 interrupts = <17>;
 219                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 220                                 dr_mode = "host";
 221                                 status = "disabled";
 222                         };
 223
 224                         gpio1: gpio@53f84000 {
 225                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 226                                 reg = <0x53f84000 0x4000>;
 227                                 interrupts = <50 51>;
 228                                 gpio-controller;
 229                                 #gpio-cells = <2>;
 230                                 interrupt-controller;
 231                                 #interrupt-cells = <2>;
 232                                 gpio-ranges = <&iomuxc 0 151 28>;
 233                         };
 234
 235                         gpio2: gpio@53f88000 {
 236                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 237                                 reg = <0x53f88000 0x4000>;
 238                                 interrupts = <52 53>;
 239                                 gpio-controller;
 240                                 #gpio-cells = <2>;
 241                                 interrupt-controller;
 242                                 #interrupt-cells = <2>;
 243                                 gpio-ranges = <&iomuxc  0 75 8>, <&iomuxc 8 100 8>,
 244                                               <&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
 245                                               <&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
 246                                               <&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
 247                         };
 248
 249                         gpio3: gpio@53f8c000 {
 250                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 251                                 reg = <0x53f8c000 0x4000>;
 252                                 interrupts = <54 55>;
 253                                 gpio-controller;
 254                                 #gpio-cells = <2>;
 255                                 interrupt-controller;
 256                                 #interrupt-cells = <2>;
 257                                 gpio-ranges = <&iomuxc 0 108 32>;
 258                         };
 259
 260                         gpio4: gpio@53f90000 {
 261                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 262                                 reg = <0x53f90000 0x4000>;
 263                                 interrupts = <56 57>;
 264                                 gpio-controller;
 265                                 #gpio-cells = <2>;
 266                                 interrupt-controller;
 267                                 #interrupt-cells = <2>;
 268                                 gpio-ranges = <&iomuxc  0   8  8>, <&iomuxc 8 45 12>,
 269                                               <&iomuxc 20 140 11>;
 270                         };
 271
 272                         wdog1: wdog@53f98000 {
 273                                 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
 274                                 reg = <0x53f98000 0x4000>;
 275                                 interrupts = <58>;
 276                                 clocks = <&clks IMX5_CLK_DUMMY>;
 277                         };
 278
 279                         gpt: timer@53fa0000 {
 280                                 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
 281                                 reg = <0x53fa0000 0x4000>;
 282                                 interrupts = <39>;
 283                                 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
 284                                          <&clks IMX5_CLK_GPT_HF_GATE>;
 285                                 clock-names = "ipg", "per";
 286                         };
 287
 288                         iomuxc: iomuxc@53fa8000 {
 289                                 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
 290                                 reg = <0x53fa8000 0x4000>;
 291                         };
 292
 293                         gpr: iomuxc-gpr@53fa8000 {
 294                                 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
 295                                 reg = <0x53fa8000 0xc>;
 296                         };
 297
 298                         pwm1: pwm@53fb4000 {
 299                                 #pwm-cells = <2>;
 300                                 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
 301                                 reg = <0x53fb4000 0x4000>;
 302                                 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
 303                                          <&clks IMX5_CLK_PWM1_HF_GATE>;
 304                                 clock-names = "ipg", "per";
 305                                 interrupts = <61>;
 306                         };
 307
 308                         pwm2: pwm@53fb8000 {
 309                                 #pwm-cells = <2>;
 310                                 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
 311                                 reg = <0x53fb8000 0x4000>;
 312                                 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
 313                                          <&clks IMX5_CLK_PWM2_HF_GATE>;
 314                                 clock-names = "ipg", "per";
 315                                 interrupts = <94>;
 316                         };
 317
 318                         uart1: serial@53fbc000 {
 319                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
 320                                 reg = <0x53fbc000 0x4000>;
 321                                 interrupts = <31>;
 322                                 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
 323                                          <&clks IMX5_CLK_UART1_PER_GATE>;
 324                                 clock-names = "ipg", "per";
 325                                 status = "disabled";
 326                         };
 327
 328                         uart2: serial@53fc0000 {
 329                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
 330                                 reg = <0x53fc0000 0x4000>;
 331                                 interrupts = <32>;
 332                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
 333                                          <&clks IMX5_CLK_UART2_PER_GATE>;
 334                                 clock-names = "ipg", "per";
 335                                 status = "disabled";
 336                         };
 337
 338                         src: src@53fd0000 {
 339                                 compatible = "fsl,imx50-src", "fsl,imx51-src";
 340                                 reg = <0x53fd0000 0x4000>;
 341                                 #reset-cells = <1>;
 342                         };
 343
 344                         clks: ccm@53fd4000{
 345                                 compatible = "fsl,imx50-ccm";
 346                                 reg = <0x53fd4000 0x4000>;
 347                                 interrupts = <0 71 0x04 0 72 0x04>;
 348                                 #clock-cells = <1>;
 349                         };
 350
 351                         gpio5: gpio@53fdc000 {
 352                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 353                                 reg = <0x53fdc000 0x4000>;
 354                                 interrupts = <103 104>;
 355                                 gpio-controller;
 356                                 #gpio-cells = <2>;
 357                                 interrupt-controller;
 358                                 #interrupt-cells = <2>;
 359                                 gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
 360                         };
 361
 362                         gpio6: gpio@53fe0000 {
 363                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 364                                 reg = <0x53fe0000 0x4000>;
 365                                 interrupts = <105 106>;
 366                                 gpio-controller;
 367                                 #gpio-cells = <2>;
 368                                 interrupt-controller;
 369                                 #interrupt-cells = <2>;
 370                                 gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
 371                         };
 372
 373                         i2c3: i2c@53fec000 {
 374                                 #address-cells = <1>;
 375                                 #size-cells = <0>;
 376                                 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
 377                                 reg = <0x53fec000 0x4000>;
 378                                 interrupts = <64>;
 379                                 clocks = <&clks IMX5_CLK_I2C3_GATE>;
 380                                 status = "disabled";
 381                         };
 382
 383                         uart4: serial@53ff0000 {
 384                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
 385                                 reg = <0x53ff0000 0x4000>;
 386                                 interrupts = <13>;
 387                                 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
 388                                          <&clks IMX5_CLK_UART4_PER_GATE>;
 389                                 clock-names = "ipg", "per";
 390                                 status = "disabled";
 391                         };
 392                 };
 393
 394                 aips@60000000 { /* AIPS2 */
 395                         compatible = "fsl,aips-bus", "simple-bus";
 396                         #address-cells = <1>;
 397                         #size-cells = <1>;
 398                         reg = <0x60000000 0x10000000>;
 399                         ranges;
 400
 401                         uart5: serial@63f90000 {
 402                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
 403                                 reg = <0x63f90000 0x4000>;
 404                                 interrupts = <86>;
 405                                 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
 406                                          <&clks IMX5_CLK_UART5_PER_GATE>;
 407                                 clock-names = "ipg", "per";
 408                                 status = "disabled";
 409                         };
 410
 411                         owire: owire@63fa4000 {
 412                                 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
 413                                 reg = <0x63fa4000 0x4000>;
 414                                 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
 415                                 status = "disabled";
 416                         };
 417
 418                         ecspi2: ecspi@63fac000 {
 419                                 #address-cells = <1>;
 420                                 #size-cells = <0>;
 421                                 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
 422                                 reg = <0x63fac000 0x4000>;
 423                                 interrupts = <37>;
 424                                 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
 425                                          <&clks IMX5_CLK_ECSPI2_PER_GATE>;
 426                                 clock-names = "ipg", "per";
 427                                 status = "disabled";
 428                         };
 429
 430                         sdma: sdma@63fb0000 {
 431                                 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
 432                                 reg = <0x63fb0000 0x4000>;
 433                                 interrupts = <6>;
 434                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
 435                                          <&clks IMX5_CLK_SDMA_GATE>;
 436                                 clock-names = "ipg", "ahb";
 437                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
 438                         };
 439
 440                         cspi: cspi@63fc0000 {
 441                                 #address-cells = <1>;
 442                                 #size-cells = <0>;
 443                                 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
 444                                 reg = <0x63fc0000 0x4000>;
 445                                 interrupts = <38>;
 446                                 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
 447                                          <&clks IMX5_CLK_CSPI_IPG_GATE>;
 448                                 clock-names = "ipg", "per";
 449                                 status = "disabled";
 450                         };
 451
 452                         i2c2: i2c@63fc4000 {
 453                                 #address-cells = <1>;
 454                                 #size-cells = <0>;
 455                                 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
 456                                 reg = <0x63fc4000 0x4000>;
 457                                 interrupts = <63>;
 458                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
 459                                 status = "disabled";
 460                         };
 461
 462                         i2c1: i2c@63fc8000 {
 463                                 #address-cells = <1>;
 464                                 #size-cells = <0>;
 465                                 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
 466                                 reg = <0x63fc8000 0x4000>;
 467                                 interrupts = <62>;
 468                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
 469                                 status = "disabled";
 470                         };
 471
 472                         ssi1: ssi@63fcc000 {
 473                                 #sound-dai-cells = <0>;
 474                                 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
 475                                                         "fsl,imx21-ssi";
 476                                 reg = <0x63fcc000 0x4000>;
 477                                 interrupts = <29>;
 478                                 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
 479                                 dmas = <&sdma 28 0 0>,
 480                                        <&sdma 29 0 0>;
 481                                 dma-names = "rx", "tx";
 482                                 fsl,fifo-depth = <15>;
 483                                 status = "disabled";
 484                         };
 485
 486                         audmux: audmux@63fd0000 {
 487                                 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
 488                                 reg = <0x63fd0000 0x4000>;
 489                                 status = "disabled";
 490                         };
 491
 492                         fec: ethernet@63fec000 {
 493                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 494                                 reg = <0x63fec000 0x4000>;
 495                                 interrupts = <87>;
 496                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 497                                          <&clks IMX5_CLK_FEC_GATE>,
 498                                          <&clks IMX5_CLK_FEC_GATE>;
 499                                 clock-names = "ipg", "ahb", "ptp";
 500                                 status = "disabled";
 501                         };
 502                 };
 503         };
 504 };