2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "imx50-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
41 compatible = "arm,cortex-a8";
46 tzic: tz-interrupt-controller@0fffc000 {
47 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
49 #interrupt-cells = <1>;
50 reg = <0x0fffc000 0x4000>;
58 compatible = "fsl,imx-ckil", "fixed-clock";
60 clock-frequency = <32768>;
64 compatible = "fsl,imx-ckih1", "fixed-clock";
66 clock-frequency = <22579200>;
70 compatible = "fsl,imx-ckih2", "fixed-clock";
72 clock-frequency = <0>;
76 compatible = "fsl,imx-osc", "fixed-clock";
78 clock-frequency = <24000000>;
85 compatible = "simple-bus";
86 interrupt-parent = <&tzic>;
89 aips@50000000 { /* AIPS1 */
90 compatible = "fsl,aips-bus", "simple-bus";
93 reg = <0x50000000 0x10000000>;
97 compatible = "fsl,spba-bus", "simple-bus";
100 reg = <0x50000000 0x40000>;
103 esdhc1: esdhc@50004000 {
104 compatible = "fsl,imx50-esdhc";
105 reg = <0x50004000 0x4000>;
107 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
108 <&clks IMX5_CLK_DUMMY>,
109 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
110 clock-names = "ipg", "ahb", "per";
115 esdhc2: esdhc@50008000 {
116 compatible = "fsl,imx50-esdhc";
117 reg = <0x50008000 0x4000>;
119 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
120 <&clks IMX5_CLK_DUMMY>,
121 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
122 clock-names = "ipg", "ahb", "per";
127 uart3: serial@5000c000 {
128 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
129 reg = <0x5000c000 0x4000>;
131 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
132 <&clks IMX5_CLK_UART3_PER_GATE>;
133 clock-names = "ipg", "per";
137 ecspi1: ecspi@50010000 {
138 #address-cells = <1>;
140 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
141 reg = <0x50010000 0x4000>;
143 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
144 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
145 clock-names = "ipg", "per";
150 #sound-dai-cells = <0>;
151 compatible = "fsl,imx50-ssi",
154 reg = <0x50014000 0x4000>;
156 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
157 dmas = <&sdma 24 1 0>,
159 dma-names = "rx", "tx";
160 fsl,fifo-depth = <15>;
164 esdhc3: esdhc@50020000 {
165 compatible = "fsl,imx50-esdhc";
166 reg = <0x50020000 0x4000>;
168 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
169 <&clks IMX5_CLK_DUMMY>,
170 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
171 clock-names = "ipg", "ahb", "per";
176 esdhc4: esdhc@50024000 {
177 compatible = "fsl,imx50-esdhc";
178 reg = <0x50024000 0x4000>;
180 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
181 <&clks IMX5_CLK_DUMMY>,
182 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
183 clock-names = "ipg", "ahb", "per";
189 usbotg: usb@53f80000 {
190 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
191 reg = <0x53f80000 0x0200>;
193 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
197 usbh1: usb@53f80200 {
198 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
199 reg = <0x53f80200 0x0200>;
201 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
206 usbh2: usb@53f80400 {
207 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
208 reg = <0x53f80400 0x0200>;
210 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
215 usbh3: usb@53f80600 {
216 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
217 reg = <0x53f80600 0x0200>;
219 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
224 gpio1: gpio@53f84000 {
225 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
226 reg = <0x53f84000 0x4000>;
227 interrupts = <50 51>;
230 interrupt-controller;
231 #interrupt-cells = <2>;
232 gpio-ranges = <&iomuxc 0 151 28>;
235 gpio2: gpio@53f88000 {
236 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
237 reg = <0x53f88000 0x4000>;
238 interrupts = <52 53>;
241 interrupt-controller;
242 #interrupt-cells = <2>;
243 gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>,
244 <&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
245 <&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
246 <&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
249 gpio3: gpio@53f8c000 {
250 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
251 reg = <0x53f8c000 0x4000>;
252 interrupts = <54 55>;
255 interrupt-controller;
256 #interrupt-cells = <2>;
257 gpio-ranges = <&iomuxc 0 108 32>;
260 gpio4: gpio@53f90000 {
261 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
262 reg = <0x53f90000 0x4000>;
263 interrupts = <56 57>;
266 interrupt-controller;
267 #interrupt-cells = <2>;
268 gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>,
272 wdog1: wdog@53f98000 {
273 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
274 reg = <0x53f98000 0x4000>;
276 clocks = <&clks IMX5_CLK_DUMMY>;
279 gpt: timer@53fa0000 {
280 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
281 reg = <0x53fa0000 0x4000>;
283 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
284 <&clks IMX5_CLK_GPT_HF_GATE>;
285 clock-names = "ipg", "per";
288 iomuxc: iomuxc@53fa8000 {
289 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
290 reg = <0x53fa8000 0x4000>;
293 gpr: iomuxc-gpr@53fa8000 {
294 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
295 reg = <0x53fa8000 0xc>;
300 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
301 reg = <0x53fb4000 0x4000>;
302 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
303 <&clks IMX5_CLK_PWM1_HF_GATE>;
304 clock-names = "ipg", "per";
310 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
311 reg = <0x53fb8000 0x4000>;
312 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
313 <&clks IMX5_CLK_PWM2_HF_GATE>;
314 clock-names = "ipg", "per";
318 uart1: serial@53fbc000 {
319 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
320 reg = <0x53fbc000 0x4000>;
322 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
323 <&clks IMX5_CLK_UART1_PER_GATE>;
324 clock-names = "ipg", "per";
328 uart2: serial@53fc0000 {
329 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
330 reg = <0x53fc0000 0x4000>;
332 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
333 <&clks IMX5_CLK_UART2_PER_GATE>;
334 clock-names = "ipg", "per";
339 compatible = "fsl,imx50-src", "fsl,imx51-src";
340 reg = <0x53fd0000 0x4000>;
345 compatible = "fsl,imx50-ccm";
346 reg = <0x53fd4000 0x4000>;
347 interrupts = <0 71 0x04 0 72 0x04>;
351 gpio5: gpio@53fdc000 {
352 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
353 reg = <0x53fdc000 0x4000>;
354 interrupts = <103 104>;
357 interrupt-controller;
358 #interrupt-cells = <2>;
359 gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
362 gpio6: gpio@53fe0000 {
363 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
364 reg = <0x53fe0000 0x4000>;
365 interrupts = <105 106>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
370 gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
374 #address-cells = <1>;
376 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
377 reg = <0x53fec000 0x4000>;
379 clocks = <&clks IMX5_CLK_I2C3_GATE>;
383 uart4: serial@53ff0000 {
384 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
385 reg = <0x53ff0000 0x4000>;
387 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
388 <&clks IMX5_CLK_UART4_PER_GATE>;
389 clock-names = "ipg", "per";
394 aips@60000000 { /* AIPS2 */
395 compatible = "fsl,aips-bus", "simple-bus";
396 #address-cells = <1>;
398 reg = <0x60000000 0x10000000>;
401 uart5: serial@63f90000 {
402 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
403 reg = <0x63f90000 0x4000>;
405 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
406 <&clks IMX5_CLK_UART5_PER_GATE>;
407 clock-names = "ipg", "per";
411 owire: owire@63fa4000 {
412 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
413 reg = <0x63fa4000 0x4000>;
414 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
418 ecspi2: ecspi@63fac000 {
419 #address-cells = <1>;
421 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
422 reg = <0x63fac000 0x4000>;
424 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
425 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
426 clock-names = "ipg", "per";
430 sdma: sdma@63fb0000 {
431 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
432 reg = <0x63fb0000 0x4000>;
434 clocks = <&clks IMX5_CLK_SDMA_GATE>,
435 <&clks IMX5_CLK_SDMA_GATE>;
436 clock-names = "ipg", "ahb";
437 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
440 cspi: cspi@63fc0000 {
441 #address-cells = <1>;
443 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
444 reg = <0x63fc0000 0x4000>;
446 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
447 <&clks IMX5_CLK_CSPI_IPG_GATE>;
448 clock-names = "ipg", "per";
453 #address-cells = <1>;
455 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
456 reg = <0x63fc4000 0x4000>;
458 clocks = <&clks IMX5_CLK_I2C2_GATE>;
463 #address-cells = <1>;
465 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
466 reg = <0x63fc8000 0x4000>;
468 clocks = <&clks IMX5_CLK_I2C1_GATE>;
473 #sound-dai-cells = <0>;
474 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
476 reg = <0x63fcc000 0x4000>;
478 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
479 dmas = <&sdma 28 0 0>,
481 dma-names = "rx", "tx";
482 fsl,fifo-depth = <15>;
486 audmux: audmux@63fd0000 {
487 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
488 reg = <0x63fd0000 0x4000>;
492 fec: ethernet@63fec000 {
493 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
494 reg = <0x63fec000 0x4000>;
496 clocks = <&clks IMX5_CLK_FEC_GATE>,
497 <&clks IMX5_CLK_FEC_GATE>,
498 <&clks IMX5_CLK_FEC_GATE>;
499 clock-names = "ipg", "ahb", "ptp";