arch/arm/boot/dts/imx6q-gw54xx.dts

   1 /*
   2  * Copyright 2013 Gateworks Corporation
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 /dts-v1/;
  13 #include "imx6q.dtsi"
  14 #include "imx6qdl-gw54xx.dtsi"
  15 #include <dt-bindings/media/tda1997x.h>
  16
  17 / {
  18         model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
  19         compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
  20
  21         sound-digital {
  22                 compatible = "simple-audio-card";
  23                 simple-audio-card,name = "tda1997x-audio";
  24
  25                 simple-audio-card,dai-link@0 {
  26                         format = "i2s";
  27
  28                         cpu {
  29                                 sound-dai = <&ssi2>;
  30                         };
  31
  32                         codec {
  33                                 bitclock-master;
  34                                 frame-master;
  35                                 sound-dai = <&hdmi_receiver>;
  36                         };
  37                 };
  38         };
  39 };
  40
  41 &i2c3 {
  42         adv7180: camera@20 {
  43                 compatible = "adi,adv7180";
  44                 pinctrl-names = "default";
  45                 pinctrl-0 = <&pinctrl_adv7180>;
  46                 reg = <0x20>;
  47                 powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
  48                 interrupt-parent = <&gpio3>;
  49                 interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
  50
  51                 port {
  52                         adv7180_to_ipu2_csi1_mux: endpoint {
  53                                 remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
  54                                 bus-width = <8>;
  55                         };
  56                 };
  57         };
  58
  59         hdmi_receiver: hdmi-receiver@48 {
  60                 compatible = "nxp,tda19971";
  61                 pinctrl-names = "default";
  62                 pinctrl-0 = <&pinctrl_tda1997x>;
  63                 reg = <0x48>;
  64                 interrupt-parent = <&gpio1>;
  65                 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
  66                 DOVDD-supply = <&reg_3p3v>;
  67                 AVDD-supply = <&sw4_reg>;
  68                 DVDD-supply = <&sw4_reg>;
  69                 #sound-dai-cells = <0>;
  70                 nxp,audout-format = "i2s";
  71                 nxp,audout-layout = <0>;
  72                 nxp,audout-width = <16>;
  73                 nxp,audout-mclk-fs = <128>;
  74                 /*
  75                  * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
  76                  * and Y[11:4] across 16bits in the same cycle
  77                  * which we map to VP[15:08]<->CSI_DATA[19:12]
  78                  */
  79                 nxp,vidout-portcfg =
  80                         /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
  81                         < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
  82                         /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
  83                         < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
  84                         /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
  85                         < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
  86                         /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
  87                         < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
  88
  89                 port {
  90                         tda1997x_to_ipu1_csi0_mux: endpoint {
  91                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
  92                                 bus-width = <16>;
  93                                 hsync-active = <1>;
  94                                 vsync-active = <1>;
  95                                 data-active = <1>;
  96                         };
  97                 };
  98         };
  99 };
 100
 101 &ipu1_csi0_from_ipu1_csi0_mux {
 102         bus-width = <16>;
 103 };
 104
 105 &ipu1_csi0_mux_from_parallel_sensor {
 106         remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
 107         bus-width = <16>;
 108 };
 109
 110 &ipu1_csi0 {
 111         pinctrl-names = "default";
 112         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 113 };
 114
 115 &ipu2_csi1_from_ipu2_csi1_mux {
 116         bus-width = <8>;
 117 };
 118
 119 &ipu2_csi1_mux_from_parallel_sensor {
 120         remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
 121         bus-width = <8>;
 122 };
 123
 124 &ipu2_csi1 {
 125         pinctrl-names = "default";
 126         pinctrl-0 = <&pinctrl_ipu2_csi1>;
 127 };
 128
 129 &sata {
 130         status = "okay";
 131 };
 132
 133 &iomuxc {
 134         pinctrl_adv7180: adv7180grp {
 135                 fsl,pins = <
 136                         MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x0001b0b0
 137                         MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x4001b0b0
 138                 >;
 139         };
 140
 141         pinctrl_ipu1_csi0: ipu1_csi0grp {
 142                 fsl,pins = <
 143                         MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04          0x1b0b0
 144                         MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05          0x1b0b0
 145                         MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06          0x1b0b0
 146                         MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07          0x1b0b0
 147                         MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08          0x1b0b0
 148                         MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09          0x1b0b0
 149                         MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10         0x1b0b0
 150                         MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11         0x1b0b0
 151                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12         0x1b0b0
 152                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13         0x1b0b0
 153                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14         0x1b0b0
 154                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15         0x1b0b0
 155                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16         0x1b0b0
 156                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17         0x1b0b0
 157                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18         0x1b0b0
 158                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19         0x1b0b0
 159                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC           0x1b0b0
 160                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK        0x1b0b0
 161                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC          0x1b0b0
 162                 >;
 163         };
 164
 165         pinctrl_ipu2_csi1: ipu2_csi1grp {
 166                 fsl,pins = <
 167                         MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19    0x1b0b0
 168                         MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18    0x1b0b0
 169                         MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17    0x1b0b0
 170                         MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16    0x1b0b0
 171                         MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15    0x1b0b0
 172                         MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14    0x1b0b0
 173                         MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13    0x1b0b0
 174                         MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12    0x1b0b0
 175                         MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC     0x1b0b0
 176                         MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC     0x1b0b0
 177                         MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK    0x1b0b0
 178                 >;
 179         };
 180
 181         pinctrl_tda1997x: tda1997xgrp {
 182                 fsl,pins = <
 183                         MX6QDL_PAD_GPIO_7__GPIO1_IO07   0x1b0b0
 184                 >;
 185         };
 186 };