1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright 2013 Freescale Semiconductor, Inc.
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
7 #include "imx6qdl.dtsi"
20 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
40 clock-latency = <61036>; /* two CLK32 periods */
41 clocks = <&clks IMX6QDL_CLK_ARM>,
42 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
43 <&clks IMX6QDL_CLK_STEP>,
44 <&clks IMX6QDL_CLK_PLL1_SW>,
45 <&clks IMX6QDL_CLK_PLL1_SYS>;
46 clock-names = "arm", "pll2_pfd2_396m", "step",
47 "pll1_sw", "pll1_sys";
48 arm-supply = <®_arm>;
49 pu-supply = <®_pu>;
50 soc-supply = <®_soc>;
54 compatible = "arm,cortex-a9";
57 next-level-cache = <&L2>;
61 compatible = "arm,cortex-a9";
64 next-level-cache = <&L2>;
68 compatible = "arm,cortex-a9";
71 next-level-cache = <&L2>;
77 compatible = "mmio-sram";
78 reg = <0x00900000 0x40000>;
79 clocks = <&clks IMX6QDL_CLK_OCRAM>;
82 aips-bus@2000000 { /* AIPS1 */
84 ecspi5: ecspi@2018000 {
87 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
88 reg = <0x02018000 0x4000>;
89 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&clks IMX6Q_CLK_ECSPI5>,
91 <&clks IMX6Q_CLK_ECSPI5>;
92 clock-names = "ipg", "per";
93 dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
94 dma-names = "rx", "tx";
99 iomuxc: iomuxc@20e0000 {
100 compatible = "fsl,imx6q-iomuxc";
105 compatible = "fsl,imx6q-ahci";
106 reg = <0x02200000 0x4000>;
107 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
108 clocks = <&clks IMX6QDL_CLK_SATA>,
109 <&clks IMX6QDL_CLK_SATA_REF_100M>,
110 <&clks IMX6QDL_CLK_AHB>;
111 clock-names = "sata", "sata_ref", "ahb";
115 gpu_vg: gpu@2204000 {
116 compatible = "vivante,gc";
117 reg = <0x02204000 0x4000>;
118 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
120 <&clks IMX6QDL_CLK_GPU2D_CORE>;
121 clock-names = "bus", "core";
122 power-domains = <&pd_pu>;
126 #address-cells = <1>;
128 compatible = "fsl,imx6q-ipu";
129 reg = <0x02800000 0x400000>;
130 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
131 <0 7 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&clks IMX6QDL_CLK_IPU2>,
133 <&clks IMX6QDL_CLK_IPU2_DI0>,
134 <&clks IMX6QDL_CLK_IPU2_DI1>;
135 clock-names = "bus", "di0", "di1";
141 ipu2_csi0_from_mipi_vc2: endpoint {
142 remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
149 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
150 remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
155 #address-cells = <1>;
159 ipu2_di0_disp0: endpoint@0 {
163 ipu2_di0_hdmi: endpoint@1 {
165 remote-endpoint = <&hdmi_mux_2>;
168 ipu2_di0_mipi: endpoint@2 {
170 remote-endpoint = <&mipi_mux_2>;
173 ipu2_di0_lvds0: endpoint@3 {
175 remote-endpoint = <&lvds0_mux_2>;
178 ipu2_di0_lvds1: endpoint@4 {
180 remote-endpoint = <&lvds1_mux_2>;
185 #address-cells = <1>;
189 ipu2_di1_hdmi: endpoint@1 {
191 remote-endpoint = <&hdmi_mux_3>;
194 ipu2_di1_mipi: endpoint@2 {
196 remote-endpoint = <&mipi_mux_3>;
199 ipu2_di1_lvds0: endpoint@3 {
201 remote-endpoint = <&lvds0_mux_3>;
204 ipu2_di1_lvds1: endpoint@4 {
206 remote-endpoint = <&lvds1_mux_3>;
213 compatible = "fsl,imx-capture-subsystem";
214 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
218 compatible = "fsl,imx-display-subsystem";
219 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
224 gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
225 <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
226 <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
227 <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
228 <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
233 gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
238 gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
242 gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
246 gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
247 <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
251 gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
252 <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
257 gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
262 compatible = "video-mux";
263 mux-controls = <&mux 0>;
264 #address-cells = <1>;
270 ipu1_csi0_mux_from_mipi_vc0: endpoint {
271 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
278 ipu1_csi0_mux_from_parallel_sensor: endpoint {
285 ipu1_csi0_mux_to_ipu1_csi0: endpoint {
286 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
292 compatible = "video-mux";
293 mux-controls = <&mux 1>;
294 #address-cells = <1>;
300 ipu2_csi1_mux_from_mipi_vc3: endpoint {
301 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
308 ipu2_csi1_mux_from_parallel_sensor: endpoint {
315 ipu2_csi1_mux_to_ipu2_csi1: endpoint {
316 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
323 compatible = "fsl,imx6q-hdmi";
328 hdmi_mux_2: endpoint {
329 remote-endpoint = <&ipu2_di0_hdmi>;
336 hdmi_mux_3: endpoint {
337 remote-endpoint = <&ipu2_di1_hdmi>;
343 ipu1_csi1_from_mipi_vc1: endpoint {
344 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
349 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
350 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
351 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
352 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
353 clock-names = "di0_pll", "di1_pll",
354 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
361 lvds0_mux_2: endpoint {
362 remote-endpoint = <&ipu2_di0_lvds0>;
369 lvds0_mux_3: endpoint {
370 remote-endpoint = <&ipu2_di1_lvds0>;
379 lvds1_mux_2: endpoint {
380 remote-endpoint = <&ipu2_di0_lvds1>;
387 lvds1_mux_3: endpoint {
388 remote-endpoint = <&ipu2_di1_lvds1>;
398 mipi_vc0_to_ipu1_csi0_mux: endpoint {
399 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
406 mipi_vc1_to_ipu1_csi1: endpoint {
407 remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
414 mipi_vc2_to_ipu2_csi0: endpoint {
415 remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
422 mipi_vc3_to_ipu2_csi1_mux: endpoint {
423 remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
433 mipi_mux_2: endpoint {
434 remote-endpoint = <&ipu2_di0_mipi>;
441 mipi_mux_3: endpoint {
442 remote-endpoint = <&ipu2_di1_mipi>;
449 mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
450 <0x04 0x00100000>, /* MIPI_IPU2_MUX */
451 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
452 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
453 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
454 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
455 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
459 compatible = "fsl,imx6q-vpu", "cnm,coda960";