2 * Copyright 2015 Freescale Semiconductor, Inc.
3 * Copyright 2016 Toradex AG
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/clock/imx7d-clock.h>
45 #include <dt-bindings/gpio/gpio.h>
46 #include <dt-bindings/input/input.h>
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include "imx7d-pinfunc.h"
87 compatible = "arm,cortex-a7";
90 clock-frequency = <792000000>;
91 clock-latency = <61036>; /* two CLK32 periods */
92 clocks = <&clks IMX7D_CLK_ARM>;
97 compatible = "fixed-clock";
99 clock-frequency = <32768>;
100 clock-output-names = "ckil";
104 compatible = "fixed-clock";
106 clock-frequency = <24000000>;
107 clock-output-names = "osc";
111 #address-cells = <1>;
113 compatible = "simple-bus";
114 interrupt-parent = <&intc>;
118 compatible = "arm,coresight-funnel", "arm,primecell";
119 reg = <0x30041000 0x1000>;
120 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
121 clock-names = "apb_pclk";
123 ca_funnel_ports: ports {
124 #address-cells = <1>;
127 /* funnel input ports */
130 ca_funnel_in_port0: endpoint {
132 remote-endpoint = <&etm0_out_port>;
136 /* funnel output port */
139 ca_funnel_out_port0: endpoint {
140 remote-endpoint = <&hugo_funnel_in_port0>;
144 /* the other input ports are not connect to anything */
149 compatible = "arm,coresight-etm3x", "arm,primecell";
150 reg = <0x3007c000 0x1000>;
152 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
153 clock-names = "apb_pclk";
156 etm0_out_port: endpoint {
157 remote-endpoint = <&ca_funnel_in_port0>;
163 compatible = "arm,coresight-funnel", "arm,primecell";
164 reg = <0x30083000 0x1000>;
165 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
166 clock-names = "apb_pclk";
169 #address-cells = <1>;
172 /* funnel input ports */
175 hugo_funnel_in_port0: endpoint {
177 remote-endpoint = <&ca_funnel_out_port0>;
183 hugo_funnel_in_port1: endpoint {
184 slave-mode; /* M4 input */
190 hugo_funnel_out_port0: endpoint {
191 remote-endpoint = <&etf_in_port>;
195 /* the other input ports are not connect to anything */
200 compatible = "arm,coresight-tmc", "arm,primecell";
201 reg = <0x30084000 0x1000>;
202 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
203 clock-names = "apb_pclk";
206 #address-cells = <1>;
211 etf_in_port: endpoint {
213 remote-endpoint = <&hugo_funnel_out_port0>;
219 etf_out_port: endpoint {
220 remote-endpoint = <&replicator_in_port0>;
227 compatible = "arm,coresight-tmc", "arm,primecell";
228 reg = <0x30086000 0x1000>;
229 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
230 clock-names = "apb_pclk";
233 etr_in_port: endpoint {
235 remote-endpoint = <&replicator_out_port1>;
241 compatible = "arm,coresight-tpiu", "arm,primecell";
242 reg = <0x30087000 0x1000>;
243 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
244 clock-names = "apb_pclk";
247 tpiu_in_port: endpoint {
249 remote-endpoint = <&replicator_out_port1>;
256 * non-configurable replicators don't show up on the
257 * AMBA bus. As such no need to add "arm,primecell"
259 compatible = "arm,coresight-replicator";
262 #address-cells = <1>;
265 /* replicator output ports */
268 replicator_out_port0: endpoint {
269 remote-endpoint = <&tpiu_in_port>;
275 replicator_out_port1: endpoint {
276 remote-endpoint = <&etr_in_port>;
280 /* replicator input port */
283 replicator_in_port0: endpoint {
285 remote-endpoint = <&etf_out_port>;
291 intc: interrupt-controller@31001000 {
292 compatible = "arm,cortex-a7-gic";
293 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
294 #interrupt-cells = <3>;
295 interrupt-controller;
296 reg = <0x31001000 0x1000>,
303 compatible = "arm,armv7-timer";
304 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
305 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
306 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
307 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
310 aips1: aips-bus@30000000 {
311 compatible = "fsl,aips-bus", "simple-bus";
312 #address-cells = <1>;
314 reg = <0x30000000 0x400000>;
317 gpio1: gpio@30200000 {
318 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
319 reg = <0x30200000 0x10000>;
320 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
321 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
324 interrupt-controller;
325 #interrupt-cells = <2>;
326 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
329 gpio2: gpio@30210000 {
330 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
331 reg = <0x30210000 0x10000>;
332 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 gpio-ranges = <&iomuxc 0 13 32>;
341 gpio3: gpio@30220000 {
342 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
343 reg = <0x30220000 0x10000>;
344 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 gpio-ranges = <&iomuxc 0 45 29>;
353 gpio4: gpio@30230000 {
354 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
355 reg = <0x30230000 0x10000>;
356 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-controller;
361 #interrupt-cells = <2>;
362 gpio-ranges = <&iomuxc 0 74 24>;
365 gpio5: gpio@30240000 {
366 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
367 reg = <0x30240000 0x10000>;
368 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
369 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
372 interrupt-controller;
373 #interrupt-cells = <2>;
374 gpio-ranges = <&iomuxc 0 98 18>;
377 gpio6: gpio@30250000 {
378 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
379 reg = <0x30250000 0x10000>;
380 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
384 interrupt-controller;
385 #interrupt-cells = <2>;
386 gpio-ranges = <&iomuxc 0 116 23>;
389 gpio7: gpio@30260000 {
390 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
391 reg = <0x30260000 0x10000>;
392 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
396 interrupt-controller;
397 #interrupt-cells = <2>;
398 gpio-ranges = <&iomuxc 0 139 16>;
401 wdog1: wdog@30280000 {
402 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
403 reg = <0x30280000 0x10000>;
404 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
408 wdog2: wdog@30290000 {
409 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
410 reg = <0x30290000 0x10000>;
411 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
416 wdog3: wdog@302a0000 {
417 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
418 reg = <0x302a0000 0x10000>;
419 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
424 wdog4: wdog@302b0000 {
425 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
426 reg = <0x302b0000 0x10000>;
427 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
432 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
433 compatible = "fsl,imx7d-iomuxc-lpsr";
434 reg = <0x302c0000 0x10000>;
435 fsl,input-sel = <&iomuxc>;
439 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
440 reg = <0x302d0000 0x10000>;
441 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&clks IMX7D_CLK_DUMMY>,
443 <&clks IMX7D_GPT1_ROOT_CLK>;
444 clock-names = "ipg", "per";
448 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
449 reg = <0x302e0000 0x10000>;
450 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&clks IMX7D_CLK_DUMMY>,
452 <&clks IMX7D_GPT2_ROOT_CLK>;
453 clock-names = "ipg", "per";
458 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
459 reg = <0x302f0000 0x10000>;
460 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&clks IMX7D_CLK_DUMMY>,
462 <&clks IMX7D_GPT3_ROOT_CLK>;
463 clock-names = "ipg", "per";
468 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
469 reg = <0x30300000 0x10000>;
470 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&clks IMX7D_CLK_DUMMY>,
472 <&clks IMX7D_GPT4_ROOT_CLK>;
473 clock-names = "ipg", "per";
477 iomuxc: iomuxc@30330000 {
478 compatible = "fsl,imx7d-iomuxc";
479 reg = <0x30330000 0x10000>;
482 gpr: iomuxc-gpr@30340000 {
483 compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
484 reg = <0x30340000 0x10000>;
487 ocotp: ocotp-ctrl@30350000 {
488 compatible = "syscon";
489 reg = <0x30350000 0x10000>;
490 clocks = <&clks IMX7D_CLK_DUMMY>;
494 anatop: anatop@30360000 {
495 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
496 "syscon", "simple-bus";
497 reg = <0x30360000 0x10000>;
498 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
501 reg_1p0d: regulator-vdd1p0d {
502 compatible = "fsl,anatop-regulator";
503 regulator-name = "vdd1p0d";
504 regulator-min-microvolt = <800000>;
505 regulator-max-microvolt = <1200000>;
506 anatop-reg-offset = <0x210>;
507 anatop-vol-bit-shift = <8>;
508 anatop-vol-bit-width = <5>;
509 anatop-min-bit-val = <8>;
510 anatop-min-voltage = <800000>;
511 anatop-max-voltage = <1200000>;
512 anatop-enable-bit = <31>;
516 snvs: snvs@30370000 {
517 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
518 reg = <0x30370000 0x10000>;
520 snvs_rtc: snvs-rtc-lp {
521 compatible = "fsl,sec-v4.0-mon-rtc-lp";
524 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
528 snvs_poweroff: snvs-poweroff {
529 compatible = "syscon-poweroff";
535 snvs_pwrkey: snvs-powerkey {
536 compatible = "fsl,sec-v4.0-pwrkey";
538 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
539 linux,keycode = <KEY_POWER>;
545 compatible = "fsl,imx7d-ccm";
546 reg = <0x30380000 0x10000>;
547 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&ckil>, <&osc>;
551 clock-names = "ckil", "osc";
555 compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
556 reg = <0x30390000 0x10000>;
557 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
562 aips2: aips-bus@30400000 {
563 compatible = "fsl,aips-bus", "simple-bus";
564 #address-cells = <1>;
566 reg = <0x30400000 0x400000>;
570 compatible = "fsl,imx7d-adc";
571 reg = <0x30610000 0x10000>;
572 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
579 compatible = "fsl,imx7d-adc";
580 reg = <0x30620000 0x10000>;
581 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
587 ecspi4: ecspi@30630000 {
588 #address-cells = <1>;
590 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
591 reg = <0x30630000 0x10000>;
592 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
594 <&clks IMX7D_ECSPI4_ROOT_CLK>;
595 clock-names = "ipg", "per";
600 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
601 reg = <0x30660000 0x10000>;
602 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
604 <&clks IMX7D_PWM1_ROOT_CLK>;
605 clock-names = "ipg", "per";
611 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
612 reg = <0x30670000 0x10000>;
613 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
615 <&clks IMX7D_PWM2_ROOT_CLK>;
616 clock-names = "ipg", "per";
622 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
623 reg = <0x30680000 0x10000>;
624 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
626 <&clks IMX7D_PWM3_ROOT_CLK>;
627 clock-names = "ipg", "per";
633 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
634 reg = <0x30690000 0x10000>;
635 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
637 <&clks IMX7D_PWM4_ROOT_CLK>;
638 clock-names = "ipg", "per";
643 lcdif: lcdif@30730000 {
644 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
645 reg = <0x30730000 0x10000>;
646 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
648 <&clks IMX7D_CLK_DUMMY>,
649 <&clks IMX7D_CLK_DUMMY>;
650 clock-names = "pix", "axi", "disp_axi";
655 aips3: aips-bus@30800000 {
656 compatible = "fsl,aips-bus", "simple-bus";
657 #address-cells = <1>;
659 reg = <0x30800000 0x400000>;
662 ecspi1: ecspi@30820000 {
663 #address-cells = <1>;
665 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
666 reg = <0x30820000 0x10000>;
667 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
669 <&clks IMX7D_ECSPI1_ROOT_CLK>;
670 clock-names = "ipg", "per";
674 ecspi2: ecspi@30830000 {
675 #address-cells = <1>;
677 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
678 reg = <0x30830000 0x10000>;
679 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
681 <&clks IMX7D_ECSPI2_ROOT_CLK>;
682 clock-names = "ipg", "per";
686 ecspi3: ecspi@30840000 {
687 #address-cells = <1>;
689 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
690 reg = <0x30840000 0x10000>;
691 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
693 <&clks IMX7D_ECSPI3_ROOT_CLK>;
694 clock-names = "ipg", "per";
698 uart1: serial@30860000 {
699 compatible = "fsl,imx7d-uart",
701 reg = <0x30860000 0x10000>;
702 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
704 <&clks IMX7D_UART1_ROOT_CLK>;
705 clock-names = "ipg", "per";
709 uart2: serial@30890000 {
710 compatible = "fsl,imx7d-uart",
712 reg = <0x30890000 0x10000>;
713 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
715 <&clks IMX7D_UART2_ROOT_CLK>;
716 clock-names = "ipg", "per";
720 uart3: serial@30880000 {
721 compatible = "fsl,imx7d-uart",
723 reg = <0x30880000 0x10000>;
724 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
726 <&clks IMX7D_UART3_ROOT_CLK>;
727 clock-names = "ipg", "per";
732 #sound-dai-cells = <0>;
733 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
734 reg = <0x308a0000 0x10000>;
735 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
737 <&clks IMX7D_SAI1_ROOT_CLK>,
738 <&clks IMX7D_CLK_DUMMY>,
739 <&clks IMX7D_CLK_DUMMY>;
740 clock-names = "bus", "mclk1", "mclk2", "mclk3";
741 dma-names = "rx", "tx";
742 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
747 #sound-dai-cells = <0>;
748 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
749 reg = <0x308b0000 0x10000>;
750 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
752 <&clks IMX7D_SAI2_ROOT_CLK>,
753 <&clks IMX7D_CLK_DUMMY>,
754 <&clks IMX7D_CLK_DUMMY>;
755 clock-names = "bus", "mclk1", "mclk2", "mclk3";
756 dma-names = "rx", "tx";
757 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
762 #sound-dai-cells = <0>;
763 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
764 reg = <0x308c0000 0x10000>;
765 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
767 <&clks IMX7D_SAI3_ROOT_CLK>,
768 <&clks IMX7D_CLK_DUMMY>,
769 <&clks IMX7D_CLK_DUMMY>;
770 clock-names = "bus", "mclk1", "mclk2", "mclk3";
771 dma-names = "rx", "tx";
772 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
776 flexcan1: can@30a00000 {
777 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
778 reg = <0x30a00000 0x10000>;
779 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&clks IMX7D_CLK_DUMMY>,
781 <&clks IMX7D_CAN1_ROOT_CLK>;
782 clock-names = "ipg", "per";
786 flexcan2: can@30a10000 {
787 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
788 reg = <0x30a10000 0x10000>;
789 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&clks IMX7D_CLK_DUMMY>,
791 <&clks IMX7D_CAN2_ROOT_CLK>;
792 clock-names = "ipg", "per";
797 #address-cells = <1>;
799 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
800 reg = <0x30a20000 0x10000>;
801 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
807 #address-cells = <1>;
809 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
810 reg = <0x30a30000 0x10000>;
811 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
817 #address-cells = <1>;
819 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
820 reg = <0x30a40000 0x10000>;
821 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
827 #address-cells = <1>;
829 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
830 reg = <0x30a50000 0x10000>;
831 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
836 uart4: serial@30a60000 {
837 compatible = "fsl,imx7d-uart",
839 reg = <0x30a60000 0x10000>;
840 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
842 <&clks IMX7D_UART4_ROOT_CLK>;
843 clock-names = "ipg", "per";
847 uart5: serial@30a70000 {
848 compatible = "fsl,imx7d-uart",
850 reg = <0x30a70000 0x10000>;
851 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
853 <&clks IMX7D_UART5_ROOT_CLK>;
854 clock-names = "ipg", "per";
858 uart6: serial@30a80000 {
859 compatible = "fsl,imx7d-uart",
861 reg = <0x30a80000 0x10000>;
862 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
863 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
864 <&clks IMX7D_UART6_ROOT_CLK>;
865 clock-names = "ipg", "per";
869 uart7: serial@30a90000 {
870 compatible = "fsl,imx7d-uart",
872 reg = <0x30a90000 0x10000>;
873 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
874 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
875 <&clks IMX7D_UART7_ROOT_CLK>;
876 clock-names = "ipg", "per";
880 usbotg1: usb@30b10000 {
881 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
882 reg = <0x30b10000 0x200>;
883 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
884 clocks = <&clks IMX7D_USB_CTRL_CLK>;
885 fsl,usbphy = <&usbphynop1>;
886 fsl,usbmisc = <&usbmisc1 0>;
887 phy-clkgate-delay-us = <400>;
892 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
893 reg = <0x30b30000 0x200>;
894 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
895 clocks = <&clks IMX7D_USB_CTRL_CLK>;
896 fsl,usbphy = <&usbphynop3>;
897 fsl,usbmisc = <&usbmisc3 0>;
900 phy-clkgate-delay-us = <400>;
904 usbmisc1: usbmisc@30b10200 {
906 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
907 reg = <0x30b10200 0x200>;
910 usbmisc3: usbmisc@30b30200 {
912 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
913 reg = <0x30b30200 0x200>;
916 usbphynop1: usbphynop1 {
917 compatible = "usb-nop-xceiv";
918 clocks = <&clks IMX7D_USB_PHY1_CLK>;
919 clock-names = "main_clk";
922 usbphynop3: usbphynop3 {
923 compatible = "usb-nop-xceiv";
924 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
925 clock-names = "main_clk";
928 usdhc1: usdhc@30b40000 {
929 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
930 reg = <0x30b40000 0x10000>;
931 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&clks IMX7D_CLK_DUMMY>,
933 <&clks IMX7D_CLK_DUMMY>,
934 <&clks IMX7D_USDHC1_ROOT_CLK>;
935 clock-names = "ipg", "ahb", "per";
940 usdhc2: usdhc@30b50000 {
941 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
942 reg = <0x30b50000 0x10000>;
943 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
944 clocks = <&clks IMX7D_CLK_DUMMY>,
945 <&clks IMX7D_CLK_DUMMY>,
946 <&clks IMX7D_USDHC2_ROOT_CLK>;
947 clock-names = "ipg", "ahb", "per";
952 usdhc3: usdhc@30b60000 {
953 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
954 reg = <0x30b60000 0x10000>;
955 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&clks IMX7D_CLK_DUMMY>,
957 <&clks IMX7D_CLK_DUMMY>,
958 <&clks IMX7D_USDHC3_ROOT_CLK>;
959 clock-names = "ipg", "ahb", "per";
964 sdma: sdma@30bd0000 {
965 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
966 reg = <0x30bd0000 0x10000>;
967 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&clks IMX7D_SDMA_CORE_CLK>,
969 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
970 clock-names = "ipg", "ahb";
972 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
975 fec1: ethernet@30be0000 {
976 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
977 reg = <0x30be0000 0x10000>;
978 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
982 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
983 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
984 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
985 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
986 clock-names = "ipg", "ahb", "ptp",
987 "enet_clk_ref", "enet_out";
988 fsl,num-tx-queues=<3>;
989 fsl,num-rx-queues=<3>;