arch/arm/boot/dts/imx7s.dtsi

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  * Copyright 2016 Toradex AG
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/clock/imx7d-clock.h>
  45 #include <dt-bindings/gpio/gpio.h>
  46 #include <dt-bindings/input/input.h>
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include "imx7d-pinfunc.h"
  49
  50 / {
  51         #address-cells = <1>;
  52         #size-cells = <1>;
  53
  54         aliases {
  55                 gpio0 = &gpio1;
  56                 gpio1 = &gpio2;
  57                 gpio2 = &gpio3;
  58                 gpio3 = &gpio4;
  59                 gpio4 = &gpio5;
  60                 gpio5 = &gpio6;
  61                 gpio6 = &gpio7;
  62                 i2c0 = &i2c1;
  63                 i2c1 = &i2c2;
  64                 i2c2 = &i2c3;
  65                 i2c3 = &i2c4;
  66                 mmc0 = &usdhc1;
  67                 mmc1 = &usdhc2;
  68                 mmc2 = &usdhc3;
  69                 serial0 = &uart1;
  70                 serial1 = &uart2;
  71                 serial2 = &uart3;
  72                 serial3 = &uart4;
  73                 serial4 = &uart5;
  74                 serial5 = &uart6;
  75                 serial6 = &uart7;
  76                 spi0 = &ecspi1;
  77                 spi1 = &ecspi2;
  78                 spi2 = &ecspi3;
  79                 spi3 = &ecspi4;
  80         };
  81
  82         cpus {
  83                 #address-cells = <1>;
  84                 #size-cells = <0>;
  85
  86                 cpu0: cpu@0 {
  87                         compatible = "arm,cortex-a7";
  88                         device_type = "cpu";
  89                         reg = <0>;
  90                         clock-frequency = <792000000>;
  91                         clock-latency = <61036>; /* two CLK32 periods */
  92                         clocks = <&clks IMX7D_CLK_ARM>;
  93                 };
  94         };
  95
  96         ckil: clock-cki {
  97                 compatible = "fixed-clock";
  98                 #clock-cells = <0>;
  99                 clock-frequency = <32768>;
 100                 clock-output-names = "ckil";
 101         };
 102
 103         osc: clock-osc {
 104                 compatible = "fixed-clock";
 105                 #clock-cells = <0>;
 106                 clock-frequency = <24000000>;
 107                 clock-output-names = "osc";
 108         };
 109
 110         soc {
 111                 #address-cells = <1>;
 112                 #size-cells = <1>;
 113                 compatible = "simple-bus";
 114                 interrupt-parent = <&intc>;
 115                 ranges;
 116
 117                 funnel@30041000 {
 118                         compatible = "arm,coresight-funnel", "arm,primecell";
 119                         reg = <0x30041000 0x1000>;
 120                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 121                         clock-names = "apb_pclk";
 122
 123                         ca_funnel_ports: ports {
 124                                 #address-cells = <1>;
 125                                 #size-cells = <0>;
 126
 127                                 /* funnel input ports */
 128                                 port@0 {
 129                                         reg = <0>;
 130                                         ca_funnel_in_port0: endpoint {
 131                                                 slave-mode;
 132                                                 remote-endpoint = <&etm0_out_port>;
 133                                         };
 134                                 };
 135
 136                                 /* funnel output port */
 137                                 port@2 {
 138                                         reg = <0>;
 139                                         ca_funnel_out_port0: endpoint {
 140                                                 remote-endpoint = <&hugo_funnel_in_port0>;
 141                                         };
 142                                 };
 143
 144                                 /* the other input ports are not connect to anything */
 145                         };
 146                 };
 147
 148                 etm@3007c000 {
 149                         compatible = "arm,coresight-etm3x", "arm,primecell";
 150                         reg = <0x3007c000 0x1000>;
 151                         cpu = <&cpu0>;
 152                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 153                         clock-names = "apb_pclk";
 154
 155                         port {
 156                                 etm0_out_port: endpoint {
 157                                         remote-endpoint = <&ca_funnel_in_port0>;
 158                                 };
 159                         };
 160                 };
 161
 162                 funnel@30083000 {
 163                         compatible = "arm,coresight-funnel", "arm,primecell";
 164                         reg = <0x30083000 0x1000>;
 165                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 166                         clock-names = "apb_pclk";
 167
 168                         ports {
 169                                 #address-cells = <1>;
 170                                 #size-cells = <0>;
 171
 172                                 /* funnel input ports */
 173                                 port@0 {
 174                                         reg = <0>;
 175                                         hugo_funnel_in_port0: endpoint {
 176                                                 slave-mode;
 177                                                 remote-endpoint = <&ca_funnel_out_port0>;
 178                                         };
 179                                 };
 180
 181                                 port@1 {
 182                                         reg = <1>;
 183                                         hugo_funnel_in_port1: endpoint {
 184                                                 slave-mode; /* M4 input */
 185                                         };
 186                                 };
 187
 188                                 port@2 {
 189                                         reg = <0>;
 190                                         hugo_funnel_out_port0: endpoint {
 191                                                 remote-endpoint = <&etf_in_port>;
 192                                         };
 193                                 };
 194
 195                                 /* the other input ports are not connect to anything */
 196                         };
 197                 };
 198
 199                 etf@30084000 {
 200                         compatible = "arm,coresight-tmc", "arm,primecell";
 201                         reg = <0x30084000 0x1000>;
 202                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 203                         clock-names = "apb_pclk";
 204
 205                         ports {
 206                                 #address-cells = <1>;
 207                                 #size-cells = <0>;
 208
 209                                 port@0 {
 210                                         reg = <0>;
 211                                         etf_in_port: endpoint {
 212                                                 slave-mode;
 213                                                 remote-endpoint = <&hugo_funnel_out_port0>;
 214                                         };
 215                                 };
 216
 217                                 port@1 {
 218                                         reg = <0>;
 219                                         etf_out_port: endpoint {
 220                                                 remote-endpoint = <&replicator_in_port0>;
 221                                         };
 222                                 };
 223                         };
 224                 };
 225
 226                 etr@30086000 {
 227                         compatible = "arm,coresight-tmc", "arm,primecell";
 228                         reg = <0x30086000 0x1000>;
 229                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 230                         clock-names = "apb_pclk";
 231
 232                         port {
 233                                 etr_in_port: endpoint {
 234                                         slave-mode;
 235                                         remote-endpoint = <&replicator_out_port1>;
 236                                 };
 237                         };
 238                 };
 239
 240                 tpiu@30087000 {
 241                         compatible = "arm,coresight-tpiu", "arm,primecell";
 242                         reg = <0x30087000 0x1000>;
 243                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 244                         clock-names = "apb_pclk";
 245
 246                         port {
 247                                 tpiu_in_port: endpoint {
 248                                         slave-mode;
 249                                         remote-endpoint = <&replicator_out_port1>;
 250                                 };
 251                         };
 252                 };
 253
 254                 replicator {
 255                         /*
 256                          * non-configurable replicators don't show up on the
 257                          * AMBA bus.  As such no need to add "arm,primecell"
 258                          */
 259                         compatible = "arm,coresight-replicator";
 260
 261                         ports {
 262                                 #address-cells = <1>;
 263                                 #size-cells = <0>;
 264
 265                                 /* replicator output ports */
 266                                 port@0 {
 267                                         reg = <0>;
 268                                         replicator_out_port0: endpoint {
 269                                                 remote-endpoint = <&tpiu_in_port>;
 270                                         };
 271                                 };
 272
 273                                 port@1 {
 274                                         reg = <1>;
 275                                         replicator_out_port1: endpoint {
 276                                                 remote-endpoint = <&etr_in_port>;
 277                                         };
 278                                 };
 279
 280                                 /* replicator input port */
 281                                 port@2 {
 282                                         reg = <0>;
 283                                         replicator_in_port0: endpoint {
 284                                                 slave-mode;
 285                                                 remote-endpoint = <&etf_out_port>;
 286                                         };
 287                                 };
 288                         };
 289                 };
 290
 291                 intc: interrupt-controller@31001000 {
 292                         compatible = "arm,cortex-a7-gic";
 293                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 294                         #interrupt-cells = <3>;
 295                         interrupt-controller;
 296                         reg = <0x31001000 0x1000>,
 297                               <0x31002000 0x2000>,
 298                               <0x31004000 0x2000>,
 299                               <0x31006000 0x2000>;
 300                 };
 301
 302                 timer {
 303                         compatible = "arm,armv7-timer";
 304                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 305                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 306                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 307                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 308                 };
 309
 310                 aips1: aips-bus@30000000 {
 311                         compatible = "fsl,aips-bus", "simple-bus";
 312                         #address-cells = <1>;
 313                         #size-cells = <1>;
 314                         reg = <0x30000000 0x400000>;
 315                         ranges;
 316
 317                         gpio1: gpio@30200000 {
 318                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 319                                 reg = <0x30200000 0x10000>;
 320                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
 321                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
 322                                 gpio-controller;
 323                                 #gpio-cells = <2>;
 324                                 interrupt-controller;
 325                                 #interrupt-cells = <2>;
 326                                 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
 327                         };
 328
 329                         gpio2: gpio@30210000 {
 330                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 331                                 reg = <0x30210000 0x10000>;
 332                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 333                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 334                                 gpio-controller;
 335                                 #gpio-cells = <2>;
 336                                 interrupt-controller;
 337                                 #interrupt-cells = <2>;
 338                                 gpio-ranges = <&iomuxc 0 13 32>;
 339                         };
 340
 341                         gpio3: gpio@30220000 {
 342                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 343                                 reg = <0x30220000 0x10000>;
 344                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 345                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 346                                 gpio-controller;
 347                                 #gpio-cells = <2>;
 348                                 interrupt-controller;
 349                                 #interrupt-cells = <2>;
 350                                 gpio-ranges = <&iomuxc 0 45 29>;
 351                         };
 352
 353                         gpio4: gpio@30230000 {
 354                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 355                                 reg = <0x30230000 0x10000>;
 356                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 357                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 358                                 gpio-controller;
 359                                 #gpio-cells = <2>;
 360                                 interrupt-controller;
 361                                 #interrupt-cells = <2>;
 362                                 gpio-ranges = <&iomuxc 0 74 24>;
 363                         };
 364
 365                         gpio5: gpio@30240000 {
 366                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 367                                 reg = <0x30240000 0x10000>;
 368                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 369                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 370                                 gpio-controller;
 371                                 #gpio-cells = <2>;
 372                                 interrupt-controller;
 373                                 #interrupt-cells = <2>;
 374                                 gpio-ranges = <&iomuxc 0 98 18>;
 375                         };
 376
 377                         gpio6: gpio@30250000 {
 378                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 379                                 reg = <0x30250000 0x10000>;
 380                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 381                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 382                                 gpio-controller;
 383                                 #gpio-cells = <2>;
 384                                 interrupt-controller;
 385                                 #interrupt-cells = <2>;
 386                                 gpio-ranges = <&iomuxc 0 116 23>;
 387                         };
 388
 389                         gpio7: gpio@30260000 {
 390                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 391                                 reg = <0x30260000 0x10000>;
 392                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 393                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 394                                 gpio-controller;
 395                                 #gpio-cells = <2>;
 396                                 interrupt-controller;
 397                                 #interrupt-cells = <2>;
 398                                 gpio-ranges = <&iomuxc 0 139 16>;
 399                         };
 400
 401                         wdog1: wdog@30280000 {
 402                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 403                                 reg = <0x30280000 0x10000>;
 404                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 405                                 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
 406                         };
 407
 408                         wdog2: wdog@30290000 {
 409                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 410                                 reg = <0x30290000 0x10000>;
 411                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 412                                 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
 413                                 status = "disabled";
 414                         };
 415
 416                         wdog3: wdog@302a0000 {
 417                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 418                                 reg = <0x302a0000 0x10000>;
 419                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 420                                 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
 421                                 status = "disabled";
 422                         };
 423
 424                         wdog4: wdog@302b0000 {
 425                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 426                                 reg = <0x302b0000 0x10000>;
 427                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 428                                 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
 429                                 status = "disabled";
 430                         };
 431
 432                         iomuxc_lpsr: iomuxc-lpsr@302c0000 {
 433                                 compatible = "fsl,imx7d-iomuxc-lpsr";
 434                                 reg = <0x302c0000 0x10000>;
 435                                 fsl,input-sel = <&iomuxc>;
 436                         };
 437
 438                         gpt1: gpt@302d0000 {
 439                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 440                                 reg = <0x302d0000 0x10000>;
 441                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 442                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 443                                          <&clks IMX7D_GPT1_ROOT_CLK>;
 444                                 clock-names = "ipg", "per";
 445                         };
 446
 447                         gpt2: gpt@302e0000 {
 448                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 449                                 reg = <0x302e0000 0x10000>;
 450                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 451                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 452                                          <&clks IMX7D_GPT2_ROOT_CLK>;
 453                                 clock-names = "ipg", "per";
 454                                 status = "disabled";
 455                         };
 456
 457                         gpt3: gpt@302f0000 {
 458                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 459                                 reg = <0x302f0000 0x10000>;
 460                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 461                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 462                                          <&clks IMX7D_GPT3_ROOT_CLK>;
 463                                 clock-names = "ipg", "per";
 464                                 status = "disabled";
 465                         };
 466
 467                         gpt4: gpt@30300000 {
 468                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 469                                 reg = <0x30300000 0x10000>;
 470                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 471                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 472                                          <&clks IMX7D_GPT4_ROOT_CLK>;
 473                                 clock-names = "ipg", "per";
 474                                 status = "disabled";
 475                         };
 476
 477                         iomuxc: iomuxc@30330000 {
 478                                 compatible = "fsl,imx7d-iomuxc";
 479                                 reg = <0x30330000 0x10000>;
 480                         };
 481
 482                         gpr: iomuxc-gpr@30340000 {
 483                                 compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
 484                                 reg = <0x30340000 0x10000>;
 485                         };
 486
 487                         ocotp: ocotp-ctrl@30350000 {
 488                                 compatible = "syscon";
 489                                 reg = <0x30350000 0x10000>;
 490                                 clocks = <&clks IMX7D_CLK_DUMMY>;
 491                                 status = "disabled";
 492                         };
 493
 494                         anatop: anatop@30360000 {
 495                                 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
 496                                         "syscon", "simple-bus";
 497                                 reg = <0x30360000 0x10000>;
 498                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 499                                         <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 500
 501                                 reg_1p0d: regulator-vdd1p0d {
 502                                         compatible = "fsl,anatop-regulator";
 503                                         regulator-name = "vdd1p0d";
 504                                         regulator-min-microvolt = <800000>;
 505                                         regulator-max-microvolt = <1200000>;
 506                                         anatop-reg-offset = <0x210>;
 507                                         anatop-vol-bit-shift = <8>;
 508                                         anatop-vol-bit-width = <5>;
 509                                         anatop-min-bit-val = <8>;
 510                                         anatop-min-voltage = <800000>;
 511                                         anatop-max-voltage = <1200000>;
 512                                         anatop-enable-bit = <31>;
 513                                 };
 514                         };
 515
 516                         snvs: snvs@30370000 {
 517                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 518                                 reg = <0x30370000 0x10000>;
 519
 520                                 snvs_rtc: snvs-rtc-lp {
 521                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 522                                         regmap = <&snvs>;
 523                                         offset = <0x34>;
 524                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 525                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 526                                 };
 527
 528                                 snvs_poweroff: snvs-poweroff {
 529                                         compatible = "syscon-poweroff";
 530                                         regmap = <&snvs>;
 531                                         offset = <0x38>;
 532                                         mask = <0x60>;
 533                                 };
 534
 535                                 snvs_pwrkey: snvs-powerkey {
 536                                         compatible = "fsl,sec-v4.0-pwrkey";
 537                                         regmap = <&snvs>;
 538                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 539                                         linux,keycode = <KEY_POWER>;
 540                                         wakeup-source;
 541                                 };
 542                         };
 543
 544                         clks: ccm@30380000 {
 545                                 compatible = "fsl,imx7d-ccm";
 546                                 reg = <0x30380000 0x10000>;
 547                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 548                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 549                                 #clock-cells = <1>;
 550                                 clocks = <&ckil>, <&osc>;
 551                                 clock-names = "ckil", "osc";
 552                         };
 553
 554                         src: src@30390000 {
 555                                 compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
 556                                 reg = <0x30390000 0x10000>;
 557                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 558                                 #reset-cells = <1>;
 559                         };
 560                 };
 561
 562                 aips2: aips-bus@30400000 {
 563                         compatible = "fsl,aips-bus", "simple-bus";
 564                         #address-cells = <1>;
 565                         #size-cells = <1>;
 566                         reg = <0x30400000 0x400000>;
 567                         ranges;
 568
 569                         adc1: adc@30610000 {
 570                                 compatible = "fsl,imx7d-adc";
 571                                 reg = <0x30610000 0x10000>;
 572                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 573                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
 574                                 clock-names = "adc";
 575                                 status = "disabled";
 576                         };
 577
 578                         adc2: adc@30620000 {
 579                                 compatible = "fsl,imx7d-adc";
 580                                 reg = <0x30620000 0x10000>;
 581                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 582                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
 583                                 clock-names = "adc";
 584                                 status = "disabled";
 585                         };
 586
 587                         ecspi4: ecspi@30630000 {
 588                                 #address-cells = <1>;
 589                                 #size-cells = <0>;
 590                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 591                                 reg = <0x30630000 0x10000>;
 592                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 593                                 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
 594                                         <&clks IMX7D_ECSPI4_ROOT_CLK>;
 595                                 clock-names = "ipg", "per";
 596                                 status = "disabled";
 597                         };
 598
 599                         pwm1: pwm@30660000 {
 600                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 601                                 reg = <0x30660000 0x10000>;
 602                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 603                                 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
 604                                          <&clks IMX7D_PWM1_ROOT_CLK>;
 605                                 clock-names = "ipg", "per";
 606                                 #pwm-cells = <2>;
 607                                 status = "disabled";
 608                         };
 609
 610                         pwm2: pwm@30670000 {
 611                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 612                                 reg = <0x30670000 0x10000>;
 613                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 614                                 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
 615                                          <&clks IMX7D_PWM2_ROOT_CLK>;
 616                                 clock-names = "ipg", "per";
 617                                 #pwm-cells = <2>;
 618                                 status = "disabled";
 619                         };
 620
 621                         pwm3: pwm@30680000 {
 622                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 623                                 reg = <0x30680000 0x10000>;
 624                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 625                                 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
 626                                          <&clks IMX7D_PWM3_ROOT_CLK>;
 627                                 clock-names = "ipg", "per";
 628                                 #pwm-cells = <2>;
 629                                 status = "disabled";
 630                         };
 631
 632                         pwm4: pwm@30690000 {
 633                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 634                                 reg = <0x30690000 0x10000>;
 635                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 636                                 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
 637                                          <&clks IMX7D_PWM4_ROOT_CLK>;
 638                                 clock-names = "ipg", "per";
 639                                 #pwm-cells = <2>;
 640                                 status = "disabled";
 641                         };
 642
 643                         lcdif: lcdif@30730000 {
 644                                 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
 645                                 reg = <0x30730000 0x10000>;
 646                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 647                                 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
 648                                         <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
 649                                 clock-names = "pix", "axi";
 650                                 status = "disabled";
 651                         };
 652                 };
 653
 654                 aips3: aips-bus@30800000 {
 655                         compatible = "fsl,aips-bus", "simple-bus";
 656                         #address-cells = <1>;
 657                         #size-cells = <1>;
 658                         reg = <0x30800000 0x400000>;
 659                         ranges;
 660
 661                         ecspi1: ecspi@30820000 {
 662                                 #address-cells = <1>;
 663                                 #size-cells = <0>;
 664                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 665                                 reg = <0x30820000 0x10000>;
 666                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 667                                 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
 668                                         <&clks IMX7D_ECSPI1_ROOT_CLK>;
 669                                 clock-names = "ipg", "per";
 670                                 status = "disabled";
 671                         };
 672
 673                         ecspi2: ecspi@30830000 {
 674                                 #address-cells = <1>;
 675                                 #size-cells = <0>;
 676                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 677                                 reg = <0x30830000 0x10000>;
 678                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 679                                 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
 680                                         <&clks IMX7D_ECSPI2_ROOT_CLK>;
 681                                 clock-names = "ipg", "per";
 682                                 status = "disabled";
 683                         };
 684
 685                         ecspi3: ecspi@30840000 {
 686                                 #address-cells = <1>;
 687                                 #size-cells = <0>;
 688                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 689                                 reg = <0x30840000 0x10000>;
 690                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 691                                 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
 692                                         <&clks IMX7D_ECSPI3_ROOT_CLK>;
 693                                 clock-names = "ipg", "per";
 694                                 status = "disabled";
 695                         };
 696
 697                         uart1: serial@30860000 {
 698                                 compatible = "fsl,imx7d-uart",
 699                                              "fsl,imx6q-uart";
 700                                 reg = <0x30860000 0x10000>;
 701                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 702                                 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
 703                                         <&clks IMX7D_UART1_ROOT_CLK>;
 704                                 clock-names = "ipg", "per";
 705                                 status = "disabled";
 706                         };
 707
 708                         uart2: serial@30890000 {
 709                                 compatible = "fsl,imx7d-uart",
 710                                              "fsl,imx6q-uart";
 711                                 reg = <0x30890000 0x10000>;
 712                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 713                                 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
 714                                         <&clks IMX7D_UART2_ROOT_CLK>;
 715                                 clock-names = "ipg", "per";
 716                                 status = "disabled";
 717                         };
 718
 719                         uart3: serial@30880000 {
 720                                 compatible = "fsl,imx7d-uart",
 721                                              "fsl,imx6q-uart";
 722                                 reg = <0x30880000 0x10000>;
 723                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 724                                 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
 725                                         <&clks IMX7D_UART3_ROOT_CLK>;
 726                                 clock-names = "ipg", "per";
 727                                 status = "disabled";
 728                         };
 729
 730                         sai1: sai@308a0000 {
 731                                 #sound-dai-cells = <0>;
 732                                 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 733                                 reg = <0x308a0000 0x10000>;
 734                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 735                                 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
 736                                          <&clks IMX7D_SAI1_ROOT_CLK>,
 737                                          <&clks IMX7D_CLK_DUMMY>,
 738                                          <&clks IMX7D_CLK_DUMMY>;
 739                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 740                                 dma-names = "rx", "tx";
 741                                 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
 742                                 status = "disabled";
 743                         };
 744
 745                         sai2: sai@308b0000 {
 746                                 #sound-dai-cells = <0>;
 747                                 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 748                                 reg = <0x308b0000 0x10000>;
 749                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 750                                 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
 751                                          <&clks IMX7D_SAI2_ROOT_CLK>,
 752                                          <&clks IMX7D_CLK_DUMMY>,
 753                                          <&clks IMX7D_CLK_DUMMY>;
 754                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 755                                 dma-names = "rx", "tx";
 756                                 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
 757                                 status = "disabled";
 758                         };
 759
 760                         sai3: sai@308c0000 {
 761                                 #sound-dai-cells = <0>;
 762                                 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 763                                 reg = <0x308c0000 0x10000>;
 764                                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 765                                 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
 766                                          <&clks IMX7D_SAI3_ROOT_CLK>,
 767                                          <&clks IMX7D_CLK_DUMMY>,
 768                                          <&clks IMX7D_CLK_DUMMY>;
 769                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 770                                 dma-names = "rx", "tx";
 771                                 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
 772                                 status = "disabled";
 773                         };
 774
 775                         flexcan1: can@30a00000 {
 776                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
 777                                 reg = <0x30a00000 0x10000>;
 778                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 779                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 780                                         <&clks IMX7D_CAN1_ROOT_CLK>;
 781                                 clock-names = "ipg", "per";
 782                                 status = "disabled";
 783                         };
 784
 785                         flexcan2: can@30a10000 {
 786                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
 787                                 reg = <0x30a10000 0x10000>;
 788                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 789                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 790                                         <&clks IMX7D_CAN2_ROOT_CLK>;
 791                                 clock-names = "ipg", "per";
 792                                 status = "disabled";
 793                         };
 794
 795                         i2c1: i2c@30a20000 {
 796                                 #address-cells = <1>;
 797                                 #size-cells = <0>;
 798                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 799                                 reg = <0x30a20000 0x10000>;
 800                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 801                                 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
 802                                 status = "disabled";
 803                         };
 804
 805                         i2c2: i2c@30a30000 {
 806                                 #address-cells = <1>;
 807                                 #size-cells = <0>;
 808                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 809                                 reg = <0x30a30000 0x10000>;
 810                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 811                                 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
 812                                 status = "disabled";
 813                         };
 814
 815                         i2c3: i2c@30a40000 {
 816                                 #address-cells = <1>;
 817                                 #size-cells = <0>;
 818                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 819                                 reg = <0x30a40000 0x10000>;
 820                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 821                                 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
 822                                 status = "disabled";
 823                         };
 824
 825                         i2c4: i2c@30a50000 {
 826                                 #address-cells = <1>;
 827                                 #size-cells = <0>;
 828                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 829                                 reg = <0x30a50000 0x10000>;
 830                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 831                                 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
 832                                 status = "disabled";
 833                         };
 834
 835                         uart4: serial@30a60000 {
 836                                 compatible = "fsl,imx7d-uart",
 837                                              "fsl,imx6q-uart";
 838                                 reg = <0x30a60000 0x10000>;
 839                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 840                                 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
 841                                         <&clks IMX7D_UART4_ROOT_CLK>;
 842                                 clock-names = "ipg", "per";
 843                                 status = "disabled";
 844                         };
 845
 846                         uart5: serial@30a70000 {
 847                                 compatible = "fsl,imx7d-uart",
 848                                              "fsl,imx6q-uart";
 849                                 reg = <0x30a70000 0x10000>;
 850                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 851                                 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
 852                                         <&clks IMX7D_UART5_ROOT_CLK>;
 853                                 clock-names = "ipg", "per";
 854                                 status = "disabled";
 855                         };
 856
 857                         uart6: serial@30a80000 {
 858                                 compatible = "fsl,imx7d-uart",
 859                                              "fsl,imx6q-uart";
 860                                 reg = <0x30a80000 0x10000>;
 861                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 862                                 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
 863                                         <&clks IMX7D_UART6_ROOT_CLK>;
 864                                 clock-names = "ipg", "per";
 865                                 status = "disabled";
 866                         };
 867
 868                         uart7: serial@30a90000 {
 869                                 compatible = "fsl,imx7d-uart",
 870                                              "fsl,imx6q-uart";
 871                                 reg = <0x30a90000 0x10000>;
 872                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 873                                 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
 874                                         <&clks IMX7D_UART7_ROOT_CLK>;
 875                                 clock-names = "ipg", "per";
 876                                 status = "disabled";
 877                         };
 878
 879                         usbotg1: usb@30b10000 {
 880                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 881                                 reg = <0x30b10000 0x200>;
 882                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 883                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
 884                                 fsl,usbphy = <&usbphynop1>;
 885                                 fsl,usbmisc = <&usbmisc1 0>;
 886                                 phy-clkgate-delay-us = <400>;
 887                                 status = "disabled";
 888                         };
 889
 890                         usbh: usb@30b30000 {
 891                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 892                                 reg = <0x30b30000 0x200>;
 893                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 894                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
 895                                 fsl,usbphy = <&usbphynop3>;
 896                                 fsl,usbmisc = <&usbmisc3 0>;
 897                                 phy_type = "hsic";
 898                                 dr_mode = "host";
 899                                 phy-clkgate-delay-us = <400>;
 900                                 status = "disabled";
 901                         };
 902
 903                         usbmisc1: usbmisc@30b10200 {
 904                                 #index-cells = <1>;
 905                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
 906                                 reg = <0x30b10200 0x200>;
 907                         };
 908
 909                         usbmisc3: usbmisc@30b30200 {
 910                                 #index-cells = <1>;
 911                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
 912                                 reg = <0x30b30200 0x200>;
 913                         };
 914
 915                         usbphynop1: usbphynop1 {
 916                                 compatible = "usb-nop-xceiv";
 917                                 clocks = <&clks IMX7D_USB_PHY1_CLK>;
 918                                 clock-names = "main_clk";
 919                         };
 920
 921                         usbphynop3: usbphynop3 {
 922                                 compatible = "usb-nop-xceiv";
 923                                 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
 924                                 clock-names = "main_clk";
 925                         };
 926
 927                         usdhc1: usdhc@30b40000 {
 928                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 929                                 reg = <0x30b40000 0x10000>;
 930                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 931                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 932                                         <&clks IMX7D_CLK_DUMMY>,
 933                                         <&clks IMX7D_USDHC1_ROOT_CLK>;
 934                                 clock-names = "ipg", "ahb", "per";
 935                                 bus-width = <4>;
 936                                 status = "disabled";
 937                         };
 938
 939                         usdhc2: usdhc@30b50000 {
 940                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 941                                 reg = <0x30b50000 0x10000>;
 942                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 943                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 944                                         <&clks IMX7D_CLK_DUMMY>,
 945                                         <&clks IMX7D_USDHC2_ROOT_CLK>;
 946                                 clock-names = "ipg", "ahb", "per";
 947                                 bus-width = <4>;
 948                                 status = "disabled";
 949                         };
 950
 951                         usdhc3: usdhc@30b60000 {
 952                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 953                                 reg = <0x30b60000 0x10000>;
 954                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 955                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 956                                         <&clks IMX7D_CLK_DUMMY>,
 957                                         <&clks IMX7D_USDHC3_ROOT_CLK>;
 958                                 clock-names = "ipg", "ahb", "per";
 959                                 bus-width = <4>;
 960                                 status = "disabled";
 961                         };
 962
 963                         sdma: sdma@30bd0000 {
 964                                 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
 965                                 reg = <0x30bd0000 0x10000>;
 966                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 967                                 clocks = <&clks IMX7D_SDMA_CORE_CLK>,
 968                                          <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
 969                                 clock-names = "ipg", "ahb";
 970                                 #dma-cells = <3>;
 971                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 972                         };
 973
 974                         fec1: ethernet@30be0000 {
 975                                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
 976                                 reg = <0x30be0000 0x10000>;
 977                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 978                                         <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 979                                         <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 980                                 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
 981                                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
 982                                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
 983                                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
 984                                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
 985                                 clock-names = "ipg", "ahb", "ptp",
 986                                         "enet_clk_ref", "enet_out";
 987                                 fsl,num-tx-queues=<3>;
 988                                 fsl,num-rx-queues=<3>;
 989                                 status = "disabled";
 990                         };
 991                 };
 992         };
 993 };