2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Erin.Lo <erin.lo@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <dt-bindings/clock/mt2701-clk.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/power/mt2701-power.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/memory/mt2701-larb-port.h>
21 #include <dt-bindings/reset/mt2701-resets.h>
22 #include "skeleton64.dtsi"
23 #include "mt2701-pinfunc.h"
26 compatible = "mediatek,mt2701";
27 interrupt-parent = <&cirq>;
32 enable-method = "mediatek,mt81xx-tz-smp";
36 compatible = "arm,cortex-a7";
41 compatible = "arm,cortex-a7";
46 compatible = "arm,cortex-a7";
51 compatible = "arm,cortex-a7";
61 trustzone-bootinfo@80002000 {
62 compatible = "mediatek,trustzone-bootinfo";
63 reg = <0 0x80002000 0 0x1000>;
67 system_clk: dummy13m {
68 compatible = "fixed-clock";
69 clock-frequency = <13000000>;
74 compatible = "fixed-clock";
75 clock-frequency = <32000>;
79 clk26m: oscillator@0 {
80 compatible = "fixed-clock";
82 clock-frequency = <26000000>;
83 clock-output-names = "clk26m";
86 rtc32k: oscillator@1 {
87 compatible = "fixed-clock";
89 clock-frequency = <32000>;
90 clock-output-names = "rtc32k";
94 cpu_thermal: cpu_thermal {
95 polling-delay-passive = <1000>; /* milliseconds */
96 polling-delay = <1000>; /* milliseconds */
98 thermal-sensors = <&thermal 0>;
99 sustainable-power = <1000>;
102 threshold: trip-point@0 {
103 temperature = <68000>;
108 target: trip-point@1 {
109 temperature = <85000>;
114 cpu_crit: cpu_crit@0 {
115 temperature = <115000>;
124 compatible = "arm,armv7-timer";
125 interrupt-parent = <&gic>;
126 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
127 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
129 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
132 topckgen: syscon@10000000 {
133 compatible = "mediatek,mt2701-topckgen", "syscon";
134 reg = <0 0x10000000 0 0x1000>;
138 infracfg: syscon@10001000 {
139 compatible = "mediatek,mt2701-infracfg", "syscon";
140 reg = <0 0x10001000 0 0x1000>;
145 pericfg: syscon@10003000 {
146 compatible = "mediatek,mt2701-pericfg", "syscon";
147 reg = <0 0x10003000 0 0x1000>;
152 syscfg_pctl_a: syscfg@10005000 {
153 compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
154 reg = <0 0x10005000 0 0x1000>;
157 scpsys: scpsys@10006000 {
158 compatible = "mediatek,mt2701-scpsys", "syscon";
159 #power-domain-cells = <1>;
160 reg = <0 0x10006000 0 0x1000>;
161 infracfg = <&infracfg>;
162 clocks = <&topckgen CLK_TOP_MM_SEL>,
163 <&topckgen CLK_TOP_MFG_SEL>,
164 <&topckgen CLK_TOP_ETHIF_SEL>;
165 clock-names = "mm", "mfg", "ethif";
168 watchdog: watchdog@10007000 {
169 compatible = "mediatek,mt2701-wdt",
170 "mediatek,mt6589-wdt";
171 reg = <0 0x10007000 0 0x100>;
174 timer: timer@10008000 {
175 compatible = "mediatek,mt2701-timer",
176 "mediatek,mt6577-timer";
177 reg = <0 0x10008000 0 0x80>;
178 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
179 clocks = <&system_clk>, <&rtc_clk>;
180 clock-names = "system-clk", "rtc-clk";
183 pio: pinctrl@1000b000 {
184 compatible = "mediatek,mt2701-pinctrl";
185 reg = <0 0x1000b000 0 0x1000>;
186 mediatek,pctl-regmap = <&syscfg_pctl_a>;
190 interrupt-controller;
191 #interrupt-cells = <2>;
192 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
196 smi_common: smi@1000c000 {
197 compatible = "mediatek,mt2701-smi-common";
198 reg = <0 0x1000c000 0 0x1000>;
199 clocks = <&infracfg CLK_INFRA_SMI>,
200 <&mmsys CLK_MM_SMI_COMMON>,
201 <&infracfg CLK_INFRA_SMI>;
202 clock-names = "apb", "smi", "async";
203 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
206 sysirq: interrupt-controller@10200100 {
207 compatible = "mediatek,mt2701-sysirq",
208 "mediatek,mt6577-sysirq";
209 interrupt-controller;
210 #interrupt-cells = <3>;
211 interrupt-parent = <&gic>;
212 reg = <0 0x10200100 0 0x1c>;
215 cirq: interrupt-controller@10204000 {
216 compatible = "mediatek,mt2701-cirq",
218 interrupt-controller;
219 #interrupt-cells = <3>;
220 interrupt-parent = <&sysirq>;
221 reg = <0 0x10204000 0 0x400>;
222 mediatek,ext-irq-range = <32 200>;
225 iommu: mmsys_iommu@10205000 {
226 compatible = "mediatek,mt2701-m4u";
227 reg = <0 0x10205000 0 0x1000>;
228 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
229 clocks = <&infracfg CLK_INFRA_M4U>;
230 clock-names = "bclk";
231 mediatek,larbs = <&larb0 &larb1 &larb2>;
235 apmixedsys: syscon@10209000 {
236 compatible = "mediatek,mt2701-apmixedsys", "syscon";
237 reg = <0 0x10209000 0 0x1000>;
241 gic: interrupt-controller@10211000 {
242 compatible = "arm,cortex-a7-gic";
243 interrupt-controller;
244 #interrupt-cells = <3>;
245 interrupt-parent = <&gic>;
246 reg = <0 0x10211000 0 0x1000>,
247 <0 0x10212000 0 0x2000>,
248 <0 0x10214000 0 0x2000>,
249 <0 0x10216000 0 0x2000>;
252 auxadc: adc@11001000 {
253 compatible = "mediatek,mt2701-auxadc";
254 reg = <0 0x11001000 0 0x1000>;
255 clocks = <&pericfg CLK_PERI_AUXADC>;
256 clock-names = "main";
257 #io-channel-cells = <1>;
261 uart0: serial@11002000 {
262 compatible = "mediatek,mt2701-uart",
263 "mediatek,mt6577-uart";
264 reg = <0 0x11002000 0 0x400>;
265 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
266 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
267 clock-names = "baud", "bus";
271 uart1: serial@11003000 {
272 compatible = "mediatek,mt2701-uart",
273 "mediatek,mt6577-uart";
274 reg = <0 0x11003000 0 0x400>;
275 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
276 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
277 clock-names = "baud", "bus";
281 uart2: serial@11004000 {
282 compatible = "mediatek,mt2701-uart",
283 "mediatek,mt6577-uart";
284 reg = <0 0x11004000 0 0x400>;
285 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
286 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
287 clock-names = "baud", "bus";
291 uart3: serial@11005000 {
292 compatible = "mediatek,mt2701-uart",
293 "mediatek,mt6577-uart";
294 reg = <0 0x11005000 0 0x400>;
295 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
296 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
297 clock-names = "baud", "bus";
302 compatible = "mediatek,mt2701-i2c",
303 "mediatek,mt6577-i2c";
304 reg = <0 0x11007000 0 0x70>,
305 <0 0x11000200 0 0x80>;
306 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
308 clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
309 clock-names = "main", "dma";
310 #address-cells = <1>;
316 compatible = "mediatek,mt2701-i2c",
317 "mediatek,mt6577-i2c";
318 reg = <0 0x11008000 0 0x70>,
319 <0 0x11000280 0 0x80>;
320 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
322 clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
323 clock-names = "main", "dma";
324 #address-cells = <1>;
330 compatible = "mediatek,mt2701-i2c",
331 "mediatek,mt6577-i2c";
332 reg = <0 0x11009000 0 0x70>,
333 <0 0x11000300 0 0x80>;
334 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
336 clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
337 clock-names = "main", "dma";
338 #address-cells = <1>;
344 compatible = "mediatek,mt2701-spi";
345 #address-cells = <1>;
347 reg = <0 0x1100a000 0 0x100>;
348 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
349 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
350 <&topckgen CLK_TOP_SPI0_SEL>,
351 <&pericfg CLK_PERI_SPI0>;
352 clock-names = "parent-clk", "sel-clk", "spi-clk";
356 thermal: thermal@1100b000 {
357 #thermal-sensor-cells = <0>;
358 compatible = "mediatek,mt2701-thermal";
359 reg = <0 0x1100b000 0 0x1000>;
360 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
361 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
362 clock-names = "therm", "auxadc";
363 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
364 reset-names = "therm";
365 mediatek,auxadc = <&auxadc>;
366 mediatek,apmixedsys = <&apmixedsys>;
369 nandc: nfi@1100d000 {
370 compatible = "mediatek,mt2701-nfc";
371 reg = <0 0x1100d000 0 0x1000>;
372 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
373 clocks = <&pericfg CLK_PERI_NFI>,
374 <&pericfg CLK_PERI_NFI_PAD>;
375 clock-names = "nfi_clk", "pad_clk";
378 #address-cells = <1>;
383 compatible = "mediatek,mt2701-ecc";
384 reg = <0 0x1100e000 0 0x1000>;
385 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
386 clocks = <&pericfg CLK_PERI_NFI_ECC>;
387 clock-names = "nfiecc_clk";
391 nor_flash: spi@11014000 {
392 compatible = "mediatek,mt2701-nor",
393 "mediatek,mt8173-nor";
394 reg = <0 0x11014000 0 0xe0>;
395 clocks = <&pericfg CLK_PERI_FLASH>,
396 <&topckgen CLK_TOP_FLASH_SEL>;
397 clock-names = "spi", "sf";
398 #address-cells = <1>;
404 compatible = "mediatek,mt2701-spi";
405 #address-cells = <1>;
407 reg = <0 0x11016000 0 0x100>;
408 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
409 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
410 <&topckgen CLK_TOP_SPI1_SEL>,
411 <&pericfg CLK_PERI_SPI1>;
412 clock-names = "parent-clk", "sel-clk", "spi-clk";
417 compatible = "mediatek,mt2701-spi";
418 #address-cells = <1>;
420 reg = <0 0x11017000 0 0x1000>;
421 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
422 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
423 <&topckgen CLK_TOP_SPI2_SEL>,
424 <&pericfg CLK_PERI_SPI2>;
425 clock-names = "parent-clk", "sel-clk", "spi-clk";
429 audsys: clock-controller@11220000 {
430 compatible = "mediatek,mt2701-audsys", "syscon";
431 reg = <0 0x11220000 0 0x2000>;
434 afe: audio-controller {
435 compatible = "mediatek,mt2701-audio";
436 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
437 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
438 interrupt-names = "afe", "asys";
439 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
441 clocks = <&infracfg CLK_INFRA_AUDIO>,
442 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
443 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
444 <&topckgen CLK_TOP_AUD_48K_TIMING>,
445 <&topckgen CLK_TOP_AUD_44K_TIMING>,
446 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
447 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
448 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
449 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
450 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
451 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
452 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
453 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
454 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
455 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
456 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
457 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
458 <&audsys CLK_AUD_I2SO1>,
459 <&audsys CLK_AUD_I2SO2>,
460 <&audsys CLK_AUD_I2SO3>,
461 <&audsys CLK_AUD_I2SO4>,
462 <&audsys CLK_AUD_I2SIN1>,
463 <&audsys CLK_AUD_I2SIN2>,
464 <&audsys CLK_AUD_I2SIN3>,
465 <&audsys CLK_AUD_I2SIN4>,
466 <&audsys CLK_AUD_ASRCO1>,
467 <&audsys CLK_AUD_ASRCO2>,
468 <&audsys CLK_AUD_ASRCO3>,
469 <&audsys CLK_AUD_ASRCO4>,
470 <&audsys CLK_AUD_AFE>,
471 <&audsys CLK_AUD_AFE_CONN>,
472 <&audsys CLK_AUD_A1SYS>,
473 <&audsys CLK_AUD_A2SYS>,
474 <&audsys CLK_AUD_AFE_MRGIF>;
476 clock-names = "infra_sys_audio_clk",
477 "top_audio_mux1_sel",
478 "top_audio_mux2_sel",
479 "top_audio_a1sys_hp",
480 "top_audio_a2sys_hp",
511 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
512 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
513 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
514 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
515 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
516 <&topckgen CLK_TOP_AUD2PLL_90M>;
517 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
521 mmsys: syscon@14000000 {
522 compatible = "mediatek,mt2701-mmsys", "syscon";
523 reg = <0 0x14000000 0 0x1000>;
528 compatible = "mediatek,mt2701-disp-pwm";
529 reg = <0 0x1400a000 0 0x1000>;
531 clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>;
532 clock-names = "main", "mm";
536 larb0: larb@14010000 {
537 compatible = "mediatek,mt2701-smi-larb";
538 reg = <0 0x14010000 0 0x1000>;
539 mediatek,smi = <&smi_common>;
540 mediatek,larb-id = <0>;
541 clocks = <&mmsys CLK_MM_SMI_LARB0>,
542 <&mmsys CLK_MM_SMI_LARB0>;
543 clock-names = "apb", "smi";
544 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
547 imgsys: syscon@15000000 {
548 compatible = "mediatek,mt2701-imgsys", "syscon";
549 reg = <0 0x15000000 0 0x1000>;
553 larb2: larb@15001000 {
554 compatible = "mediatek,mt2701-smi-larb";
555 reg = <0 0x15001000 0 0x1000>;
556 mediatek,smi = <&smi_common>;
557 mediatek,larb-id = <2>;
558 clocks = <&imgsys CLK_IMG_SMI_COMM>,
559 <&imgsys CLK_IMG_SMI_COMM>;
560 clock-names = "apb", "smi";
561 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
564 jpegdec: jpegdec@15004000 {
565 compatible = "mediatek,mt2701-jpgdec";
566 reg = <0 0x15004000 0 0x1000>;
567 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
568 clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
569 <&imgsys CLK_IMG_JPGDEC>;
570 clock-names = "jpgdec-smi",
572 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
573 mediatek,larb = <&larb2>;
574 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
575 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
578 vdecsys: syscon@16000000 {
579 compatible = "mediatek,mt2701-vdecsys", "syscon";
580 reg = <0 0x16000000 0 0x1000>;
584 larb1: larb@16010000 {
585 compatible = "mediatek,mt2701-smi-larb";
586 reg = <0 0x16010000 0 0x1000>;
587 mediatek,smi = <&smi_common>;
588 mediatek,larb-id = <1>;
589 clocks = <&vdecsys CLK_VDEC_CKGEN>,
590 <&vdecsys CLK_VDEC_LARB>;
591 clock-names = "apb", "smi";
592 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
595 hifsys: syscon@1a000000 {
596 compatible = "mediatek,mt2701-hifsys", "syscon";
597 reg = <0 0x1a000000 0 0x1000>;
603 compatible = "mediatek,mt8173-xhci";
604 reg = <0 0x1a1c0000 0 0x1000>,
605 <0 0x1a1c4700 0 0x0100>;
606 reg-names = "mac", "ippc";
607 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
608 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
609 <&topckgen CLK_TOP_ETHIF_SEL>;
610 clock-names = "sys_ck", "ref_ck";
611 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
612 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
616 u3phy0: usb-phy@1a1c4000 {
617 compatible = "mediatek,mt2701-u3phy";
618 reg = <0 0x1a1c4000 0 0x0700>;
619 #address-cells = <2>;
624 u2port0: usb-phy@1a1c4800 {
625 reg = <0 0x1a1c4800 0 0x0100>;
626 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
632 u3port0: usb-phy@1a1c4900 {
633 reg = <0 0x1a1c4900 0 0x0700>;
642 compatible = "mediatek,mt8173-xhci";
643 reg = <0 0x1a240000 0 0x1000>,
644 <0 0x1a244700 0 0x0100>;
645 reg-names = "mac", "ippc";
646 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
647 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
648 <&topckgen CLK_TOP_ETHIF_SEL>;
649 clock-names = "sys_ck", "ref_ck";
650 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
651 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
655 u3phy1: usb-phy@1a244000 {
656 compatible = "mediatek,mt2701-u3phy";
657 reg = <0 0x1a244000 0 0x0700>;
658 #address-cells = <2>;
663 u2port1: usb-phy@1a244800 {
664 reg = <0 0x1a244800 0 0x0100>;
665 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
671 u3port1: usb-phy@1a244900 {
672 reg = <0 0x1a244900 0 0x0700>;
680 ethsys: syscon@1b000000 {
681 compatible = "mediatek,mt2701-ethsys", "syscon";
682 reg = <0 0x1b000000 0 0x1000>;
687 eth: ethernet@1b100000 {
688 compatible = "mediatek,mt2701-eth", "syscon";
689 reg = <0 0x1b100000 0 0x20000>;
690 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
691 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
692 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
693 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
694 <ðsys CLK_ETHSYS_ESW>,
695 <ðsys CLK_ETHSYS_GP1>,
696 <ðsys CLK_ETHSYS_GP2>,
697 <&apmixedsys CLK_APMIXED_TRGPLL>;
698 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
699 resets = <ðsys MT2701_ETHSYS_FE_RST>,
700 <ðsys MT2701_ETHSYS_GMAC_RST>,
701 <ðsys MT2701_ETHSYS_PPE_RST>;
702 reset-names = "fe", "gmac", "ppe";
703 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
704 mediatek,ethsys = <ðsys>;
705 mediatek,pctl = <&syscfg_pctl_a>;
706 #address-cells = <1>;
711 bdpsys: syscon@1c000000 {
712 compatible = "mediatek,mt2701-bdpsys", "syscon";
713 reg = <0 0x1c000000 0 0x1000>;