arch/arm/boot/dts/omap4-l4-abe.dtsi

   1 &l4_abe {                                               /* 0x40100000 */
   2         compatible = "ti,omap4-l4-abe", "simple-bus";
   3         reg = <0x40100000 0x400>,
   4               <0x40100400 0x400>;
   5         reg-names = "la", "ap";
   6         #address-cells = <1>;
   7         #size-cells = <1>;
   8         ranges = <0x00000000 0x40100000 0x100000>,      /* segment 0 */
   9                  <0x49000000 0x49000000 0x100000>;
  10         segment@0 {                                     /* 0x40100000 */
  11                 compatible = "simple-bus";
  12                 #address-cells = <1>;
  13                 #size-cells = <1>;
  14                 ranges =
  15                          /* CPU to L4 ABE mapping */
  16                          <0x00000000 0x00000000 0x000400>,      /* ap 0 */
  17                          <0x00000400 0x00000400 0x000400>,      /* ap 1 */
  18                          <0x00022000 0x00022000 0x001000>,      /* ap 2 */
  19                          <0x00023000 0x00023000 0x001000>,      /* ap 3 */
  20                          <0x00024000 0x00024000 0x001000>,      /* ap 4 */
  21                          <0x00025000 0x00025000 0x001000>,      /* ap 5 */
  22                          <0x00026000 0x00026000 0x001000>,      /* ap 6 */
  23                          <0x00027000 0x00027000 0x001000>,      /* ap 7 */
  24                          <0x00028000 0x00028000 0x001000>,      /* ap 8 */
  25                          <0x00029000 0x00029000 0x001000>,      /* ap 9 */
  26                          <0x0002a000 0x0002a000 0x001000>,      /* ap 10 */
  27                          <0x0002b000 0x0002b000 0x001000>,      /* ap 11 */
  28                          <0x0002e000 0x0002e000 0x001000>,      /* ap 12 */
  29                          <0x0002f000 0x0002f000 0x001000>,      /* ap 13 */
  30                          <0x00030000 0x00030000 0x001000>,      /* ap 14 */
  31                          <0x00031000 0x00031000 0x001000>,      /* ap 15 */
  32                          <0x00032000 0x00032000 0x001000>,      /* ap 16 */
  33                          <0x00033000 0x00033000 0x001000>,      /* ap 17 */
  34                          <0x00038000 0x00038000 0x001000>,      /* ap 18 */
  35                          <0x00039000 0x00039000 0x001000>,      /* ap 19 */
  36                          <0x0003a000 0x0003a000 0x001000>,      /* ap 20 */
  37                          <0x0003b000 0x0003b000 0x001000>,      /* ap 21 */
  38                          <0x0003c000 0x0003c000 0x001000>,      /* ap 22 */
  39                          <0x0003d000 0x0003d000 0x001000>,      /* ap 23 */
  40                          <0x0003e000 0x0003e000 0x001000>,      /* ap 24 */
  41                          <0x0003f000 0x0003f000 0x001000>,      /* ap 25 */
  42                          <0x00080000 0x00080000 0x010000>,      /* ap 26 */
  43                          <0x00080000 0x00080000 0x001000>,      /* ap 27 */
  44                          <0x000a0000 0x000a0000 0x010000>,      /* ap 28 */
  45                          <0x000a0000 0x000a0000 0x001000>,      /* ap 29 */
  46                          <0x000c0000 0x000c0000 0x010000>,      /* ap 30 */
  47                          <0x000c0000 0x000c0000 0x001000>,      /* ap 31 */
  48                          <0x000f1000 0x000f1000 0x001000>,      /* ap 32 */
  49                          <0x000f2000 0x000f2000 0x001000>,      /* ap 33 */
  50
  51                          /* L3 to L4 ABE mapping */
  52                          <0x49000000 0x49000000 0x000400>,      /* ap 0 */
  53                          <0x49000400 0x49000400 0x000400>,      /* ap 1 */
  54                          <0x49022000 0x49022000 0x001000>,      /* ap 2 */
  55                          <0x49023000 0x49023000 0x001000>,      /* ap 3 */
  56                          <0x49024000 0x49024000 0x001000>,      /* ap 4 */
  57                          <0x49025000 0x49025000 0x001000>,      /* ap 5 */
  58                          <0x49026000 0x49026000 0x001000>,      /* ap 6 */
  59                          <0x49027000 0x49027000 0x001000>,      /* ap 7 */
  60                          <0x49028000 0x49028000 0x001000>,      /* ap 8 */
  61                          <0x49029000 0x49029000 0x001000>,      /* ap 9 */
  62                          <0x4902a000 0x4902a000 0x001000>,      /* ap 10 */
  63                          <0x4902b000 0x4902b000 0x001000>,      /* ap 11 */
  64                          <0x4902e000 0x4902e000 0x001000>,      /* ap 12 */
  65                          <0x4902f000 0x4902f000 0x001000>,      /* ap 13 */
  66                          <0x49030000 0x49030000 0x001000>,      /* ap 14 */
  67                          <0x49031000 0x49031000 0x001000>,      /* ap 15 */
  68                          <0x49032000 0x49032000 0x001000>,      /* ap 16 */
  69                          <0x49033000 0x49033000 0x001000>,      /* ap 17 */
  70                          <0x49038000 0x49038000 0x001000>,      /* ap 18 */
  71                          <0x49039000 0x49039000 0x001000>,      /* ap 19 */
  72                          <0x4903a000 0x4903a000 0x001000>,      /* ap 20 */
  73                          <0x4903b000 0x4903b000 0x001000>,      /* ap 21 */
  74                          <0x4903c000 0x4903c000 0x001000>,      /* ap 22 */
  75                          <0x4903d000 0x4903d000 0x001000>,      /* ap 23 */
  76                          <0x4903e000 0x4903e000 0x001000>,      /* ap 24 */
  77                          <0x4903f000 0x4903f000 0x001000>,      /* ap 25 */
  78                          <0x49080000 0x49080000 0x010000>,      /* ap 26 */
  79                          <0x49080000 0x49080000 0x001000>,      /* ap 27 */
  80                          <0x490a0000 0x490a0000 0x010000>,      /* ap 28 */
  81                          <0x490a0000 0x490a0000 0x001000>,      /* ap 29 */
  82                          <0x490c0000 0x490c0000 0x010000>,      /* ap 30 */
  83                          <0x490c0000 0x490c0000 0x001000>,      /* ap 31 */
  84                          <0x490f1000 0x490f1000 0x001000>,      /* ap 32 */
  85                          <0x490f2000 0x490f2000 0x001000>;      /* ap 33 */
  86
  87                 target-module@22000 {                   /* 0x40122000, ap 2 02.0 */
  88                         compatible = "ti,sysc-omap2", "ti,sysc";
  89                         reg = <0x2208c 0x4>;
  90                         reg-names = "sysc";
  91                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  92                                          SYSC_OMAP2_ENAWAKEUP |
  93                                          SYSC_OMAP2_SOFTRESET)>;
  94                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  95                                         <SYSC_IDLE_NO>,
  96                                         <SYSC_IDLE_SMART>;
  97                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
  98                         clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
  99                         clock-names = "fck";
 100                         #address-cells = <1>;
 101                         #size-cells = <1>;
 102                         ranges = <0x0 0x22000 0x1000>,
 103                                  <0x49022000 0x49022000 0x1000>;
 104
 105                         mcbsp1: mcbsp@0 {
 106                                 compatible = "ti,omap4-mcbsp";
 107                                 reg = <0x0 0xff>, /* MPU private access */
 108                                       <0x49022000 0xff>; /* L3 Interconnect */
 109                                 reg-names = "mpu", "dma";
 110                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 111                                 interrupt-names = "common";
 112                                 ti,buffer-size = <128>;
 113                                 dmas = <&sdma 33>,
 114                                        <&sdma 34>;
 115                                 dma-names = "tx", "rx";
 116                                 status = "disabled";
 117                         };
 118                 };
 119
 120                 target-module@24000 {                   /* 0x40124000, ap 4 04.0 */
 121                         compatible = "ti,sysc-omap2", "ti,sysc";
 122                         reg = <0x2408c 0x4>;
 123                         reg-names = "sysc";
 124                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 125                                          SYSC_OMAP2_ENAWAKEUP |
 126                                          SYSC_OMAP2_SOFTRESET)>;
 127                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 128                                         <SYSC_IDLE_NO>,
 129                                         <SYSC_IDLE_SMART>;
 130                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 131                         clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
 132                         clock-names = "fck";
 133                         #address-cells = <1>;
 134                         #size-cells = <1>;
 135                         ranges = <0x0 0x24000 0x1000>,
 136                                  <0x49024000 0x49024000 0x1000>;
 137
 138                         mcbsp2: mcbsp@0 {
 139                                 compatible = "ti,omap4-mcbsp";
 140                                 reg = <0x0 0xff>, /* MPU private access */
 141                                       <0x49024000 0xff>; /* L3 Interconnect */
 142                                 reg-names = "mpu", "dma";
 143                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 144                                 interrupt-names = "common";
 145                                 ti,buffer-size = <128>;
 146                                 dmas = <&sdma 17>,
 147                                        <&sdma 18>;
 148                                 dma-names = "tx", "rx";
 149                                 status = "disabled";
 150                         };
 151                 };
 152
 153                 target-module@26000 {                   /* 0x40126000, ap 6 06.0 */
 154                         compatible = "ti,sysc-omap2", "ti,sysc";
 155                         reg = <0x2608c 0x4>;
 156                         reg-names = "sysc";
 157                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 158                                          SYSC_OMAP2_ENAWAKEUP |
 159                                          SYSC_OMAP2_SOFTRESET)>;
 160                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 161                                         <SYSC_IDLE_NO>,
 162                                         <SYSC_IDLE_SMART>;
 163                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 164                         clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
 165                         clock-names = "fck";
 166                         #address-cells = <1>;
 167                         #size-cells = <1>;
 168                         ranges = <0x0 0x26000 0x1000>,
 169                                  <0x49026000 0x49026000 0x1000>;
 170
 171                         mcbsp3: mcbsp@0 {
 172                                 compatible = "ti,omap4-mcbsp";
 173                                 reg = <0x0 0xff>, /* MPU private access */
 174                                       <0x49026000 0xff>; /* L3 Interconnect */
 175                                 reg-names = "mpu", "dma";
 176                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 177                                 interrupt-names = "common";
 178                                 ti,buffer-size = <128>;
 179                                 dmas = <&sdma 19>,
 180                                        <&sdma 20>;
 181                                 dma-names = "tx", "rx";
 182                                 status = "disabled";
 183                         };
 184                 };
 185
 186                 target-module@28000 {                   /* 0x40128000, ap 8 08.0 */
 187                         compatible = "ti,sysc-mcasp", "ti,sysc";
 188                         ti,hwmods = "mcasp";
 189                         reg = <0x28000 0x4>,
 190                               <0x28004 0x4>;
 191                         reg-names = "rev", "sysc";
 192                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 193                                         <SYSC_IDLE_NO>,
 194                                         <SYSC_IDLE_SMART>,
 195                                         <SYSC_IDLE_SMART_WKUP>;
 196                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 197                         clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
 198                         clock-names = "fck";
 199                         #address-cells = <1>;
 200                         #size-cells = <1>;
 201                         ranges = <0x0 0x28000 0x1000>,
 202                                  <0x49028000 0x49028000 0x1000>;
 203
 204                         /*
 205                          * Child device unsupported by davinci-mcasp. At least
 206                          * RX path is disabled for omap4, and only DIT mode
 207                          * works with no I2S. See also old Android kernel
 208                          * omap-mcasp driver for more information.
 209                          */
 210                 };
 211
 212                 target-module@2a000 {                   /* 0x4012a000, ap 10 0a.0 */
 213                         compatible = "ti,sysc";
 214                         status = "disabled";
 215                         #address-cells = <1>;
 216                         #size-cells = <1>;
 217                         ranges = <0x0 0x2a000 0x1000>,
 218                                  <0x4902a000 0x4902a000 0x1000>;
 219                 };
 220
 221                 target-module@2e000 {                   /* 0x4012e000, ap 12 0c.0 */
 222                         compatible = "ti,sysc-omap4", "ti,sysc";
 223                         ti,hwmods = "dmic";
 224                         reg = <0x2e000 0x4>,
 225                               <0x2e010 0x4>;
 226                         reg-names = "rev", "sysc";
 227                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 228                                          SYSC_OMAP4_SOFTRESET)>;
 229                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 230                                         <SYSC_IDLE_NO>,
 231                                         <SYSC_IDLE_SMART>,
 232                                         <SYSC_IDLE_SMART_WKUP>;
 233                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 234                         clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
 235                         clock-names = "fck";
 236                         #address-cells = <1>;
 237                         #size-cells = <1>;
 238                         ranges = <0x0 0x2e000 0x1000>,
 239                                  <0x4902e000 0x4902e000 0x1000>;
 240
 241                         dmic: dmic@0 {
 242                                 compatible = "ti,omap4-dmic";
 243                                 reg = <0x0 0x7f>, /* MPU private access */
 244                                       <0x4902e000 0x7f>; /* L3 Interconnect */
 245                                 reg-names = "mpu", "dma";
 246                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 247                                 dmas = <&sdma 67>;
 248                                 dma-names = "up_link";
 249                                 status = "disabled";
 250                         };
 251                 };
 252
 253                 target-module@30000 {                   /* 0x40130000, ap 14 0e.0 */
 254                         compatible = "ti,sysc-omap2", "ti,sysc";
 255                         reg = <0x30000 0x4>,
 256                               <0x30010 0x4>,
 257                               <0x30014 0x4>;
 258                         reg-names = "rev", "sysc", "syss";
 259                         ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
 260                                          SYSC_OMAP2_SOFTRESET)>;
 261                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 262                                         <SYSC_IDLE_NO>,
 263                                         <SYSC_IDLE_SMART>,
 264                                         <SYSC_IDLE_SMART_WKUP>;
 265                         ti,syss-mask = <1>;
 266                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 267                         clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
 268                         clock-names = "fck";
 269                         #address-cells = <1>;
 270                         #size-cells = <1>;
 271                         ranges = <0x0 0x30000 0x1000>,
 272                                  <0x49030000 0x49030000 0x1000>;
 273
 274                         wdt3: wdt@0 {
 275                                 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 276                                 reg = <0x0 0x80>;
 277                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 278                         };
 279                 };
 280
 281                 mcpdm_module: target-module@32000 {     /* 0x40132000, ap 16 10.0 */
 282                         compatible = "ti,sysc-omap4", "ti,sysc";
 283                         ti,hwmods = "mcpdm";
 284                         reg = <0x32000 0x4>,
 285                               <0x32010 0x4>;
 286                         reg-names = "rev", "sysc";
 287                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 288                                          SYSC_OMAP4_SOFTRESET)>;
 289                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 290                                         <SYSC_IDLE_NO>,
 291                                         <SYSC_IDLE_SMART>,
 292                                         <SYSC_IDLE_SMART_WKUP>;
 293                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 294                         clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
 295                         clock-names = "fck";
 296                         #address-cells = <1>;
 297                         #size-cells = <1>;
 298                         ranges = <0x0 0x32000 0x1000>,
 299                                  <0x49032000 0x49032000 0x1000>;
 300
 301                         /* Must be only enabled for boards with pdmclk wired */
 302                         status = "disabled";
 303
 304                         mcpdm: mcpdm@0 {
 305                                 compatible = "ti,omap4-mcpdm";
 306                                 reg = <0x0 0x7f>, /* MPU private access */
 307                                       <0x49032000 0x7f>; /* L3 Interconnect */
 308                                 reg-names = "mpu", "dma";
 309                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 310                                 dmas = <&sdma 65>,
 311                                        <&sdma 66>;
 312                                 dma-names = "up_link", "dn_link";
 313                         };
 314                 };
 315
 316                 target-module@38000 {                   /* 0x40138000, ap 18 12.0 */
 317                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 318                         ti,hwmods = "timer5";
 319                         reg = <0x38000 0x4>,
 320                               <0x38010 0x4>;
 321                         reg-names = "rev", "sysc";
 322                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 323                                          SYSC_OMAP4_SOFTRESET)>;
 324                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 325                                         <SYSC_IDLE_NO>,
 326                                         <SYSC_IDLE_SMART>,
 327                                         <SYSC_IDLE_SMART_WKUP>;
 328                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 329                         clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
 330                         clock-names = "fck";
 331                         #address-cells = <1>;
 332                         #size-cells = <1>;
 333                         ranges = <0x0 0x38000 0x1000>,
 334                                  <0x49038000 0x49038000 0x1000>;
 335
 336                         timer5: timer@0 {
 337                                 compatible = "ti,omap4430-timer";
 338                                 reg = <0x00000000 0x80>,
 339                                       <0x49038000 0x80>;
 340                                 clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>;
 341                                 clock-names = "fck";
 342                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 343                                 ti,timer-dsp;
 344                         };
 345                 };
 346
 347                 target-module@3a000 {                   /* 0x4013a000, ap 20 14.0 */
 348                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 349                         ti,hwmods = "timer6";
 350                         reg = <0x3a000 0x4>,
 351                               <0x3a010 0x4>;
 352                         reg-names = "rev", "sysc";
 353                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 354                                          SYSC_OMAP4_SOFTRESET)>;
 355                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 356                                         <SYSC_IDLE_NO>,
 357                                         <SYSC_IDLE_SMART>,
 358                                         <SYSC_IDLE_SMART_WKUP>;
 359                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 360                         clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
 361                         clock-names = "fck";
 362                         #address-cells = <1>;
 363                         #size-cells = <1>;
 364                         ranges = <0x0 0x3a000 0x1000>,
 365                                  <0x4903a000 0x4903a000 0x1000>;
 366
 367                         timer6: timer@0 {
 368                                 compatible = "ti,omap4430-timer";
 369                                 reg = <0x00000000 0x80>,
 370                                       <0x4903a000 0x80>;
 371                                 clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>;
 372                                 clock-names = "fck";
 373                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 374                                 ti,timer-dsp;
 375                         };
 376                 };
 377
 378                 target-module@3c000 {                   /* 0x4013c000, ap 22 16.0 */
 379                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 380                         ti,hwmods = "timer7";
 381                         reg = <0x3c000 0x4>,
 382                               <0x3c010 0x4>;
 383                         reg-names = "rev", "sysc";
 384                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 385                                          SYSC_OMAP4_SOFTRESET)>;
 386                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 387                                         <SYSC_IDLE_NO>,
 388                                         <SYSC_IDLE_SMART>,
 389                                         <SYSC_IDLE_SMART_WKUP>;
 390                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 391                         clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
 392                         clock-names = "fck";
 393                         #address-cells = <1>;
 394                         #size-cells = <1>;
 395                         ranges = <0x0 0x3c000 0x1000>,
 396                                  <0x4903c000 0x4903c000 0x1000>;
 397
 398                         timer7: timer@0 {
 399                                 compatible = "ti,omap4430-timer";
 400                                 reg = <0x00000000 0x80>,
 401                                       <0x4903c000 0x80>;
 402                                 clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>;
 403                                 clock-names = "fck";
 404                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 405                                 ti,timer-dsp;
 406                         };
 407                 };
 408
 409                 target-module@3e000 {                   /* 0x4013e000, ap 24 18.0 */
 410                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 411                         ti,hwmods = "timer8";
 412                         reg = <0x3e000 0x4>,
 413                               <0x3e010 0x4>;
 414                         reg-names = "rev", "sysc";
 415                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 416                                          SYSC_OMAP4_SOFTRESET)>;
 417                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 418                                         <SYSC_IDLE_NO>,
 419                                         <SYSC_IDLE_SMART>,
 420                                         <SYSC_IDLE_SMART_WKUP>;
 421                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 422                         clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
 423                         clock-names = "fck";
 424                         #address-cells = <1>;
 425                         #size-cells = <1>;
 426                         ranges = <0x0 0x3e000 0x1000>,
 427                                  <0x4903e000 0x4903e000 0x1000>;
 428
 429                         timer8: timer@0 {
 430                                 compatible = "ti,omap4430-timer";
 431                                 reg = <0x00000000 0x80>,
 432                                       <0x4903e000 0x80>;
 433                                 clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
 434                                 clock-names = "fck";
 435                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 436                                 ti,timer-pwm;
 437                                 ti,timer-dsp;
 438                         };
 439                 };
 440
 441                 target-module@80000 {                   /* 0x40180000, ap 26 1a.0 */
 442                         compatible = "ti,sysc";
 443                         status = "disabled";
 444                         #address-cells = <1>;
 445                         #size-cells = <1>;
 446                         ranges = <0x0 0x80000 0x10000>,
 447                                  <0x49080000 0x49080000 0x10000>;
 448                 };
 449
 450                 target-module@a0000 {                   /* 0x401a0000, ap 28 1c.0 */
 451                         compatible = "ti,sysc";
 452                         status = "disabled";
 453                         #address-cells = <1>;
 454                         #size-cells = <1>;
 455                         ranges = <0x0 0xa0000 0x10000>,
 456                                  <0x490a0000 0x490a0000 0x10000>;
 457                 };
 458
 459                 target-module@c0000 {                   /* 0x401c0000, ap 30 1e.0 */
 460                         compatible = "ti,sysc";
 461                         status = "disabled";
 462                         #address-cells = <1>;
 463                         #size-cells = <1>;
 464                         ranges = <0x0 0xc0000 0x10000>,
 465                                  <0x490c0000 0x490c0000 0x10000>;
 466                 };
 467
 468                 target-module@f1000 {                   /* 0x401f1000, ap 32 20.0 */
 469                         compatible = "ti,sysc-omap4", "ti,sysc";
 470                         ti,hwmods = "aess";
 471                         reg = <0xf1000 0x4>,
 472                               <0xf1010 0x4>;
 473                         reg-names = "rev", "sysc";
 474                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 475                                         <SYSC_IDLE_NO>,
 476                                         <SYSC_IDLE_SMART>,
 477                                         <SYSC_IDLE_SMART_WKUP>;
 478                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 479                                         <SYSC_IDLE_NO>,
 480                                         <SYSC_IDLE_SMART>;
 481                         /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
 482                         clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
 483                         clock-names = "fck";
 484                         #address-cells = <1>;
 485                         #size-cells = <1>;
 486                         ranges = <0x0 0xf1000 0x1000>,
 487                                  <0x490f1000 0x490f1000 0x1000>;
 488
 489                         /*
 490                          * No child device binding or driver in mainline.
 491                          * See Android tree and related upstreaming efforts
 492                          * for the old driver.
 493                          */
 494                 };
 495         };
 496 };
 497