arch/arm/boot/dts/r7s72100.dtsi

   1 /*
   2  * Device Tree Source for the r7s72100 SoC
   3  *
   4  * Copyright (C) 2013-14 Renesas Solutions Corp.
   5  * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r7s72100-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r7s72100";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 spi0 = &spi0;
  28                 spi1 = &spi1;
  29                 spi2 = &spi2;
  30                 spi3 = &spi3;
  31                 spi4 = &spi4;
  32         };
  33
  34         clocks {
  35                 ranges;
  36                 #address-cells = <1>;
  37                 #size-cells = <1>;
  38
  39                 /* External clocks */
  40                 extal_clk: extal {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         /* If clk present, value must be set by board */
  44                         clock-frequency = <0>;
  45                 };
  46
  47                 usb_x1_clk: usb_x1 {
  48                         #clock-cells = <0>;
  49                         compatible = "fixed-clock";
  50                         /* If clk present, value must be set by board */
  51                         clock-frequency = <0>;
  52                 };
  53
  54                 /* Fixed factor clocks */
  55                 b_clk: b {
  56                         #clock-cells = <0>;
  57                         compatible = "fixed-factor-clock";
  58                         clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  59                         clock-mult = <1>;
  60                         clock-div = <3>;
  61                 };
  62                 p1_clk: p1 {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-factor-clock";
  65                         clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  66                         clock-mult = <1>;
  67                         clock-div = <6>;
  68                 };
  69                 p0_clk: p0 {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-factor-clock";
  72                         clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  73                         clock-mult = <1>;
  74                         clock-div = <12>;
  75                 };
  76
  77                 /* Special CPG clocks */
  78                 cpg_clocks: cpg_clocks@fcfe0000 {
  79                         #clock-cells = <1>;
  80                         compatible = "renesas,r7s72100-cpg-clocks",
  81                                      "renesas,rz-cpg-clocks";
  82                         reg = <0xfcfe0000 0x18>;
  83                         clocks = <&extal_clk>, <&usb_x1_clk>;
  84                         clock-output-names = "pll", "i", "g";
  85                         #power-domain-cells = <0>;
  86                 };
  87
  88                 /* MSTP clocks */
  89                 mstp3_clks: mstp3_clks@fcfe0420 {
  90                         #clock-cells = <1>;
  91                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
  92                         reg = <0xfcfe0420 4>;
  93                         clocks = <&p0_clk>;
  94                         clock-indices = <R7S72100_CLK_MTU2>;
  95                         clock-output-names = "mtu2";
  96                 };
  97
  98                 mstp4_clks: mstp4_clks@fcfe0424 {
  99                         #clock-cells = <1>;
 100                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 101                         reg = <0xfcfe0424 4>;
 102                         clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
 103                                  <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
 104                         clock-indices = <
 105                                 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
 106                                 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
 107                         >;
 108                         clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
 109                 };
 110
 111                 mstp5_clks: mstp5_clks@fcfe0428 {
 112                         #clock-cells = <1>;
 113                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 114                         reg = <0xfcfe0428 4>;
 115                         clocks = <&p0_clk>, <&p0_clk>;
 116                         clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
 117                         clock-output-names = "ostm0", "ostm1";
 118                 };
 119
 120                 mstp7_clks: mstp7_clks@fcfe0430 {
 121                         #clock-cells = <1>;
 122                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 123                         reg = <0xfcfe0430 4>;
 124                         clocks = <&b_clk>;
 125                         clock-indices = <R7S72100_CLK_ETHER>;
 126                         clock-output-names = "ether";
 127                 };
 128
 129                 mstp8_clks: mstp8_clks@fcfe0434 {
 130                         #clock-cells = <1>;
 131                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 132                         reg = <0xfcfe0434 4>;
 133                         clocks = <&p1_clk>;
 134                         clock-indices = <R7S72100_CLK_MMCIF>;
 135                         clock-output-names = "mmcif";
 136                 };
 137
 138                 mstp9_clks: mstp9_clks@fcfe0438 {
 139                         #clock-cells = <1>;
 140                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 141                         reg = <0xfcfe0438 4>;
 142                         clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
 143                         clock-indices = <
 144                                 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
 145                         >;
 146                         clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
 147                 };
 148
 149                 mstp10_clks: mstp10_clks@fcfe043c {
 150                         #clock-cells = <1>;
 151                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 152                         reg = <0xfcfe043c 4>;
 153                         clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
 154                                  <&p1_clk>;
 155                         clock-indices = <
 156                                 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
 157                                 R7S72100_CLK_SPI4
 158                         >;
 159                         clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
 160                 };
 161                 mstp12_clks: mstp12_clks@fcfe0444 {
 162                         #clock-cells = <1>;
 163                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 164                         reg = <0xfcfe0444 4>;
 165                         clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
 166                         clock-indices = <
 167                                 R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
 168                                 R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
 169                         >;
 170                         clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
 171                 };
 172         };
 173
 174         cpus {
 175                 #address-cells = <1>;
 176                 #size-cells = <0>;
 177
 178                 cpu@0 {
 179                         device_type = "cpu";
 180                         compatible = "arm,cortex-a9";
 181                         reg = <0>;
 182                         clock-frequency = <400000000>;
 183                 };
 184         };
 185
 186         scif0: serial@e8007000 {
 187                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 188                 reg = <0xe8007000 64>;
 189                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 193                 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
 194                 clock-names = "fck";
 195                 power-domains = <&cpg_clocks>;
 196                 status = "disabled";
 197         };
 198
 199         scif1: serial@e8007800 {
 200                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 201                 reg = <0xe8007800 64>;
 202                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
 203                              <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
 204                              <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 206                 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
 207                 clock-names = "fck";
 208                 power-domains = <&cpg_clocks>;
 209                 status = "disabled";
 210         };
 211
 212         scif2: serial@e8008000 {
 213                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 214                 reg = <0xe8008000 64>;
 215                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 217                              <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
 220                 clock-names = "fck";
 221                 power-domains = <&cpg_clocks>;
 222                 status = "disabled";
 223         };
 224
 225         scif3: serial@e8008800 {
 226                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 227                 reg = <0xe8008800 64>;
 228                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 229                              <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 230                              <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
 231                              <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 232                 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
 233                 clock-names = "fck";
 234                 power-domains = <&cpg_clocks>;
 235                 status = "disabled";
 236         };
 237
 238         scif4: serial@e8009000 {
 239                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 240                 reg = <0xe8009000 64>;
 241                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
 242                              <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 243                              <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 244                              <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 245                 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
 246                 clock-names = "fck";
 247                 power-domains = <&cpg_clocks>;
 248                 status = "disabled";
 249         };
 250
 251         scif5: serial@e8009800 {
 252                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 253                 reg = <0xe8009800 64>;
 254                 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 255                              <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 258                 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
 259                 clock-names = "fck";
 260                 power-domains = <&cpg_clocks>;
 261                 status = "disabled";
 262         };
 263
 264         scif6: serial@e800a000 {
 265                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 266                 reg = <0xe800a000 64>;
 267                 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 269                              <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
 270                              <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
 271                 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
 272                 clock-names = "fck";
 273                 power-domains = <&cpg_clocks>;
 274                 status = "disabled";
 275         };
 276
 277         scif7: serial@e800a800 {
 278                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 279                 reg = <0xe800a800 64>;
 280                 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 281                              <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 282                              <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
 283                              <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
 284                 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
 285                 clock-names = "fck";
 286                 power-domains = <&cpg_clocks>;
 287                 status = "disabled";
 288         };
 289
 290         spi0: spi@e800c800 {
 291                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 292                 reg = <0xe800c800 0x24>;
 293                 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 296                 interrupt-names = "error", "rx", "tx";
 297                 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
 298                 power-domains = <&cpg_clocks>;
 299                 num-cs = <1>;
 300                 #address-cells = <1>;
 301                 #size-cells = <0>;
 302                 status = "disabled";
 303         };
 304
 305         spi1: spi@e800d000 {
 306                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 307                 reg = <0xe800d000 0x24>;
 308                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 309                              <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 310                              <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 311                 interrupt-names = "error", "rx", "tx";
 312                 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
 313                 power-domains = <&cpg_clocks>;
 314                 num-cs = <1>;
 315                 #address-cells = <1>;
 316                 #size-cells = <0>;
 317                 status = "disabled";
 318         };
 319
 320         spi2: spi@e800d800 {
 321                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 322                 reg = <0xe800d800 0x24>;
 323                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 324                              <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 325                              <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 326                 interrupt-names = "error", "rx", "tx";
 327                 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
 328                 power-domains = <&cpg_clocks>;
 329                 num-cs = <1>;
 330                 #address-cells = <1>;
 331                 #size-cells = <0>;
 332                 status = "disabled";
 333         };
 334
 335         spi3: spi@e800e000 {
 336                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 337                 reg = <0xe800e000 0x24>;
 338                 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 339                              <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 340                              <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 341                 interrupt-names = "error", "rx", "tx";
 342                 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
 343                 power-domains = <&cpg_clocks>;
 344                 num-cs = <1>;
 345                 #address-cells = <1>;
 346                 #size-cells = <0>;
 347                 status = "disabled";
 348         };
 349
 350         spi4: spi@e800e800 {
 351                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 352                 reg = <0xe800e800 0x24>;
 353                 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 354                              <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 355                              <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 356                 interrupt-names = "error", "rx", "tx";
 357                 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
 358                 power-domains = <&cpg_clocks>;
 359                 num-cs = <1>;
 360                 #address-cells = <1>;
 361                 #size-cells = <0>;
 362                 status = "disabled";
 363         };
 364
 365         gic: interrupt-controller@e8201000 {
 366                 compatible = "arm,pl390";
 367                 #interrupt-cells = <3>;
 368                 #address-cells = <0>;
 369                 interrupt-controller;
 370                 reg = <0xe8201000 0x1000>,
 371                         <0xe8202000 0x1000>;
 372         };
 373
 374         wdt: watchdog@fcfe0000 {
 375                 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
 376                 reg = <0xfcfe0000 0x6>;
 377                 interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
 378                 clocks = <&p0_clk>;
 379         };
 380
 381         i2c0: i2c@fcfee000 {
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 385                 reg = <0xfcfee000 0x44>;
 386                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 387                              <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
 388                              <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
 389                              <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 390                              <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 391                              <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 392                              <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 393                              <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 394                 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
 395                 clock-frequency = <100000>;
 396                 power-domains = <&cpg_clocks>;
 397                 status = "disabled";
 398         };
 399
 400         i2c1: i2c@fcfee400 {
 401                 #address-cells = <1>;
 402                 #size-cells = <0>;
 403                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 404                 reg = <0xfcfee400 0x44>;
 405                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 406                              <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
 407                              <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
 408                              <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 409                              <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 410                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 411                              <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 412                              <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 413                 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
 414                 clock-frequency = <100000>;
 415                 power-domains = <&cpg_clocks>;
 416                 status = "disabled";
 417         };
 418
 419         i2c2: i2c@fcfee800 {
 420                 #address-cells = <1>;
 421                 #size-cells = <0>;
 422                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 423                 reg = <0xfcfee800 0x44>;
 424                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 425                              <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
 426                              <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
 427                              <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 428                              <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 429                              <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 430                              <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 431                              <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 432                 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
 433                 clock-frequency = <100000>;
 434                 power-domains = <&cpg_clocks>;
 435                 status = "disabled";
 436         };
 437
 438         i2c3: i2c@fcfeec00 {
 439                 #address-cells = <1>;
 440                 #size-cells = <0>;
 441                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 442                 reg = <0xfcfeec00 0x44>;
 443                 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 444                              <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
 445                              <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
 446                              <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 447                              <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 448                              <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 449                              <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 450                              <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 451                 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
 452                 clock-frequency = <100000>;
 453                 power-domains = <&cpg_clocks>;
 454                 status = "disabled";
 455         };
 456
 457         mtu2: timer@fcff0000 {
 458                 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
 459                 reg = <0xfcff0000 0x400>;
 460                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 461                 interrupt-names = "tgi0a";
 462                 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
 463                 clock-names = "fck";
 464                 power-domains = <&cpg_clocks>;
 465                 status = "disabled";
 466         };
 467
 468         ether: ethernet@e8203000 {
 469                 compatible = "renesas,ether-r7s72100";
 470                 reg = <0xe8203000 0x800>,
 471                       <0xe8204800 0x200>;
 472                 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
 473                 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
 474                 power-domains = <&cpg_clocks>;
 475                 phy-mode = "mii";
 476                 #address-cells = <1>;
 477                 #size-cells = <0>;
 478                 status = "disabled";
 479         };
 480
 481         mmcif: mmc@e804c800 {
 482                 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
 483                 reg = <0xe804c800 0x80>;
 484                 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
 485                               GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
 486                               GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 487                 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
 488                 power-domains = <&cpg_clocks>;
 489                 reg-io-width = <4>;
 490                 bus-width = <8>;
 491                 status = "disabled";
 492         };
 493
 494         sdhi0: sd@e804e000 {
 495                 compatible = "renesas,sdhi-r7s72100";
 496                 reg = <0xe804e000 0x100>;
 497                 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
 498                               GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
 499                               GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 500
 501                 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
 502                          <&mstp12_clks R7S72100_CLK_SDHI01>;
 503                 clock-names = "core", "cd";
 504                 power-domains = <&cpg_clocks>;
 505                 cap-sd-highspeed;
 506                 cap-sdio-irq;
 507                 status = "disabled";
 508         };
 509
 510         sdhi1: sd@e804e800 {
 511                 compatible = "renesas,sdhi-r7s72100";
 512                 reg = <0xe804e800 0x100>;
 513                 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
 514                               GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
 515                               GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
 516
 517                 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
 518                          <&mstp12_clks R7S72100_CLK_SDHI11>;
 519                 clock-names = "core", "cd";
 520                 power-domains = <&cpg_clocks>;
 521                 cap-sd-highspeed;
 522                 cap-sdio-irq;
 523                 status = "disabled";
 524         };
 525
 526         ostm0: timer@fcfec000 {
 527                 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
 528                 reg = <0xfcfec000 0x30>;
 529                 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
 530                 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
 531                 power-domains = <&cpg_clocks>;
 532                 status = "disabled";
 533         };
 534
 535         ostm1: timer@fcfec400 {
 536                 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
 537                 reg = <0xfcfec400 0x30>;
 538                 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
 539                 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
 540                 power-domains = <&cpg_clocks>;
 541                 status = "disabled";
 542         };
 543 };