arch/arm/boot/dts/r7s72100.dtsi

   1 /*
   2  * Device Tree Source for the r7s72100 SoC
   3  *
   4  * Copyright (C) 2013-14 Renesas Solutions Corp.
   5  * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r7s72100-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r7s72100";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 spi0 = &spi0;
  28                 spi1 = &spi1;
  29                 spi2 = &spi2;
  30                 spi3 = &spi3;
  31                 spi4 = &spi4;
  32         };
  33
  34         clocks {
  35                 ranges;
  36                 #address-cells = <1>;
  37                 #size-cells = <1>;
  38
  39                 /* External clocks */
  40                 extal_clk: extal {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         /* If clk present, value must be set by board */
  44                         clock-frequency = <0>;
  45                 };
  46
  47                 usb_x1_clk: usb_x1 {
  48                         #clock-cells = <0>;
  49                         compatible = "fixed-clock";
  50                         /* If clk present, value must be set by board */
  51                         clock-frequency = <0>;
  52                 };
  53
  54                 /* Fixed factor clocks */
  55                 b_clk: b {
  56                         #clock-cells = <0>;
  57                         compatible = "fixed-factor-clock";
  58                         clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  59                         clock-mult = <1>;
  60                         clock-div = <3>;
  61                 };
  62                 p1_clk: p1 {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-factor-clock";
  65                         clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  66                         clock-mult = <1>;
  67                         clock-div = <6>;
  68                 };
  69                 p0_clk: p0 {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-factor-clock";
  72                         clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  73                         clock-mult = <1>;
  74                         clock-div = <12>;
  75                 };
  76
  77                 /* Special CPG clocks */
  78                 cpg_clocks: cpg_clocks@fcfe0000 {
  79                         #clock-cells = <1>;
  80                         compatible = "renesas,r7s72100-cpg-clocks",
  81                                      "renesas,rz-cpg-clocks";
  82                         reg = <0xfcfe0000 0x18>;
  83                         clocks = <&extal_clk>, <&usb_x1_clk>;
  84                         clock-output-names = "pll", "i", "g";
  85                         #power-domain-cells = <0>;
  86                 };
  87
  88                 /* MSTP clocks */
  89                 mstp3_clks: mstp3_clks@fcfe0420 {
  90                         #clock-cells = <1>;
  91                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
  92                         reg = <0xfcfe0420 4>;
  93                         clocks = <&p0_clk>;
  94                         clock-indices = <R7S72100_CLK_MTU2>;
  95                         clock-output-names = "mtu2";
  96                 };
  97
  98                 mstp4_clks: mstp4_clks@fcfe0424 {
  99                         #clock-cells = <1>;
 100                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 101                         reg = <0xfcfe0424 4>;
 102                         clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
 103                                  <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
 104                         clock-indices = <
 105                                 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
 106                                 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
 107                         >;
 108                         clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
 109                 };
 110
 111                 mstp7_clks: mstp7_clks@fcfe0430 {
 112                         #clock-cells = <1>;
 113                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 114                         reg = <0xfcfe0430 4>;
 115                         clocks = <&p0_clk>;
 116                         clock-indices = <R7S72100_CLK_ETHER>;
 117                         clock-output-names = "ether";
 118                 };
 119
 120                 mstp8_clks: mstp8_clks@fcfe0434 {
 121                         #clock-cells = <1>;
 122                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 123                         reg = <0xfcfe0434 4>;
 124                         clocks = <&p1_clk>;
 125                         clock-indices = <R7S72100_CLK_MMCIF>;
 126                         clock-output-names = "mmcif";
 127                 };
 128
 129                 mstp9_clks: mstp9_clks@fcfe0438 {
 130                         #clock-cells = <1>;
 131                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 132                         reg = <0xfcfe0438 4>;
 133                         clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
 134                         clock-indices = <
 135                                 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
 136                         >;
 137                         clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
 138                 };
 139
 140                 mstp10_clks: mstp10_clks@fcfe043c {
 141                         #clock-cells = <1>;
 142                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 143                         reg = <0xfcfe043c 4>;
 144                         clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
 145                                  <&p1_clk>;
 146                         clock-indices = <
 147                                 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
 148                                 R7S72100_CLK_SPI4
 149                         >;
 150                         clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
 151                 };
 152         };
 153
 154         cpus {
 155                 #address-cells = <1>;
 156                 #size-cells = <0>;
 157
 158                 cpu@0 {
 159                         device_type = "cpu";
 160                         compatible = "arm,cortex-a9";
 161                         reg = <0>;
 162                         clock-frequency = <400000000>;
 163                 };
 164         };
 165
 166         scif0: serial@e8007000 {
 167                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 168                 reg = <0xe8007000 64>;
 169                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 173                 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
 174                 clock-names = "fck";
 175                 power-domains = <&cpg_clocks>;
 176                 status = "disabled";
 177         };
 178
 179         scif1: serial@e8007800 {
 180                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 181                 reg = <0xe8007800 64>;
 182                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
 183                              <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
 184                              <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 185                              <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 186                 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
 187                 clock-names = "fck";
 188                 power-domains = <&cpg_clocks>;
 189                 status = "disabled";
 190         };
 191
 192         scif2: serial@e8008000 {
 193                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 194                 reg = <0xe8008000 64>;
 195                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 199                 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
 200                 clock-names = "fck";
 201                 power-domains = <&cpg_clocks>;
 202                 status = "disabled";
 203         };
 204
 205         scif3: serial@e8008800 {
 206                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 207                 reg = <0xe8008800 64>;
 208                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 209                              <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 212                 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
 213                 clock-names = "fck";
 214                 power-domains = <&cpg_clocks>;
 215                 status = "disabled";
 216         };
 217
 218         scif4: serial@e8009000 {
 219                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 220                 reg = <0xe8009000 64>;
 221                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
 222                              <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 223                              <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 224                              <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 225                 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
 226                 clock-names = "fck";
 227                 power-domains = <&cpg_clocks>;
 228                 status = "disabled";
 229         };
 230
 231         scif5: serial@e8009800 {
 232                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 233                 reg = <0xe8009800 64>;
 234                 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 235                              <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 236                              <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 237                              <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 238                 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
 239                 clock-names = "fck";
 240                 power-domains = <&cpg_clocks>;
 241                 status = "disabled";
 242         };
 243
 244         scif6: serial@e800a000 {
 245                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 246                 reg = <0xe800a000 64>;
 247                 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 248                              <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 249                              <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
 250                              <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
 251                 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
 252                 clock-names = "fck";
 253                 power-domains = <&cpg_clocks>;
 254                 status = "disabled";
 255         };
 256
 257         scif7: serial@e800a800 {
 258                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 259                 reg = <0xe800a800 64>;
 260                 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
 264                 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
 265                 clock-names = "fck";
 266                 power-domains = <&cpg_clocks>;
 267                 status = "disabled";
 268         };
 269
 270         spi0: spi@e800c800 {
 271                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 272                 reg = <0xe800c800 0x24>;
 273                 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 274                              <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 276                 interrupt-names = "error", "rx", "tx";
 277                 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
 278                 power-domains = <&cpg_clocks>;
 279                 num-cs = <1>;
 280                 #address-cells = <1>;
 281                 #size-cells = <0>;
 282                 status = "disabled";
 283         };
 284
 285         spi1: spi@e800d000 {
 286                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 287                 reg = <0xe800d000 0x24>;
 288                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 291                 interrupt-names = "error", "rx", "tx";
 292                 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
 293                 power-domains = <&cpg_clocks>;
 294                 num-cs = <1>;
 295                 #address-cells = <1>;
 296                 #size-cells = <0>;
 297                 status = "disabled";
 298         };
 299
 300         spi2: spi@e800d800 {
 301                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 302                 reg = <0xe800d800 0x24>;
 303                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 305                              <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 306                 interrupt-names = "error", "rx", "tx";
 307                 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
 308                 power-domains = <&cpg_clocks>;
 309                 num-cs = <1>;
 310                 #address-cells = <1>;
 311                 #size-cells = <0>;
 312                 status = "disabled";
 313         };
 314
 315         spi3: spi@e800e000 {
 316                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 317                 reg = <0xe800e000 0x24>;
 318                 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 319                              <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 320                              <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 321                 interrupt-names = "error", "rx", "tx";
 322                 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
 323                 power-domains = <&cpg_clocks>;
 324                 num-cs = <1>;
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327                 status = "disabled";
 328         };
 329
 330         spi4: spi@e800e800 {
 331                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 332                 reg = <0xe800e800 0x24>;
 333                 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 334                              <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 335                              <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 336                 interrupt-names = "error", "rx", "tx";
 337                 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
 338                 power-domains = <&cpg_clocks>;
 339                 num-cs = <1>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 status = "disabled";
 343         };
 344
 345         gic: interrupt-controller@e8201000 {
 346                 compatible = "arm,pl390";
 347                 #interrupt-cells = <3>;
 348                 #address-cells = <0>;
 349                 interrupt-controller;
 350                 reg = <0xe8201000 0x1000>,
 351                         <0xe8202000 0x1000>;
 352         };
 353
 354         i2c0: i2c@fcfee000 {
 355                 #address-cells = <1>;
 356                 #size-cells = <0>;
 357                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 358                 reg = <0xfcfee000 0x44>;
 359                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 360                              <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
 361                              <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
 362                              <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 363                              <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 364                              <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 365                              <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 366                              <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 367                 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
 368                 clock-frequency = <100000>;
 369                 power-domains = <&cpg_clocks>;
 370                 status = "disabled";
 371         };
 372
 373         i2c1: i2c@fcfee400 {
 374                 #address-cells = <1>;
 375                 #size-cells = <0>;
 376                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 377                 reg = <0xfcfee400 0x44>;
 378                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 379                              <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
 380                              <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
 381                              <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 382                              <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 383                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 384                              <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 385                              <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 386                 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
 387                 clock-frequency = <100000>;
 388                 power-domains = <&cpg_clocks>;
 389                 status = "disabled";
 390         };
 391
 392         i2c2: i2c@fcfee800 {
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 396                 reg = <0xfcfee800 0x44>;
 397                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 398                              <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
 399                              <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
 400                              <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 401                              <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 402                              <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 403                              <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 404                              <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 405                 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
 406                 clock-frequency = <100000>;
 407                 power-domains = <&cpg_clocks>;
 408                 status = "disabled";
 409         };
 410
 411         i2c3: i2c@fcfeec00 {
 412                 #address-cells = <1>;
 413                 #size-cells = <0>;
 414                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 415                 reg = <0xfcfeec00 0x44>;
 416                 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 417                              <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
 418                              <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
 419                              <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 420                              <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 421                              <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 422                              <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 423                              <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 424                 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
 425                 clock-frequency = <100000>;
 426                 power-domains = <&cpg_clocks>;
 427                 status = "disabled";
 428         };
 429
 430         mtu2: timer@fcff0000 {
 431                 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
 432                 reg = <0xfcff0000 0x400>;
 433                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 434                 interrupt-names = "tgi0a";
 435                 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
 436                 clock-names = "fck";
 437                 power-domains = <&cpg_clocks>;
 438                 status = "disabled";
 439         };
 440
 441         ether: ethernet@e8203000 {
 442                 compatible = "renesas,ether-r7s72100";
 443                 reg = <0xe8203000 0x800>,
 444                       <0xe8204800 0x200>;
 445                 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
 446                 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
 447                 power-domains = <&cpg_clocks>;
 448                 phy-mode = "mii";
 449                 #address-cells = <1>;
 450                 #size-cells = <0>;
 451                 status = "disabled";
 452         };
 453 };