1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/power/rk3288-power.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
17 compatible = "rockchip,rk3288";
19 interrupt-parent = <&gic>;
44 compatible = "arm,cortex-a12-pmu";
45 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
49 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
55 enable-method = "rockchip,rk3066-smp";
56 rockchip,pmu = <&pmu>;
60 compatible = "arm,cortex-a12";
62 resets = <&cru SRST_CORE0>;
63 operating-points-v2 = <&cpu_opp_table>;
64 #cooling-cells = <2>; /* min followed by max */
65 clock-latency = <40000>;
66 clocks = <&cru ARMCLK>;
70 compatible = "arm,cortex-a12";
72 resets = <&cru SRST_CORE1>;
73 operating-points-v2 = <&cpu_opp_table>;
74 #cooling-cells = <2>; /* min followed by max */
75 clock-latency = <40000>;
76 clocks = <&cru ARMCLK>;
80 compatible = "arm,cortex-a12";
82 resets = <&cru SRST_CORE2>;
83 operating-points-v2 = <&cpu_opp_table>;
84 #cooling-cells = <2>; /* min followed by max */
85 clock-latency = <40000>;
86 clocks = <&cru ARMCLK>;
90 compatible = "arm,cortex-a12";
92 resets = <&cru SRST_CORE3>;
93 operating-points-v2 = <&cpu_opp_table>;
94 #cooling-cells = <2>; /* min followed by max */
95 clock-latency = <40000>;
96 clocks = <&cru ARMCLK>;
100 cpu_opp_table: cpu-opp-table {
101 compatible = "operating-points-v2";
105 opp-hz = /bits/ 64 <126000000>;
106 opp-microvolt = <900000>;
109 opp-hz = /bits/ 64 <216000000>;
110 opp-microvolt = <900000>;
113 opp-hz = /bits/ 64 <312000000>;
114 opp-microvolt = <900000>;
117 opp-hz = /bits/ 64 <408000000>;
118 opp-microvolt = <900000>;
121 opp-hz = /bits/ 64 <600000000>;
122 opp-microvolt = <900000>;
125 opp-hz = /bits/ 64 <696000000>;
126 opp-microvolt = <950000>;
129 opp-hz = /bits/ 64 <816000000>;
130 opp-microvolt = <1000000>;
133 opp-hz = /bits/ 64 <1008000000>;
134 opp-microvolt = <1050000>;
137 opp-hz = /bits/ 64 <1200000000>;
138 opp-microvolt = <1100000>;
141 opp-hz = /bits/ 64 <1416000000>;
142 opp-microvolt = <1200000>;
145 opp-hz = /bits/ 64 <1512000000>;
146 opp-microvolt = <1300000>;
149 opp-hz = /bits/ 64 <1608000000>;
150 opp-microvolt = <1350000>;
155 compatible = "simple-bus";
156 #address-cells = <2>;
160 dmac_peri: dma-controller@ff250000 {
161 compatible = "arm,pl330", "arm,primecell";
162 reg = <0x0 0xff250000 0x0 0x4000>;
163 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
166 arm,pl330-broken-no-flushp;
167 clocks = <&cru ACLK_DMAC2>;
168 clock-names = "apb_pclk";
171 dmac_bus_ns: dma-controller@ff600000 {
172 compatible = "arm,pl330", "arm,primecell";
173 reg = <0x0 0xff600000 0x0 0x4000>;
174 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
177 arm,pl330-broken-no-flushp;
178 clocks = <&cru ACLK_DMAC1>;
179 clock-names = "apb_pclk";
183 dmac_bus_s: dma-controller@ffb20000 {
184 compatible = "arm,pl330", "arm,primecell";
185 reg = <0x0 0xffb20000 0x0 0x4000>;
186 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
189 arm,pl330-broken-no-flushp;
190 clocks = <&cru ACLK_DMAC1>;
191 clock-names = "apb_pclk";
196 #address-cells = <2>;
201 * The rk3288 cannot use the memory area above 0xfe000000
202 * for dma operations for some reason. While there is
203 * probably a better solution available somewhere, we
204 * haven't found it yet and while devices with 2GB of ram
205 * are not affected, this issue prevents 4GB from booting.
206 * So to make these devices at least bootable, block
207 * this area for the time being until the real solution
210 dma-unusable@fe000000 {
211 reg = <0x0 0xfe000000 0x0 0x1000000>;
216 compatible = "fixed-clock";
217 clock-frequency = <24000000>;
218 clock-output-names = "xin24m";
223 compatible = "arm,armv7-timer";
224 arm,cpu-registers-not-fw-configured;
225 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
226 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
227 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
228 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
229 clock-frequency = <24000000>;
232 timer: timer@ff810000 {
233 compatible = "rockchip,rk3288-timer";
234 reg = <0x0 0xff810000 0x0 0x20>;
235 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&xin24m>, <&cru PCLK_TIMER>;
237 clock-names = "timer", "pclk";
241 compatible = "rockchip,display-subsystem";
242 ports = <&vopl_out>, <&vopb_out>;
245 sdmmc: dwmmc@ff0c0000 {
246 compatible = "rockchip,rk3288-dw-mshc";
247 max-frequency = <150000000>;
248 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
249 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
250 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
251 fifo-depth = <0x100>;
252 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
253 reg = <0x0 0xff0c0000 0x0 0x4000>;
254 resets = <&cru SRST_MMC0>;
255 reset-names = "reset";
259 sdio0: dwmmc@ff0d0000 {
260 compatible = "rockchip,rk3288-dw-mshc";
261 max-frequency = <150000000>;
262 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
263 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
264 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
265 fifo-depth = <0x100>;
266 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
267 reg = <0x0 0xff0d0000 0x0 0x4000>;
268 resets = <&cru SRST_SDIO0>;
269 reset-names = "reset";
273 sdio1: dwmmc@ff0e0000 {
274 compatible = "rockchip,rk3288-dw-mshc";
275 max-frequency = <150000000>;
276 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
277 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
278 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
279 fifo-depth = <0x100>;
280 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
281 reg = <0x0 0xff0e0000 0x0 0x4000>;
282 resets = <&cru SRST_SDIO1>;
283 reset-names = "reset";
287 emmc: dwmmc@ff0f0000 {
288 compatible = "rockchip,rk3288-dw-mshc";
289 max-frequency = <150000000>;
290 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
291 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
292 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
293 fifo-depth = <0x100>;
294 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
295 reg = <0x0 0xff0f0000 0x0 0x4000>;
296 resets = <&cru SRST_EMMC>;
297 reset-names = "reset";
301 saradc: saradc@ff100000 {
302 compatible = "rockchip,saradc";
303 reg = <0x0 0xff100000 0x0 0x100>;
304 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
305 #io-channel-cells = <1>;
306 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
307 clock-names = "saradc", "apb_pclk";
308 resets = <&cru SRST_SARADC>;
309 reset-names = "saradc-apb";
314 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
315 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
316 clock-names = "spiclk", "apb_pclk";
317 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
318 dma-names = "tx", "rx";
319 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
322 reg = <0x0 0xff110000 0x0 0x1000>;
323 #address-cells = <1>;
329 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
330 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
331 clock-names = "spiclk", "apb_pclk";
332 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
333 dma-names = "tx", "rx";
334 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
337 reg = <0x0 0xff120000 0x0 0x1000>;
338 #address-cells = <1>;
344 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
345 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
346 clock-names = "spiclk", "apb_pclk";
347 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
348 dma-names = "tx", "rx";
349 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
352 reg = <0x0 0xff130000 0x0 0x1000>;
353 #address-cells = <1>;
359 compatible = "rockchip,rk3288-i2c";
360 reg = <0x0 0xff140000 0x0 0x1000>;
361 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
362 #address-cells = <1>;
365 clocks = <&cru PCLK_I2C1>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&i2c1_xfer>;
372 compatible = "rockchip,rk3288-i2c";
373 reg = <0x0 0xff150000 0x0 0x1000>;
374 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
375 #address-cells = <1>;
378 clocks = <&cru PCLK_I2C3>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&i2c3_xfer>;
385 compatible = "rockchip,rk3288-i2c";
386 reg = <0x0 0xff160000 0x0 0x1000>;
387 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
388 #address-cells = <1>;
391 clocks = <&cru PCLK_I2C4>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&i2c4_xfer>;
398 compatible = "rockchip,rk3288-i2c";
399 reg = <0x0 0xff170000 0x0 0x1000>;
400 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
401 #address-cells = <1>;
404 clocks = <&cru PCLK_I2C5>;
405 pinctrl-names = "default";
406 pinctrl-0 = <&i2c5_xfer>;
410 uart0: serial@ff180000 {
411 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
412 reg = <0x0 0xff180000 0x0 0x100>;
413 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
417 clock-names = "baudclk", "apb_pclk";
418 pinctrl-names = "default";
419 pinctrl-0 = <&uart0_xfer>;
423 uart1: serial@ff190000 {
424 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
425 reg = <0x0 0xff190000 0x0 0x100>;
426 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
430 clock-names = "baudclk", "apb_pclk";
431 pinctrl-names = "default";
432 pinctrl-0 = <&uart1_xfer>;
436 uart2: serial@ff690000 {
437 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
438 reg = <0x0 0xff690000 0x0 0x100>;
439 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
443 clock-names = "baudclk", "apb_pclk";
444 pinctrl-names = "default";
445 pinctrl-0 = <&uart2_xfer>;
449 uart3: serial@ff1b0000 {
450 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
451 reg = <0x0 0xff1b0000 0x0 0x100>;
452 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
456 clock-names = "baudclk", "apb_pclk";
457 pinctrl-names = "default";
458 pinctrl-0 = <&uart3_xfer>;
462 uart4: serial@ff1c0000 {
463 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
464 reg = <0x0 0xff1c0000 0x0 0x100>;
465 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
469 clock-names = "baudclk", "apb_pclk";
470 pinctrl-names = "default";
471 pinctrl-0 = <&uart4_xfer>;
476 reserve_thermal: reserve_thermal {
477 polling-delay-passive = <1000>; /* milliseconds */
478 polling-delay = <5000>; /* milliseconds */
480 thermal-sensors = <&tsadc 0>;
483 cpu_thermal: cpu_thermal {
484 polling-delay-passive = <100>; /* milliseconds */
485 polling-delay = <5000>; /* milliseconds */
487 thermal-sensors = <&tsadc 1>;
490 cpu_alert0: cpu_alert0 {
491 temperature = <70000>; /* millicelsius */
492 hysteresis = <2000>; /* millicelsius */
495 cpu_alert1: cpu_alert1 {
496 temperature = <75000>; /* millicelsius */
497 hysteresis = <2000>; /* millicelsius */
501 temperature = <90000>; /* millicelsius */
502 hysteresis = <2000>; /* millicelsius */
509 trip = <&cpu_alert0>;
511 <&cpu0 THERMAL_NO_LIMIT 6>,
512 <&cpu1 THERMAL_NO_LIMIT 6>,
513 <&cpu2 THERMAL_NO_LIMIT 6>,
514 <&cpu3 THERMAL_NO_LIMIT 6>;
517 trip = <&cpu_alert1>;
519 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
520 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
521 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
522 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
527 gpu_thermal: gpu_thermal {
528 polling-delay-passive = <100>; /* milliseconds */
529 polling-delay = <5000>; /* milliseconds */
531 thermal-sensors = <&tsadc 2>;
534 gpu_alert0: gpu_alert0 {
535 temperature = <70000>; /* millicelsius */
536 hysteresis = <2000>; /* millicelsius */
540 temperature = <90000>; /* millicelsius */
541 hysteresis = <2000>; /* millicelsius */
548 trip = <&gpu_alert0>;
550 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
551 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
552 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
553 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
559 tsadc: tsadc@ff280000 {
560 compatible = "rockchip,rk3288-tsadc";
561 reg = <0x0 0xff280000 0x0 0x100>;
562 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
564 clock-names = "tsadc", "apb_pclk";
565 resets = <&cru SRST_TSADC>;
566 reset-names = "tsadc-apb";
567 pinctrl-names = "init", "default", "sleep";
568 pinctrl-0 = <&otp_gpio>;
569 pinctrl-1 = <&otp_out>;
570 pinctrl-2 = <&otp_gpio>;
571 #thermal-sensor-cells = <1>;
572 rockchip,hw-tshut-temp = <95000>;
576 gmac: ethernet@ff290000 {
577 compatible = "rockchip,rk3288-gmac";
578 reg = <0x0 0xff290000 0x0 0x10000>;
579 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
581 interrupt-names = "macirq", "eth_wake_irq";
582 rockchip,grf = <&grf>;
583 clocks = <&cru SCLK_MAC>,
584 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
585 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
586 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
587 clock-names = "stmmaceth",
588 "mac_clk_rx", "mac_clk_tx",
589 "clk_mac_ref", "clk_mac_refout",
590 "aclk_mac", "pclk_mac";
591 resets = <&cru SRST_MAC>;
592 reset-names = "stmmaceth";
596 usb_host0_ehci: usb@ff500000 {
597 compatible = "generic-ehci";
598 reg = <0x0 0xff500000 0x0 0x100>;
599 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&cru HCLK_USBHOST0>;
601 clock-names = "usbhost";
607 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
609 usb_host1: usb@ff540000 {
610 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
612 reg = <0x0 0xff540000 0x0 0x40000>;
613 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&cru HCLK_USBHOST1>;
618 phy-names = "usb2-phy";
622 usb_otg: usb@ff580000 {
623 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
625 reg = <0x0 0xff580000 0x0 0x40000>;
626 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&cru HCLK_OTG0>;
630 g-np-tx-fifo-size = <16>;
631 g-rx-fifo-size = <275>;
632 g-tx-fifo-size = <256 128 128 64 64 32>;
634 phy-names = "usb2-phy";
638 usb_hsic: usb@ff5c0000 {
639 compatible = "generic-ehci";
640 reg = <0x0 0xff5c0000 0x0 0x100>;
641 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&cru HCLK_HSIC>;
643 clock-names = "usbhost";
648 compatible = "rockchip,rk3288-i2c";
649 reg = <0x0 0xff650000 0x0 0x1000>;
650 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
651 #address-cells = <1>;
654 clocks = <&cru PCLK_I2C0>;
655 pinctrl-names = "default";
656 pinctrl-0 = <&i2c0_xfer>;
661 compatible = "rockchip,rk3288-i2c";
662 reg = <0x0 0xff660000 0x0 0x1000>;
663 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
664 #address-cells = <1>;
667 clocks = <&cru PCLK_I2C2>;
668 pinctrl-names = "default";
669 pinctrl-0 = <&i2c2_xfer>;
674 compatible = "rockchip,rk3288-pwm";
675 reg = <0x0 0xff680000 0x0 0x10>;
677 pinctrl-names = "default";
678 pinctrl-0 = <&pwm0_pin>;
679 clocks = <&cru PCLK_PWM>;
685 compatible = "rockchip,rk3288-pwm";
686 reg = <0x0 0xff680010 0x0 0x10>;
688 pinctrl-names = "default";
689 pinctrl-0 = <&pwm1_pin>;
690 clocks = <&cru PCLK_PWM>;
696 compatible = "rockchip,rk3288-pwm";
697 reg = <0x0 0xff680020 0x0 0x10>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&pwm2_pin>;
701 clocks = <&cru PCLK_PWM>;
707 compatible = "rockchip,rk3288-pwm";
708 reg = <0x0 0xff680030 0x0 0x10>;
710 pinctrl-names = "default";
711 pinctrl-0 = <&pwm3_pin>;
712 clocks = <&cru PCLK_PWM>;
717 bus_intmem@ff700000 {
718 compatible = "mmio-sram";
719 reg = <0x0 0xff700000 0x0 0x18000>;
720 #address-cells = <1>;
722 ranges = <0 0x0 0xff700000 0x18000>;
724 compatible = "rockchip,rk3066-smp-sram";
730 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
731 reg = <0x0 0xff720000 0x0 0x1000>;
734 pmu: power-management@ff730000 {
735 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
736 reg = <0x0 0xff730000 0x0 0x100>;
738 power: power-controller {
739 compatible = "rockchip,rk3288-power-controller";
740 #power-domain-cells = <1>;
741 #address-cells = <1>;
744 assigned-clocks = <&cru SCLK_EDP_24M>;
745 assigned-clock-parents = <&xin24m>;
748 * Note: Although SCLK_* are the working clocks
749 * of device without including on the NOC, needed for
752 * The clocks on the which NOC:
753 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
754 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
755 * ACLK_RGA is on ACLK_RGA_NIU.
756 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
758 * Which clock are device clocks:
760 * *_IEP IEP:Image Enhancement Processor
761 * *_ISP ISP:Image Signal Processing
762 * *_VIP VIP:Video Input Processor
763 * *_VOP* VOP:Visual Output Processor
770 pd_vio@RK3288_PD_VIO {
771 reg = <RK3288_PD_VIO>;
772 clocks = <&cru ACLK_IEP>,
786 <&cru PCLK_EDP_CTRL>,
787 <&cru PCLK_HDMI_CTRL>,
788 <&cru PCLK_LVDS_PHY>,
789 <&cru PCLK_MIPI_CSI>,
790 <&cru PCLK_MIPI_DSI0>,
791 <&cru PCLK_MIPI_DSI1>,
797 pm_qos = <&qos_vio0_iep>,
809 * Note: The following 3 are HEVC(H.265) clocks,
810 * and on the ACLK_HEVC_NIU (NOC).
812 pd_hevc@RK3288_PD_HEVC {
813 reg = <RK3288_PD_HEVC>;
814 clocks = <&cru ACLK_HEVC>,
815 <&cru SCLK_HEVC_CABAC>,
816 <&cru SCLK_HEVC_CORE>;
817 pm_qos = <&qos_hevc_r>,
822 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
823 * (video endecoder & decoder) clocks that on the
824 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
826 pd_video@RK3288_PD_VIDEO {
827 reg = <RK3288_PD_VIDEO>;
828 clocks = <&cru ACLK_VCODEC>,
830 pm_qos = <&qos_video>;
834 * Note: ACLK_GPU is the GPU clock,
835 * and on the ACLK_GPU_NIU (NOC).
837 pd_gpu@RK3288_PD_GPU {
838 reg = <RK3288_PD_GPU>;
839 clocks = <&cru ACLK_GPU>;
840 pm_qos = <&qos_gpu_r>,
846 compatible = "syscon-reboot-mode";
848 mode-normal = <BOOT_NORMAL>;
849 mode-recovery = <BOOT_RECOVERY>;
850 mode-bootloader = <BOOT_FASTBOOT>;
851 mode-loader = <BOOT_BL_DOWNLOAD>;
855 sgrf: syscon@ff740000 {
856 compatible = "rockchip,rk3288-sgrf", "syscon";
857 reg = <0x0 0xff740000 0x0 0x1000>;
860 cru: clock-controller@ff760000 {
861 compatible = "rockchip,rk3288-cru";
862 reg = <0x0 0xff760000 0x0 0x1000>;
863 rockchip,grf = <&grf>;
866 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
867 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
868 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
869 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
871 assigned-clock-rates = <594000000>, <400000000>,
872 <500000000>, <300000000>,
873 <150000000>, <75000000>,
874 <300000000>, <150000000>,
878 grf: syscon@ff770000 {
879 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
880 reg = <0x0 0xff770000 0x0 0x1000>;
883 compatible = "rockchip,rk3288-dp-phy";
884 clocks = <&cru SCLK_EDP_24M>;
890 io_domains: io-domains {
891 compatible = "rockchip,rk3288-io-voltage-domain";
896 compatible = "rockchip,rk3288-usb-phy";
897 #address-cells = <1>;
901 usbphy0: usb-phy@320 {
904 clocks = <&cru SCLK_OTGPHY0>;
905 clock-names = "phyclk";
909 usbphy1: usb-phy@334 {
912 clocks = <&cru SCLK_OTGPHY1>;
913 clock-names = "phyclk";
917 usbphy2: usb-phy@348 {
920 clocks = <&cru SCLK_OTGPHY2>;
921 clock-names = "phyclk";
927 wdt: watchdog@ff800000 {
928 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
929 reg = <0x0 0xff800000 0x0 0x100>;
930 clocks = <&cru PCLK_WDT>;
931 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
935 spdif: sound@ff88b0000 {
936 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
937 reg = <0x0 0xff8b0000 0x0 0x10000>;
938 #sound-dai-cells = <0>;
939 clock-names = "hclk", "mclk";
940 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
941 dmas = <&dmac_bus_s 3>;
943 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
944 pinctrl-names = "default";
945 pinctrl-0 = <&spdif_tx>;
946 rockchip,grf = <&grf>;
951 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
952 reg = <0x0 0xff890000 0x0 0x10000>;
953 #sound-dai-cells = <0>;
954 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
955 #address-cells = <1>;
957 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
958 dma-names = "tx", "rx";
959 clock-names = "i2s_hclk", "i2s_clk";
960 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
961 pinctrl-names = "default";
962 pinctrl-0 = <&i2s0_bus>;
963 rockchip,playback-channels = <8>;
964 rockchip,capture-channels = <2>;
968 crypto: cypto-controller@ff8a0000 {
969 compatible = "rockchip,rk3288-crypto";
970 reg = <0x0 0xff8a0000 0x0 0x4000>;
971 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
972 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
973 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
974 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
975 resets = <&cru SRST_CRYPTO>;
976 reset-names = "crypto-rst";
980 iep_mmu: iommu@ff900800 {
981 compatible = "rockchip,iommu";
982 reg = <0x0 0xff900800 0x0 0x40>;
983 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
984 interrupt-names = "iep_mmu";
985 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
986 clock-names = "aclk", "iface";
991 isp_mmu: iommu@ff914000 {
992 compatible = "rockchip,iommu";
993 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
994 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
995 interrupt-names = "isp_mmu";
996 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
997 clock-names = "aclk", "iface";
999 rockchip,disable-mmu-reset;
1000 status = "disabled";
1004 compatible = "rockchip,rk3288-rga";
1005 reg = <0x0 0xff920000 0x0 0x180>;
1006 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1007 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1008 clock-names = "aclk", "hclk", "sclk";
1009 power-domains = <&power RK3288_PD_VIO>;
1010 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1011 reset-names = "core", "axi", "ahb";
1014 vopb: vop@ff930000 {
1015 compatible = "rockchip,rk3288-vop";
1016 reg = <0x0 0xff930000 0x0 0x19c>;
1017 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1018 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1019 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1020 power-domains = <&power RK3288_PD_VIO>;
1021 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1022 reset-names = "axi", "ahb", "dclk";
1023 iommus = <&vopb_mmu>;
1024 status = "disabled";
1027 #address-cells = <1>;
1030 vopb_out_hdmi: endpoint@0 {
1032 remote-endpoint = <&hdmi_in_vopb>;
1035 vopb_out_edp: endpoint@1 {
1037 remote-endpoint = <&edp_in_vopb>;
1040 vopb_out_mipi: endpoint@2 {
1042 remote-endpoint = <&mipi_in_vopb>;
1045 vopb_out_lvds: endpoint@3 {
1047 remote-endpoint = <&lvds_in_vopb>;
1052 vopb_mmu: iommu@ff930300 {
1053 compatible = "rockchip,iommu";
1054 reg = <0x0 0xff930300 0x0 0x100>;
1055 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1056 interrupt-names = "vopb_mmu";
1057 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1058 clock-names = "aclk", "iface";
1059 power-domains = <&power RK3288_PD_VIO>;
1061 status = "disabled";
1064 vopl: vop@ff940000 {
1065 compatible = "rockchip,rk3288-vop";
1066 reg = <0x0 0xff940000 0x0 0x19c>;
1067 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1069 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1070 power-domains = <&power RK3288_PD_VIO>;
1071 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1072 reset-names = "axi", "ahb", "dclk";
1073 iommus = <&vopl_mmu>;
1074 status = "disabled";
1077 #address-cells = <1>;
1080 vopl_out_hdmi: endpoint@0 {
1082 remote-endpoint = <&hdmi_in_vopl>;
1085 vopl_out_edp: endpoint@1 {
1087 remote-endpoint = <&edp_in_vopl>;
1090 vopl_out_mipi: endpoint@2 {
1092 remote-endpoint = <&mipi_in_vopl>;
1095 vopl_out_lvds: endpoint@3 {
1097 remote-endpoint = <&lvds_in_vopl>;
1102 vopl_mmu: iommu@ff940300 {
1103 compatible = "rockchip,iommu";
1104 reg = <0x0 0xff940300 0x0 0x100>;
1105 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1106 interrupt-names = "vopl_mmu";
1107 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1108 clock-names = "aclk", "iface";
1109 power-domains = <&power RK3288_PD_VIO>;
1111 status = "disabled";
1114 mipi_dsi: mipi@ff960000 {
1115 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1116 reg = <0x0 0xff960000 0x0 0x4000>;
1117 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1118 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1119 clock-names = "ref", "pclk";
1120 power-domains = <&power RK3288_PD_VIO>;
1121 rockchip,grf = <&grf>;
1122 #address-cells = <1>;
1124 status = "disabled";
1128 #address-cells = <1>;
1130 mipi_in_vopb: endpoint@0 {
1132 remote-endpoint = <&vopb_out_mipi>;
1134 mipi_in_vopl: endpoint@1 {
1136 remote-endpoint = <&vopl_out_mipi>;
1142 lvds: lvds@ff96c000 {
1143 compatible = "rockchip,rk3288-lvds";
1144 reg = <0x0 0xff96c000 0x0 0x4000>;
1145 clocks = <&cru PCLK_LVDS_PHY>;
1146 clock-names = "pclk_lvds";
1147 pinctrl-names = "lcdc";
1148 pinctrl-0 = <&lcdc_ctl>;
1149 power-domains = <&power RK3288_PD_VIO>;
1150 rockchip,grf = <&grf>;
1151 status = "disabled";
1154 #address-cells = <1>;
1160 #address-cells = <1>;
1163 lvds_in_vopb: endpoint@0 {
1165 remote-endpoint = <&vopb_out_lvds>;
1167 lvds_in_vopl: endpoint@1 {
1169 remote-endpoint = <&vopl_out_lvds>;
1176 compatible = "rockchip,rk3288-dp";
1177 reg = <0x0 0xff970000 0x0 0x4000>;
1178 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1179 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1180 clock-names = "dp", "pclk";
1183 resets = <&cru SRST_EDP>;
1185 rockchip,grf = <&grf>;
1186 status = "disabled";
1189 #address-cells = <1>;
1193 #address-cells = <1>;
1195 edp_in_vopb: endpoint@0 {
1197 remote-endpoint = <&vopb_out_edp>;
1199 edp_in_vopl: endpoint@1 {
1201 remote-endpoint = <&vopl_out_edp>;
1207 hdmi: hdmi@ff980000 {
1208 compatible = "rockchip,rk3288-dw-hdmi";
1209 reg = <0x0 0xff980000 0x0 0x20000>;
1211 #sound-dai-cells = <0>;
1212 rockchip,grf = <&grf>;
1213 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1214 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1215 clock-names = "iahb", "isfr", "cec";
1216 power-domains = <&power RK3288_PD_VIO>;
1217 status = "disabled";
1221 #address-cells = <1>;
1223 hdmi_in_vopb: endpoint@0 {
1225 remote-endpoint = <&vopb_out_hdmi>;
1227 hdmi_in_vopl: endpoint@1 {
1229 remote-endpoint = <&vopl_out_hdmi>;
1235 vpu: video-codec@ff9a0000 {
1236 compatible = "rockchip,rk3288-vpu";
1237 reg = <0x0 0xff9a0000 0x0 0x800>;
1238 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1240 interrupt-names = "vepu", "vdpu";
1241 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1242 clock-names = "aclk", "hclk";
1243 iommus = <&vpu_mmu>;
1244 power-domains = <&power RK3288_PD_VIDEO>;
1247 vpu_mmu: iommu@ff9a0800 {
1248 compatible = "rockchip,iommu";
1249 reg = <0x0 0xff9a0800 0x0 0x100>;
1250 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1251 interrupt-names = "vpu_mmu";
1252 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1253 clock-names = "aclk", "iface";
1255 power-domains = <&power RK3288_PD_VIDEO>;
1258 hevc_mmu: iommu@ff9c0440 {
1259 compatible = "rockchip,iommu";
1260 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1261 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1262 interrupt-names = "hevc_mmu";
1263 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1264 clock-names = "aclk", "iface";
1266 status = "disabled";
1270 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1271 reg = <0x0 0xffa30000 0x0 0x10000>;
1272 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1275 interrupt-names = "job", "mmu", "gpu";
1276 clocks = <&cru ACLK_GPU>;
1277 operating-points-v2 = <&gpu_opp_table>;
1278 power-domains = <&power RK3288_PD_GPU>;
1279 status = "disabled";
1282 gpu_opp_table: gpu-opp-table {
1283 compatible = "operating-points-v2";
1286 opp-hz = /bits/ 64 <100000000>;
1287 opp-microvolt = <950000>;
1290 opp-hz = /bits/ 64 <200000000>;
1291 opp-microvolt = <950000>;
1294 opp-hz = /bits/ 64 <300000000>;
1295 opp-microvolt = <1000000>;
1298 opp-hz = /bits/ 64 <400000000>;
1299 opp-microvolt = <1100000>;
1302 opp-hz = /bits/ 64 <500000000>;
1303 opp-microvolt = <1200000>;
1306 opp-hz = /bits/ 64 <600000000>;
1307 opp-microvolt = <1250000>;
1311 qos_gpu_r: qos@ffaa0000 {
1312 compatible = "syscon";
1313 reg = <0x0 0xffaa0000 0x0 0x20>;
1316 qos_gpu_w: qos@ffaa0080 {
1317 compatible = "syscon";
1318 reg = <0x0 0xffaa0080 0x0 0x20>;
1321 qos_vio1_vop: qos@ffad0000 {
1322 compatible = "syscon";
1323 reg = <0x0 0xffad0000 0x0 0x20>;
1326 qos_vio1_isp_w0: qos@ffad0100 {
1327 compatible = "syscon";
1328 reg = <0x0 0xffad0100 0x0 0x20>;
1331 qos_vio1_isp_w1: qos@ffad0180 {
1332 compatible = "syscon";
1333 reg = <0x0 0xffad0180 0x0 0x20>;
1336 qos_vio0_vop: qos@ffad0400 {
1337 compatible = "syscon";
1338 reg = <0x0 0xffad0400 0x0 0x20>;
1341 qos_vio0_vip: qos@ffad0480 {
1342 compatible = "syscon";
1343 reg = <0x0 0xffad0480 0x0 0x20>;
1346 qos_vio0_iep: qos@ffad0500 {
1347 compatible = "syscon";
1348 reg = <0x0 0xffad0500 0x0 0x20>;
1351 qos_vio2_rga_r: qos@ffad0800 {
1352 compatible = "syscon";
1353 reg = <0x0 0xffad0800 0x0 0x20>;
1356 qos_vio2_rga_w: qos@ffad0880 {
1357 compatible = "syscon";
1358 reg = <0x0 0xffad0880 0x0 0x20>;
1361 qos_vio1_isp_r: qos@ffad0900 {
1362 compatible = "syscon";
1363 reg = <0x0 0xffad0900 0x0 0x20>;
1366 qos_video: qos@ffae0000 {
1367 compatible = "syscon";
1368 reg = <0x0 0xffae0000 0x0 0x20>;
1371 qos_hevc_r: qos@ffaf0000 {
1372 compatible = "syscon";
1373 reg = <0x0 0xffaf0000 0x0 0x20>;
1376 qos_hevc_w: qos@ffaf0080 {
1377 compatible = "syscon";
1378 reg = <0x0 0xffaf0080 0x0 0x20>;
1381 gic: interrupt-controller@ffc01000 {
1382 compatible = "arm,gic-400";
1383 interrupt-controller;
1384 #interrupt-cells = <3>;
1385 #address-cells = <0>;
1387 reg = <0x0 0xffc01000 0x0 0x1000>,
1388 <0x0 0xffc02000 0x0 0x2000>,
1389 <0x0 0xffc04000 0x0 0x2000>,
1390 <0x0 0xffc06000 0x0 0x2000>;
1391 interrupts = <GIC_PPI 9 0xf04>;
1394 efuse: efuse@ffb40000 {
1395 compatible = "rockchip,rk3288-efuse";
1396 reg = <0x0 0xffb40000 0x0 0x20>;
1397 #address-cells = <1>;
1399 clocks = <&cru PCLK_EFUSE256>;
1400 clock-names = "pclk_efuse";
1402 cpu_leakage: cpu_leakage@17 {
1408 compatible = "rockchip,rk3288-pinctrl";
1409 rockchip,grf = <&grf>;
1410 rockchip,pmu = <&pmu>;
1411 #address-cells = <2>;
1415 gpio0: gpio0@ff750000 {
1416 compatible = "rockchip,gpio-bank";
1417 reg = <0x0 0xff750000 0x0 0x100>;
1418 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&cru PCLK_GPIO0>;
1424 interrupt-controller;
1425 #interrupt-cells = <2>;
1428 gpio1: gpio1@ff780000 {
1429 compatible = "rockchip,gpio-bank";
1430 reg = <0x0 0xff780000 0x0 0x100>;
1431 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1432 clocks = <&cru PCLK_GPIO1>;
1437 interrupt-controller;
1438 #interrupt-cells = <2>;
1441 gpio2: gpio2@ff790000 {
1442 compatible = "rockchip,gpio-bank";
1443 reg = <0x0 0xff790000 0x0 0x100>;
1444 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1445 clocks = <&cru PCLK_GPIO2>;
1450 interrupt-controller;
1451 #interrupt-cells = <2>;
1454 gpio3: gpio3@ff7a0000 {
1455 compatible = "rockchip,gpio-bank";
1456 reg = <0x0 0xff7a0000 0x0 0x100>;
1457 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1458 clocks = <&cru PCLK_GPIO3>;
1463 interrupt-controller;
1464 #interrupt-cells = <2>;
1467 gpio4: gpio4@ff7b0000 {
1468 compatible = "rockchip,gpio-bank";
1469 reg = <0x0 0xff7b0000 0x0 0x100>;
1470 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1471 clocks = <&cru PCLK_GPIO4>;
1476 interrupt-controller;
1477 #interrupt-cells = <2>;
1480 gpio5: gpio5@ff7c0000 {
1481 compatible = "rockchip,gpio-bank";
1482 reg = <0x0 0xff7c0000 0x0 0x100>;
1483 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1484 clocks = <&cru PCLK_GPIO5>;
1489 interrupt-controller;
1490 #interrupt-cells = <2>;
1493 gpio6: gpio6@ff7d0000 {
1494 compatible = "rockchip,gpio-bank";
1495 reg = <0x0 0xff7d0000 0x0 0x100>;
1496 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1497 clocks = <&cru PCLK_GPIO6>;
1502 interrupt-controller;
1503 #interrupt-cells = <2>;
1506 gpio7: gpio7@ff7e0000 {
1507 compatible = "rockchip,gpio-bank";
1508 reg = <0x0 0xff7e0000 0x0 0x100>;
1509 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1510 clocks = <&cru PCLK_GPIO7>;
1515 interrupt-controller;
1516 #interrupt-cells = <2>;
1519 gpio8: gpio8@ff7f0000 {
1520 compatible = "rockchip,gpio-bank";
1521 reg = <0x0 0xff7f0000 0x0 0x100>;
1522 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1523 clocks = <&cru PCLK_GPIO8>;
1528 interrupt-controller;
1529 #interrupt-cells = <2>;
1533 hdmi_cec_c0: hdmi-cec-c0 {
1534 rockchip,pins = <7 RK_PC0 RK_FUNC_2 &pcfg_pull_none>;
1537 hdmi_cec_c7: hdmi-cec-c7 {
1538 rockchip,pins = <7 RK_PC7 RK_FUNC_4 &pcfg_pull_none>;
1541 hdmi_ddc: hdmi-ddc {
1542 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1543 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1547 pcfg_pull_up: pcfg-pull-up {
1551 pcfg_pull_down: pcfg-pull-down {
1555 pcfg_pull_none: pcfg-pull-none {
1559 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1561 drive-strength = <12>;
1565 global_pwroff: global-pwroff {
1566 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1569 ddrio_pwroff: ddrio-pwroff {
1570 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1573 ddr0_retention: ddr0-retention {
1574 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1577 ddr1_retention: ddr1-retention {
1578 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1584 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1589 i2c0_xfer: i2c0-xfer {
1590 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1591 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1596 i2c1_xfer: i2c1-xfer {
1597 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1598 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1603 i2c2_xfer: i2c2-xfer {
1604 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1605 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1610 i2c3_xfer: i2c3-xfer {
1611 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1612 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1617 i2c4_xfer: i2c4-xfer {
1618 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1619 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1624 i2c5_xfer: i2c5-xfer {
1625 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1626 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1631 i2s0_bus: i2s0-bus {
1632 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1633 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1634 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1635 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1636 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1637 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1642 lcdc_ctl: lcdc-ctl {
1643 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1644 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1645 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1646 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1651 sdmmc_clk: sdmmc-clk {
1652 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1655 sdmmc_cmd: sdmmc-cmd {
1656 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1659 sdmmc_cd: sdmmc-cd {
1660 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1663 sdmmc_bus1: sdmmc-bus1 {
1664 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1667 sdmmc_bus4: sdmmc-bus4 {
1668 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1669 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1670 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1671 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1676 sdio0_bus1: sdio0-bus1 {
1677 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1680 sdio0_bus4: sdio0-bus4 {
1681 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1682 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1683 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1684 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1687 sdio0_cmd: sdio0-cmd {
1688 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1691 sdio0_clk: sdio0-clk {
1692 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1695 sdio0_cd: sdio0-cd {
1696 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1699 sdio0_wp: sdio0-wp {
1700 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1703 sdio0_pwr: sdio0-pwr {
1704 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1707 sdio0_bkpwr: sdio0-bkpwr {
1708 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1711 sdio0_int: sdio0-int {
1712 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1717 sdio1_bus1: sdio1-bus1 {
1718 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1721 sdio1_bus4: sdio1-bus4 {
1722 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1723 <3 25 4 &pcfg_pull_up>,
1724 <3 26 4 &pcfg_pull_up>,
1725 <3 27 4 &pcfg_pull_up>;
1728 sdio1_cd: sdio1-cd {
1729 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1732 sdio1_wp: sdio1-wp {
1733 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1736 sdio1_bkpwr: sdio1-bkpwr {
1737 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1740 sdio1_int: sdio1-int {
1741 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1744 sdio1_cmd: sdio1-cmd {
1745 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1748 sdio1_clk: sdio1-clk {
1749 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1752 sdio1_pwr: sdio1-pwr {
1753 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1758 emmc_clk: emmc-clk {
1759 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1762 emmc_cmd: emmc-cmd {
1763 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1766 emmc_pwr: emmc-pwr {
1767 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1770 emmc_bus1: emmc-bus1 {
1771 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1774 emmc_bus4: emmc-bus4 {
1775 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1776 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1777 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1778 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1781 emmc_bus8: emmc-bus8 {
1782 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1783 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1784 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1785 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1786 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1787 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1788 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1789 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1794 spi0_clk: spi0-clk {
1795 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1797 spi0_cs0: spi0-cs0 {
1798 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1801 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1804 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1806 spi0_cs1: spi0-cs1 {
1807 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1811 spi1_clk: spi1-clk {
1812 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1814 spi1_cs0: spi1-cs0 {
1815 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1818 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1821 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1826 spi2_cs1: spi2-cs1 {
1827 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1829 spi2_clk: spi2-clk {
1830 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1832 spi2_cs0: spi2-cs0 {
1833 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1836 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1839 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1844 uart0_xfer: uart0-xfer {
1845 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1846 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1849 uart0_cts: uart0-cts {
1850 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1853 uart0_rts: uart0-rts {
1854 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1859 uart1_xfer: uart1-xfer {
1860 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1861 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1864 uart1_cts: uart1-cts {
1865 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1868 uart1_rts: uart1-rts {
1869 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1874 uart2_xfer: uart2-xfer {
1875 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1876 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1878 /* no rts / cts for uart2 */
1882 uart3_xfer: uart3-xfer {
1883 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1884 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1887 uart3_cts: uart3-cts {
1888 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1891 uart3_rts: uart3-rts {
1892 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1897 uart4_xfer: uart4-xfer {
1898 rockchip,pins = <5 15 3 &pcfg_pull_up>,
1899 <5 14 3 &pcfg_pull_none>;
1902 uart4_cts: uart4-cts {
1903 rockchip,pins = <5 12 3 &pcfg_pull_up>;
1906 uart4_rts: uart4-rts {
1907 rockchip,pins = <5 13 3 &pcfg_pull_none>;
1912 otp_gpio: otp-gpio {
1913 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1917 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1922 pwm0_pin: pwm0-pin {
1923 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1928 pwm1_pin: pwm1-pin {
1929 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1934 pwm2_pin: pwm2-pin {
1935 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1940 pwm3_pin: pwm3-pin {
1941 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1946 rgmii_pins: rgmii-pins {
1947 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1948 <3 31 3 &pcfg_pull_none>,
1949 <3 26 3 &pcfg_pull_none>,
1950 <3 27 3 &pcfg_pull_none>,
1951 <3 28 3 &pcfg_pull_none_12ma>,
1952 <3 29 3 &pcfg_pull_none_12ma>,
1953 <3 24 3 &pcfg_pull_none_12ma>,
1954 <3 25 3 &pcfg_pull_none_12ma>,
1955 <4 0 3 &pcfg_pull_none>,
1956 <4 5 3 &pcfg_pull_none>,
1957 <4 6 3 &pcfg_pull_none>,
1958 <4 9 3 &pcfg_pull_none_12ma>,
1959 <4 4 3 &pcfg_pull_none_12ma>,
1960 <4 1 3 &pcfg_pull_none>,
1961 <4 3 3 &pcfg_pull_none>;
1964 rmii_pins: rmii-pins {
1965 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1966 <3 31 3 &pcfg_pull_none>,
1967 <3 28 3 &pcfg_pull_none>,
1968 <3 29 3 &pcfg_pull_none>,
1969 <4 0 3 &pcfg_pull_none>,
1970 <4 5 3 &pcfg_pull_none>,
1971 <4 4 3 &pcfg_pull_none>,
1972 <4 1 3 &pcfg_pull_none>,
1973 <4 2 3 &pcfg_pull_none>,
1974 <4 3 3 &pcfg_pull_none>;
1979 spdif_tx: spdif-tx {
1980 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;