arch/arm/boot/dts/stih407-family.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics Limited.
   3  * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "stih407-pinctrl.dtsi"
  10 #include <dt-bindings/mfd/st-lpc.h>
  11 #include <dt-bindings/phy/phy.h>
  12 #include <dt-bindings/reset/stih407-resets.h>
  13 #include <dt-bindings/interrupt-controller/irq-st.h>
  14 / {
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         reg = <0>;
  25
  26                         /* u-boot puts hpen in SBC dmem at 0xa4 offset */
  27                         cpu-release-addr = <0x94100A4>;
  28
  29                                          /* kHz     uV   */
  30                         operating-points = <1500000 0
  31                                             1200000 0
  32                                             800000  0
  33                                             500000  0>;
  34
  35                         clocks = <&clk_m_a9>;
  36                         clock-names = "cpu";
  37                         clock-latency = <100000>;
  38                         cpu0-supply = <&pwm_regulator>;
  39                         st,syscfg = <&syscfg_core 0x8e0>;
  40                 };
  41                 cpu@1 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a9";
  44                         reg = <1>;
  45
  46                         /* u-boot puts hpen in SBC dmem at 0xa4 offset */
  47                         cpu-release-addr = <0x94100A4>;
  48
  49                                          /* kHz     uV   */
  50                         operating-points = <1500000 0
  51                                             1200000 0
  52                                             800000  0
  53                                             500000  0>;
  54                 };
  55         };
  56
  57         intc: interrupt-controller@08761000 {
  58                 compatible = "arm,cortex-a9-gic";
  59                 #interrupt-cells = <3>;
  60                 interrupt-controller;
  61                 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
  62         };
  63
  64         scu@08760000 {
  65                 compatible = "arm,cortex-a9-scu";
  66                 reg = <0x08760000 0x1000>;
  67         };
  68
  69         timer@08760200 {
  70                 interrupt-parent = <&intc>;
  71                 compatible = "arm,cortex-a9-global-timer";
  72                 reg = <0x08760200 0x100>;
  73                 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  74                 clocks = <&arm_periph_clk>;
  75         };
  76
  77         l2: cache-controller {
  78                 compatible = "arm,pl310-cache";
  79                 reg = <0x08762000 0x1000>;
  80                 arm,data-latency = <3 3 3>;
  81                 arm,tag-latency = <2 2 2>;
  82                 cache-unified;
  83                 cache-level = <2>;
  84         };
  85
  86         arm-pmu {
  87                 interrupt-parent = <&intc>;
  88                 compatible = "arm,cortex-a9-pmu";
  89                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
  90         };
  91
  92         pwm_regulator: pwm-regulator {
  93                 compatible = "pwm-regulator";
  94                 pwms = <&pwm1 3 8448>;
  95                 regulator-name = "CPU_1V0_AVS";
  96                 regulator-min-microvolt = <784000>;
  97                 regulator-max-microvolt = <1299000>;
  98                 regulator-always-on;
  99                 max-duty-cycle = <255>;
 100                 status = "okay";
 101         };
 102
 103         soc {
 104                 #address-cells = <1>;
 105                 #size-cells = <1>;
 106                 interrupt-parent = <&intc>;
 107                 ranges;
 108                 compatible = "simple-bus";
 109
 110                 restart {
 111                         compatible = "st,stih407-restart";
 112                         st,syscfg = <&syscfg_sbc_reg>;
 113                         status = "okay";
 114                 };
 115
 116                 powerdown: powerdown-controller {
 117                         compatible = "st,stih407-powerdown";
 118                         #reset-cells = <1>;
 119                 };
 120
 121                 softreset: softreset-controller {
 122                         compatible = "st,stih407-softreset";
 123                         #reset-cells = <1>;
 124                 };
 125
 126                 picophyreset: picophyreset-controller {
 127                         compatible = "st,stih407-picophyreset";
 128                         #reset-cells = <1>;
 129                 };
 130
 131                 syscfg_sbc: sbc-syscfg@9620000 {
 132                         compatible = "st,stih407-sbc-syscfg", "syscon";
 133                         reg = <0x9620000 0x1000>;
 134                 };
 135
 136                 syscfg_front: front-syscfg@9280000 {
 137                         compatible = "st,stih407-front-syscfg", "syscon";
 138                         reg = <0x9280000 0x1000>;
 139                 };
 140
 141                 syscfg_rear: rear-syscfg@9290000 {
 142                         compatible = "st,stih407-rear-syscfg", "syscon";
 143                         reg = <0x9290000 0x1000>;
 144                 };
 145
 146                 syscfg_flash: flash-syscfg@92a0000 {
 147                         compatible = "st,stih407-flash-syscfg", "syscon";
 148                         reg = <0x92a0000 0x1000>;
 149                 };
 150
 151                 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
 152                         compatible = "st,stih407-sbc-reg-syscfg", "syscon";
 153                         reg = <0x9600000 0x1000>;
 154                 };
 155
 156                 syscfg_core: core-syscfg@92b0000 {
 157                         compatible = "st,stih407-core-syscfg", "syscon";
 158                         reg = <0x92b0000 0x1000>;
 159                 };
 160
 161                 syscfg_lpm: lpm-syscfg@94b5100 {
 162                         compatible = "st,stih407-lpm-syscfg", "syscon";
 163                         reg = <0x94b5100 0x1000>;
 164                 };
 165
 166                 irq-syscfg {
 167                         compatible    = "st,stih407-irq-syscfg";
 168                         st,syscfg     = <&syscfg_core>;
 169                         st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
 170                                         <ST_IRQ_SYSCFG_PMU_1>;
 171                         st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
 172                                         <ST_IRQ_SYSCFG_DISABLED>;
 173                 };
 174
 175                 /* Display */
 176                 vtg_main: sti-vtg-main@8d02800 {
 177                         compatible = "st,vtg";
 178                         reg = <0x8d02800 0x200>;
 179                         interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
 180                 };
 181
 182                 vtg_aux: sti-vtg-aux@8d00200 {
 183                         compatible = "st,vtg";
 184                         reg = <0x8d00200 0x100>;
 185                         interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
 186                 };
 187
 188                 serial@9830000 {
 189                         compatible = "st,asc";
 190                         reg = <0x9830000 0x2c>;
 191                         interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
 192                         pinctrl-names = "default";
 193                         pinctrl-0 = <&pinctrl_serial0>;
 194                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 195
 196                         status = "disabled";
 197                 };
 198
 199                 serial@9831000 {
 200                         compatible = "st,asc";
 201                         reg = <0x9831000 0x2c>;
 202                         interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
 203                         pinctrl-names = "default";
 204                         pinctrl-0 = <&pinctrl_serial1>;
 205                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 206
 207                         status = "disabled";
 208                 };
 209
 210                 serial@9832000 {
 211                         compatible = "st,asc";
 212                         reg = <0x9832000 0x2c>;
 213                         interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
 214                         pinctrl-names = "default";
 215                         pinctrl-0 = <&pinctrl_serial2>;
 216                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 217
 218                         status = "disabled";
 219                 };
 220
 221                 /* SBC_ASC0 - UART10 */
 222                 sbc_serial0: serial@9530000 {
 223                         compatible = "st,asc";
 224                         reg = <0x9530000 0x2c>;
 225                         interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
 226                         pinctrl-names = "default";
 227                         pinctrl-0 = <&pinctrl_sbc_serial0>;
 228                         clocks = <&clk_sysin>;
 229
 230                         status = "disabled";
 231                 };
 232
 233                 serial@9531000 {
 234                         compatible = "st,asc";
 235                         reg = <0x9531000 0x2c>;
 236                         interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
 237                         pinctrl-names = "default";
 238                         pinctrl-0 = <&pinctrl_sbc_serial1>;
 239                         clocks = <&clk_sysin>;
 240
 241                         status = "disabled";
 242                 };
 243
 244                 i2c@9840000 {
 245                         compatible = "st,comms-ssc4-i2c";
 246                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 247                         reg = <0x9840000 0x110>;
 248                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 249                         clock-names = "ssc";
 250                         clock-frequency = <400000>;
 251                         pinctrl-names = "default";
 252                         pinctrl-0 = <&pinctrl_i2c0_default>;
 253
 254                         status = "disabled";
 255                 };
 256
 257                 i2c@9841000 {
 258                         compatible = "st,comms-ssc4-i2c";
 259                         reg = <0x9841000 0x110>;
 260                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 261                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 262                         clock-names = "ssc";
 263                         clock-frequency = <400000>;
 264                         pinctrl-names = "default";
 265                         pinctrl-0 = <&pinctrl_i2c1_default>;
 266
 267                         status = "disabled";
 268                 };
 269
 270                 i2c@9842000 {
 271                         compatible = "st,comms-ssc4-i2c";
 272                         reg = <0x9842000 0x110>;
 273                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 274                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 275                         clock-names = "ssc";
 276                         clock-frequency = <400000>;
 277                         pinctrl-names = "default";
 278                         pinctrl-0 = <&pinctrl_i2c2_default>;
 279
 280                         status = "disabled";
 281                 };
 282
 283                 i2c@9843000 {
 284                         compatible = "st,comms-ssc4-i2c";
 285                         reg = <0x9843000 0x110>;
 286                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 287                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 288                         clock-names = "ssc";
 289                         clock-frequency = <400000>;
 290                         pinctrl-names = "default";
 291                         pinctrl-0 = <&pinctrl_i2c3_default>;
 292
 293                         status = "disabled";
 294                 };
 295
 296                 i2c@9844000 {
 297                         compatible = "st,comms-ssc4-i2c";
 298                         reg = <0x9844000 0x110>;
 299                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 300                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 301                         clock-names = "ssc";
 302                         clock-frequency = <400000>;
 303                         pinctrl-names = "default";
 304                         pinctrl-0 = <&pinctrl_i2c4_default>;
 305
 306                         status = "disabled";
 307                 };
 308
 309                 i2c@9845000 {
 310                         compatible = "st,comms-ssc4-i2c";
 311                         reg = <0x9845000 0x110>;
 312                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 313                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 314                         clock-names = "ssc";
 315                         clock-frequency = <400000>;
 316                         pinctrl-names = "default";
 317                         pinctrl-0 = <&pinctrl_i2c5_default>;
 318
 319                         status = "disabled";
 320                 };
 321
 322
 323                 /* SSCs on SBC */
 324                 i2c@9540000 {
 325                         compatible = "st,comms-ssc4-i2c";
 326                         reg = <0x9540000 0x110>;
 327                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 328                         clocks = <&clk_sysin>;
 329                         clock-names = "ssc";
 330                         clock-frequency = <400000>;
 331                         pinctrl-names = "default";
 332                         pinctrl-0 = <&pinctrl_i2c10_default>;
 333
 334                         status = "disabled";
 335                 };
 336
 337                 i2c@9541000 {
 338                         compatible = "st,comms-ssc4-i2c";
 339                         reg = <0x9541000 0x110>;
 340                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 341                         clocks = <&clk_sysin>;
 342                         clock-names = "ssc";
 343                         clock-frequency = <400000>;
 344                         pinctrl-names = "default";
 345                         pinctrl-0 = <&pinctrl_i2c11_default>;
 346
 347                         status = "disabled";
 348                 };
 349
 350                 usb2_picophy0: phy1 {
 351                         compatible = "st,stih407-usb2-phy";
 352                         #phy-cells = <0>;
 353                         st,syscfg = <&syscfg_core 0x100 0xf4>;
 354                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
 355                                  <&picophyreset STIH407_PICOPHY2_RESET>;
 356                         reset-names = "global", "port";
 357                 };
 358
 359                 miphy28lp_phy: miphy28lp@9b22000 {
 360                         compatible = "st,miphy28lp-phy";
 361                         st,syscfg = <&syscfg_core>;
 362                         #address-cells  = <1>;
 363                         #size-cells     = <1>;
 364                         ranges;
 365
 366                         phy_port0: port@9b22000 {
 367                                 reg = <0x9b22000 0xff>,
 368                                       <0x9b09000 0xff>,
 369                                       <0x9b04000 0xff>;
 370                                 reg-names = "sata-up",
 371                                             "pcie-up",
 372                                             "pipew";
 373
 374                                 st,syscfg = <0x114 0x818 0xe0 0xec>;
 375                                 #phy-cells = <1>;
 376
 377                                 reset-names = "miphy-sw-rst";
 378                                 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
 379                         };
 380
 381                         phy_port1: port@9b2a000 {
 382                                 reg = <0x9b2a000 0xff>,
 383                                       <0x9b19000 0xff>,
 384                                       <0x9b14000 0xff>;
 385                                 reg-names = "sata-up",
 386                                             "pcie-up",
 387                                             "pipew";
 388
 389                                 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
 390
 391                                 #phy-cells = <1>;
 392
 393                                 reset-names = "miphy-sw-rst";
 394                                 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
 395                         };
 396
 397                         phy_port2: port@8f95000 {
 398                                 reg = <0x8f95000 0xff>,
 399                                       <0x8f90000 0xff>;
 400                                 reg-names = "pipew",
 401                                             "usb3-up";
 402
 403                                 st,syscfg = <0x11c 0x820>;
 404
 405                                 #phy-cells = <1>;
 406
 407                                 reset-names = "miphy-sw-rst";
 408                                 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
 409                         };
 410                 };
 411
 412                 spi@9840000 {
 413                         compatible = "st,comms-ssc4-spi";
 414                         reg = <0x9840000 0x110>;
 415                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 416                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 417                         clock-names = "ssc";
 418                         pinctrl-0 = <&pinctrl_spi0_default>;
 419                         pinctrl-names = "default";
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422
 423                         status = "disabled";
 424                 };
 425
 426                 spi@9841000 {
 427                         compatible = "st,comms-ssc4-spi";
 428                         reg = <0x9841000 0x110>;
 429                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 430                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 431                         clock-names = "ssc";
 432                         pinctrl-names = "default";
 433                         pinctrl-0 = <&pinctrl_spi1_default>;
 434
 435                         status = "disabled";
 436                 };
 437
 438                 spi@9842000 {
 439                         compatible = "st,comms-ssc4-spi";
 440                         reg = <0x9842000 0x110>;
 441                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 442                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 443                         clock-names = "ssc";
 444                         pinctrl-names = "default";
 445                         pinctrl-0 = <&pinctrl_spi2_default>;
 446
 447                         status = "disabled";
 448                 };
 449
 450                 spi@9843000 {
 451                         compatible = "st,comms-ssc4-spi";
 452                         reg = <0x9843000 0x110>;
 453                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 454                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 455                         clock-names = "ssc";
 456                         pinctrl-names = "default";
 457                         pinctrl-0 = <&pinctrl_spi3_default>;
 458
 459                         status = "disabled";
 460                 };
 461
 462                 spi@9844000 {
 463                         compatible = "st,comms-ssc4-spi";
 464                         reg = <0x9844000 0x110>;
 465                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 466                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 467                         clock-names = "ssc";
 468                         pinctrl-names = "default";
 469                         pinctrl-0 = <&pinctrl_spi4_default>;
 470
 471                         status = "disabled";
 472                 };
 473
 474                 /* SBC SSC */
 475                 spi@9540000 {
 476                         compatible = "st,comms-ssc4-spi";
 477                         reg = <0x9540000 0x110>;
 478                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 479                         clocks = <&clk_sysin>;
 480                         clock-names = "ssc";
 481                         pinctrl-names = "default";
 482                         pinctrl-0 = <&pinctrl_spi10_default>;
 483
 484                         status = "disabled";
 485                 };
 486
 487                 spi@9541000 {
 488                         compatible = "st,comms-ssc4-spi";
 489                         reg = <0x9541000 0x110>;
 490                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 491                         clocks = <&clk_sysin>;
 492                         clock-names = "ssc";
 493                         pinctrl-names = "default";
 494                         pinctrl-0 = <&pinctrl_spi11_default>;
 495
 496                         status = "disabled";
 497                 };
 498
 499                 spi@9542000 {
 500                         compatible = "st,comms-ssc4-spi";
 501                         reg = <0x9542000 0x110>;
 502                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 503                         clocks = <&clk_sysin>;
 504                         clock-names = "ssc";
 505                         pinctrl-names = "default";
 506                         pinctrl-0 = <&pinctrl_spi12_default>;
 507
 508                         status = "disabled";
 509                 };
 510
 511                 mmc0: sdhci@09060000 {
 512                         compatible = "st,sdhci-stih407", "st,sdhci";
 513                         status = "disabled";
 514                         reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
 515                         reg-names = "mmc", "top-mmc-delay";
 516                         interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
 517                         interrupt-names = "mmcirq";
 518                         pinctrl-names = "default";
 519                         pinctrl-0 = <&pinctrl_mmc0>;
 520                         clock-names = "mmc";
 521                         clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
 522                         bus-width = <8>;
 523                         non-removable;
 524                 };
 525
 526                 mmc1: sdhci@09080000 {
 527                         compatible = "st,sdhci-stih407", "st,sdhci";
 528                         status = "disabled";
 529                         reg = <0x09080000 0x7ff>;
 530                         reg-names = "mmc";
 531                         interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
 532                         interrupt-names = "mmcirq";
 533                         pinctrl-names = "default";
 534                         pinctrl-0 = <&pinctrl_sd1>;
 535                         clock-names = "mmc";
 536                         clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
 537                         resets = <&softreset STIH407_MMC1_SOFTRESET>;
 538                         bus-width = <4>;
 539                 };
 540
 541                 /* Watchdog and Real-Time Clock */
 542                 lpc@8787000 {
 543                         compatible = "st,stih407-lpc";
 544                         reg = <0x8787000 0x1000>;
 545                         interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
 546                         clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
 547                         timeout-sec = <120>;
 548                         st,syscfg = <&syscfg_core>;
 549                         st,lpc-mode = <ST_LPC_MODE_WDT>;
 550                 };
 551
 552                 lpc@8788000 {
 553                         compatible = "st,stih407-lpc";
 554                         reg = <0x8788000 0x1000>;
 555                         interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
 556                         clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
 557                         st,lpc-mode = <ST_LPC_MODE_RTC>;
 558                 };
 559
 560                 sata0: sata@9b20000 {
 561                         compatible = "st,ahci";
 562                         reg = <0x9b20000 0x1000>;
 563
 564                         interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
 565                         interrupt-names = "hostc";
 566
 567                         phys = <&phy_port0 PHY_TYPE_SATA>;
 568                         phy-names = "ahci_phy";
 569
 570                         resets = <&powerdown STIH407_SATA0_POWERDOWN>,
 571                                  <&softreset STIH407_SATA0_SOFTRESET>,
 572                                  <&softreset STIH407_SATA0_PWR_SOFTRESET>;
 573                         reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
 574
 575                         clock-names = "ahci_clk";
 576                         clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
 577
 578                         status = "disabled";
 579                 };
 580
 581                 sata1: sata@9b28000 {
 582                         compatible = "st,ahci";
 583                         reg = <0x9b28000 0x1000>;
 584
 585                         interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
 586                         interrupt-names = "hostc";
 587
 588                         phys = <&phy_port1 PHY_TYPE_SATA>;
 589                         phy-names = "ahci_phy";
 590
 591                         resets = <&powerdown STIH407_SATA1_POWERDOWN>,
 592                                  <&softreset STIH407_SATA1_SOFTRESET>,
 593                                  <&softreset STIH407_SATA1_PWR_SOFTRESET>;
 594                         reset-names = "pwr-dwn",
 595                                       "sw-rst",
 596                                       "pwr-rst";
 597
 598                         clock-names = "ahci_clk";
 599                         clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
 600
 601                         status = "disabled";
 602                 };
 603
 604
 605                 st_dwc3: dwc3@8f94000 {
 606                         compatible      = "st,stih407-dwc3";
 607                         reg             = <0x08f94000 0x1000>, <0x110 0x4>;
 608                         reg-names       = "reg-glue", "syscfg-reg";
 609                         st,syscfg       = <&syscfg_core>;
 610                         resets          = <&powerdown STIH407_USB3_POWERDOWN>,
 611                                           <&softreset STIH407_MIPHY2_SOFTRESET>;
 612                         reset-names     = "powerdown", "softreset";
 613                         #address-cells  = <1>;
 614                         #size-cells     = <1>;
 615                         pinctrl-names   = "default";
 616                         pinctrl-0       = <&pinctrl_usb3>;
 617                         ranges;
 618
 619                         status = "disabled";
 620
 621                         dwc3: dwc3@9900000 {
 622                                 compatible      = "snps,dwc3";
 623                                 reg             = <0x09900000 0x100000>;
 624                                 interrupts      = <GIC_SPI 155 IRQ_TYPE_NONE>;
 625                                 dr_mode         = "host";
 626                                 phy-names       = "usb2-phy", "usb3-phy";
 627                                 phys            = <&usb2_picophy0>,
 628                                                   <&phy_port2 PHY_TYPE_USB3>;
 629                         };
 630                 };
 631
 632                 /* COMMS PWM Module */
 633                 pwm0: pwm@9810000 {
 634                         compatible      = "st,sti-pwm";
 635                         #pwm-cells      = <2>;
 636                         reg             = <0x9810000 0x68>;
 637                         pinctrl-names   = "default";
 638                         pinctrl-0       = <&pinctrl_pwm0_chan0_default>;
 639                         clock-names     = "pwm";
 640                         clocks          = <&clk_sysin>;
 641                         st,pwm-num-chan = <1>;
 642
 643                         status          = "disabled";
 644                 };
 645
 646                 /* SBC PWM Module */
 647                 pwm1: pwm@9510000 {
 648                         compatible      = "st,sti-pwm";
 649                         #pwm-cells      = <2>;
 650                         reg             = <0x9510000 0x68>;
 651                         pinctrl-names   = "default";
 652                         pinctrl-0       = <&pinctrl_pwm1_chan0_default
 653                                         &pinctrl_pwm1_chan1_default
 654                                         &pinctrl_pwm1_chan2_default
 655                                         &pinctrl_pwm1_chan3_default>;
 656                         clock-names     = "pwm";
 657                         clocks          = <&clk_sysin>;
 658                         st,pwm-num-chan = <4>;
 659
 660                         status          = "disabled";
 661                 };
 662
 663                 rng10: rng@08a89000 {
 664                         compatible      = "st,rng";
 665                         reg             = <0x08a89000 0x1000>;
 666                         clocks          = <&clk_sysin>;
 667                         status          = "okay";
 668                 };
 669
 670                 rng11: rng@08a8a000 {
 671                         compatible      = "st,rng";
 672                         reg             = <0x08a8a000 0x1000>;
 673                         clocks          = <&clk_sysin>;
 674                         status          = "okay";
 675                 };
 676
 677                 ethernet0: dwmac@9630000 {
 678                         device_type = "network";
 679                         status = "disabled";
 680                         compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
 681                         reg = <0x9630000 0x8000>, <0x80 0x4>;
 682                         reg-names = "stmmaceth", "sti-ethconf";
 683
 684                         st,syscon = <&syscfg_sbc_reg 0x80>;
 685                         st,gmac_en;
 686                         resets = <&softreset STIH407_ETH1_SOFTRESET>;
 687                         reset-names = "stmmaceth";
 688
 689                         interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
 690                                      <GIC_SPI 99 IRQ_TYPE_NONE>;
 691                         interrupt-names = "macirq", "eth_wake_irq";
 692
 693                         /* DMA Bus Mode */
 694                         snps,pbl = <8>;
 695
 696                         pinctrl-names = "default";
 697                         pinctrl-0 = <&pinctrl_rgmii1>;
 698
 699                         clock-names = "stmmaceth", "sti-ethclk";
 700                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
 701                                  <&clk_s_c0_flexgen CLK_ETH_PHY>;
 702                 };
 703
 704                 rng10: rng@08a89000 {
 705                         compatible      = "st,rng";
 706                         reg             = <0x08a89000 0x1000>;
 707                         clocks          = <&clk_sysin>;
 708                         status          = "okay";
 709                 };
 710
 711                 rng11: rng@08a8a000 {
 712                         compatible      = "st,rng";
 713                         reg             = <0x08a8a000 0x1000>;
 714                         clocks          = <&clk_sysin>;
 715                         status          = "okay";
 716                 };
 717         };
 718 };