2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
59 compatible = "fixed-clock";
60 clock-frequency = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
75 clk_i2s_ckin: i2s-ckin {
77 compatible = "fixed-clock";
78 clock-frequency = <0>;
83 romem: nvmem@1fff7800 {
84 compatible = "st,stm32f4-otp";
85 reg = <0x1fff7800 0x400>;
96 timer2: timer@40000000 {
97 compatible = "st,stm32-timer";
98 reg = <0x40000000 0x400>;
100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
104 timers2: timers@40000000 {
105 #address-cells = <1>;
107 compatible = "st,stm32-timers";
108 reg = <0x40000000 0x400>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
114 compatible = "st,stm32-pwm";
119 compatible = "st,stm32-timer-trigger";
125 timer3: timer@40000400 {
126 compatible = "st,stm32-timer";
127 reg = <0x40000400 0x400>;
129 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
133 timers3: timers@40000400 {
134 #address-cells = <1>;
136 compatible = "st,stm32-timers";
137 reg = <0x40000400 0x400>;
138 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
143 compatible = "st,stm32-pwm";
148 compatible = "st,stm32-timer-trigger";
154 timer4: timer@40000800 {
155 compatible = "st,stm32-timer";
156 reg = <0x40000800 0x400>;
158 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
162 timers4: timers@40000800 {
163 #address-cells = <1>;
165 compatible = "st,stm32-timers";
166 reg = <0x40000800 0x400>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
172 compatible = "st,stm32-pwm";
177 compatible = "st,stm32-timer-trigger";
183 timer5: timer@40000c00 {
184 compatible = "st,stm32-timer";
185 reg = <0x40000c00 0x400>;
187 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
190 timers5: timers@40000c00 {
191 #address-cells = <1>;
193 compatible = "st,stm32-timers";
194 reg = <0x40000C00 0x400>;
195 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
200 compatible = "st,stm32-pwm";
205 compatible = "st,stm32-timer-trigger";
211 timer6: timer@40001000 {
212 compatible = "st,stm32-timer";
213 reg = <0x40001000 0x400>;
215 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
219 timers6: timers@40001000 {
220 #address-cells = <1>;
222 compatible = "st,stm32-timers";
223 reg = <0x40001000 0x400>;
224 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
229 compatible = "st,stm32-timer-trigger";
235 timer7: timer@40001400 {
236 compatible = "st,stm32-timer";
237 reg = <0x40001400 0x400>;
239 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
243 timers7: timers@40001400 {
244 #address-cells = <1>;
246 compatible = "st,stm32-timers";
247 reg = <0x40001400 0x400>;
248 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
253 compatible = "st,stm32-timer-trigger";
259 timers12: timers@40001800 {
260 #address-cells = <1>;
262 compatible = "st,stm32-timers";
263 reg = <0x40001800 0x400>;
264 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
269 compatible = "st,stm32-pwm";
274 compatible = "st,stm32-timer-trigger";
280 timers13: timers@40001c00 {
281 #address-cells = <1>;
283 compatible = "st,stm32-timers";
284 reg = <0x40001C00 0x400>;
285 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
290 compatible = "st,stm32-pwm";
295 timers14: timers@40002000 {
296 #address-cells = <1>;
298 compatible = "st,stm32-timers";
299 reg = <0x40002000 0x400>;
300 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
305 compatible = "st,stm32-pwm";
311 compatible = "st,stm32-rtc";
312 reg = <0x40002800 0x400>;
313 clocks = <&rcc 1 CLK_RTC>;
314 clock-names = "ck_rtc";
315 assigned-clocks = <&rcc 1 CLK_RTC>;
316 assigned-clock-parents = <&rcc 1 CLK_LSE>;
317 interrupt-parent = <&exti>;
319 interrupt-names = "alarm";
320 st,syscfg = <&pwrcfg 0x00 0x100>;
324 iwdg: watchdog@40003000 {
325 compatible = "st,stm32-iwdg";
326 reg = <0x40003000 0x400>;
333 #address-cells = <1>;
335 compatible = "st,stm32f4-spi";
336 reg = <0x40003800 0x400>;
338 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
343 #address-cells = <1>;
345 compatible = "st,stm32f4-spi";
346 reg = <0x40003c00 0x400>;
348 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
352 usart2: serial@40004400 {
353 compatible = "st,stm32-uart";
354 reg = <0x40004400 0x400>;
356 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
360 usart3: serial@40004800 {
361 compatible = "st,stm32-uart";
362 reg = <0x40004800 0x400>;
364 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
366 dmas = <&dma1 1 4 0x400 0x0>,
367 <&dma1 3 4 0x400 0x0>;
368 dma-names = "rx", "tx";
371 usart4: serial@40004c00 {
372 compatible = "st,stm32-uart";
373 reg = <0x40004c00 0x400>;
375 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
379 usart5: serial@40005000 {
380 compatible = "st,stm32-uart";
381 reg = <0x40005000 0x400>;
383 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
388 compatible = "st,stm32f4-i2c";
389 reg = <0x40005400 0x400>;
392 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
393 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
394 #address-cells = <1>;
400 compatible = "st,stm32f4-dac-core";
401 reg = <0x40007400 0x400>;
402 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
403 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
404 clock-names = "pclk";
405 #address-cells = <1>;
410 compatible = "st,stm32-dac";
411 #io-channels-cells = <1>;
417 compatible = "st,stm32-dac";
418 #io-channels-cells = <1>;
424 usart7: serial@40007800 {
425 compatible = "st,stm32-uart";
426 reg = <0x40007800 0x400>;
428 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
432 usart8: serial@40007c00 {
433 compatible = "st,stm32-uart";
434 reg = <0x40007c00 0x400>;
436 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
440 timers1: timers@40010000 {
441 #address-cells = <1>;
443 compatible = "st,stm32-timers";
444 reg = <0x40010000 0x400>;
445 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
450 compatible = "st,stm32-pwm";
455 compatible = "st,stm32-timer-trigger";
461 timers8: timers@40010400 {
462 #address-cells = <1>;
464 compatible = "st,stm32-timers";
465 reg = <0x40010400 0x400>;
466 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
471 compatible = "st,stm32-pwm";
476 compatible = "st,stm32-timer-trigger";
482 usart1: serial@40011000 {
483 compatible = "st,stm32-uart";
484 reg = <0x40011000 0x400>;
486 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
488 dmas = <&dma2 2 4 0x400 0x0>,
489 <&dma2 7 4 0x400 0x0>;
490 dma-names = "rx", "tx";
493 usart6: serial@40011400 {
494 compatible = "st,stm32-uart";
495 reg = <0x40011400 0x400>;
497 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
502 compatible = "st,stm32f4-adc-core";
503 reg = <0x40012000 0x400>;
505 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
507 interrupt-controller;
508 #interrupt-cells = <1>;
509 #address-cells = <1>;
514 compatible = "st,stm32f4-adc";
515 #io-channel-cells = <1>;
517 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
518 interrupt-parent = <&adc>;
520 dmas = <&dma2 0 0 0x400 0x0>;
526 compatible = "st,stm32f4-adc";
527 #io-channel-cells = <1>;
529 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
530 interrupt-parent = <&adc>;
532 dmas = <&dma2 3 1 0x400 0x0>;
538 compatible = "st,stm32f4-adc";
539 #io-channel-cells = <1>;
541 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
542 interrupt-parent = <&adc>;
544 dmas = <&dma2 1 2 0x400 0x0>;
550 sdio: sdio@40012c00 {
551 compatible = "arm,pl180", "arm,primecell";
552 arm,primecell-periphid = <0x00880180>;
553 reg = <0x40012c00 0x400>;
554 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
555 clock-names = "apb_pclk";
557 max-frequency = <48000000>;
562 #address-cells = <1>;
564 compatible = "st,stm32f4-spi";
565 reg = <0x40013000 0x400>;
567 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
572 #address-cells = <1>;
574 compatible = "st,stm32f4-spi";
575 reg = <0x40013400 0x400>;
577 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
581 syscfg: system-config@40013800 {
582 compatible = "syscon";
583 reg = <0x40013800 0x400>;
586 exti: interrupt-controller@40013c00 {
587 compatible = "st,stm32-exti";
588 interrupt-controller;
589 #interrupt-cells = <2>;
590 reg = <0x40013C00 0x400>;
591 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
594 timers9: timers@40014000 {
595 #address-cells = <1>;
597 compatible = "st,stm32-timers";
598 reg = <0x40014000 0x400>;
599 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
604 compatible = "st,stm32-pwm";
609 compatible = "st,stm32-timer-trigger";
615 timers10: timers@40014400 {
616 #address-cells = <1>;
618 compatible = "st,stm32-timers";
619 reg = <0x40014400 0x400>;
620 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
625 compatible = "st,stm32-pwm";
630 timers11: timers@40014800 {
631 #address-cells = <1>;
633 compatible = "st,stm32-timers";
634 reg = <0x40014800 0x400>;
635 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
640 compatible = "st,stm32-pwm";
646 #address-cells = <1>;
648 compatible = "st,stm32f4-spi";
649 reg = <0x40015000 0x400>;
651 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
656 #address-cells = <1>;
658 compatible = "st,stm32f4-spi";
659 reg = <0x40015400 0x400>;
661 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
665 pwrcfg: power-config@40007000 {
666 compatible = "syscon";
667 reg = <0x40007000 0x400>;
670 ltdc: display-controller@40016800 {
671 compatible = "st,stm32-ltdc";
672 reg = <0x40016800 0x200>;
673 interrupts = <88>, <89>;
674 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
675 clocks = <&rcc 1 CLK_LCD>;
681 compatible = "st,stm32f4-crc";
682 reg = <0x40023000 0x400>;
683 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
690 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
691 reg = <0x40023800 0x400>;
692 clocks = <&clk_hse>, <&clk_i2s_ckin>;
693 st,syscfg = <&pwrcfg>;
694 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
695 assigned-clock-rates = <1000000>;
698 dma1: dma-controller@40026000 {
699 compatible = "st,stm32-dma";
700 reg = <0x40026000 0x400>;
709 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
713 dma2: dma-controller@40026400 {
714 compatible = "st,stm32-dma";
715 reg = <0x40026400 0x400>;
724 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
729 mac: ethernet@40028000 {
730 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
731 reg = <0x40028000 0x8000>;
732 reg-names = "stmmaceth";
734 interrupt-names = "macirq";
735 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
736 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
737 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
738 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
739 st,syscon = <&syscfg 0x4>;
745 usbotg_hs: usb@40040000 {
746 compatible = "snps,dwc2";
747 reg = <0x40040000 0x40000>;
749 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
754 usbotg_fs: usb@50000000 {
755 compatible = "st,stm32f4x9-fsotg";
756 reg = <0x50000000 0x40000>;
758 clocks = <&rcc 0 39>;
763 dcmi: dcmi@50050000 {
764 compatible = "st,stm32-dcmi";
765 reg = <0x50050000 0x400>;
767 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
768 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
769 clock-names = "mclk";
770 pinctrl-names = "default";
771 pinctrl-0 = <&dcmi_pins>;
772 dmas = <&dma2 1 1 0x414 0x3>;
778 compatible = "st,stm32-rng";
779 reg = <0x50060800 0x400>;
781 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
788 clocks = <&rcc 1 SYSTICK>;