2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include "skeleton.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun4i-a10-pll2.h>
49 #include <dt-bindings/dma/sun4i-a10.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&intc>;
65 compatible = "allwinner,simple-framebuffer",
67 allwinner,pipeline = "de_be0-lcd0-hdmi";
68 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
69 <&ahb_gates 43>, <&ahb_gates 44>,
75 compatible = "allwinner,simple-framebuffer",
77 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
78 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
79 <&ahb_gates 43>, <&ahb_gates 44>,
81 <&dram_gates 25>, <&dram_gates 26>;
86 compatible = "allwinner,simple-framebuffer",
88 allwinner,pipeline = "de_fe0-de_be0-lcd0";
89 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
90 <&ahb_gates 44>, <&ahb_gates 46>,
91 <&dram_gates 25>, <&dram_gates 26>;
96 compatible = "allwinner,simple-framebuffer",
98 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
99 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
100 <&ahb_gates 36>, <&ahb_gates 44>,
102 <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>;
108 #address-cells = <1>;
112 compatible = "arm,cortex-a8";
115 clock-latency = <244144>; /* 8 32k periods */
123 #cooling-cells = <2>;
124 cooling-min-level = <0>;
125 cooling-max-level = <3>;
132 polling-delay-passive = <250>;
133 polling-delay = <1000>;
134 thermal-sensors = <&rtp>;
138 trip = <&cpu_alert0>;
139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
144 cpu_alert0: cpu_alert0 {
146 temperature = <850000>;
153 temperature = <100000>;
162 reg = <0x40000000 0x80000000>;
166 #address-cells = <1>;
171 * This is a dummy clock, to be used as placeholder on
172 * other mux clocks when a specific parent clock is not
173 * yet implemented. It should be dropped when the driver
178 compatible = "fixed-clock";
179 clock-frequency = <0>;
182 osc24M: clk@01c20050 {
184 compatible = "allwinner,sun4i-a10-osc-clk";
185 reg = <0x01c20050 0x4>;
186 clock-frequency = <24000000>;
187 clock-output-names = "osc24M";
191 compatible = "fixed-factor-clock";
196 clock-output-names = "osc3M";
201 compatible = "fixed-clock";
202 clock-frequency = <32768>;
203 clock-output-names = "osc32k";
208 compatible = "allwinner,sun4i-a10-pll1-clk";
209 reg = <0x01c20000 0x4>;
211 clock-output-names = "pll1";
216 compatible = "allwinner,sun4i-a10-pll2-clk";
217 reg = <0x01c20008 0x8>;
219 clock-output-names = "pll2-1x", "pll2-2x",
220 "pll2-4x", "pll2-8x";
225 compatible = "allwinner,sun4i-a10-pll3-clk";
226 reg = <0x01c20010 0x4>;
228 clock-output-names = "pll3";
232 compatible = "fixed-factor-clock";
237 clock-output-names = "pll3-2x";
242 compatible = "allwinner,sun4i-a10-pll1-clk";
243 reg = <0x01c20018 0x4>;
245 clock-output-names = "pll4";
250 compatible = "allwinner,sun4i-a10-pll5-clk";
251 reg = <0x01c20020 0x4>;
253 clock-output-names = "pll5_ddr", "pll5_other";
258 compatible = "allwinner,sun4i-a10-pll6-clk";
259 reg = <0x01c20028 0x4>;
261 clock-output-names = "pll6_sata", "pll6_other", "pll6";
266 compatible = "allwinner,sun4i-a10-pll3-clk";
267 reg = <0x01c20030 0x4>;
269 clock-output-names = "pll7";
273 compatible = "fixed-factor-clock";
278 clock-output-names = "pll7-2x";
284 compatible = "allwinner,sun4i-a10-cpu-clk";
285 reg = <0x01c20054 0x4>;
286 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
287 clock-output-names = "cpu";
292 compatible = "allwinner,sun4i-a10-axi-clk";
293 reg = <0x01c20054 0x4>;
295 clock-output-names = "axi";
298 axi_gates: clk@01c2005c {
300 compatible = "allwinner,sun4i-a10-axi-gates-clk";
301 reg = <0x01c2005c 0x4>;
304 clock-output-names = "axi_dram";
309 compatible = "allwinner,sun4i-a10-ahb-clk";
310 reg = <0x01c20054 0x4>;
312 clock-output-names = "ahb";
315 ahb_gates: clk@01c20060 {
317 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
318 reg = <0x01c20060 0x8>;
320 clock-indices = <0>, <1>,
335 clock-output-names = "ahb_usb0", "ahb_ehci0",
336 "ahb_ohci0", "ahb_ehci1",
337 "ahb_ohci1", "ahb_ss", "ahb_dma",
338 "ahb_bist", "ahb_mmc0", "ahb_mmc1",
339 "ahb_mmc2", "ahb_mmc3", "ahb_ms",
340 "ahb_nand", "ahb_sdram", "ahb_ace",
341 "ahb_emac", "ahb_ts", "ahb_spi0",
342 "ahb_spi1", "ahb_spi2", "ahb_spi3",
343 "ahb_pata", "ahb_sata", "ahb_gps",
344 "ahb_ve", "ahb_tvd", "ahb_tve0",
345 "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
346 "ahb_csi0", "ahb_csi1", "ahb_hdmi",
347 "ahb_de_be0", "ahb_de_be1",
348 "ahb_de_fe0", "ahb_de_fe1",
349 "ahb_mp", "ahb_mali400";
352 apb0: apb0@01c20054 {
354 compatible = "allwinner,sun4i-a10-apb0-clk";
355 reg = <0x01c20054 0x4>;
357 clock-output-names = "apb0";
360 apb0_gates: clk@01c20068 {
362 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
363 reg = <0x01c20068 0x4>;
365 clock-indices = <0>, <1>,
369 clock-output-names = "apb0_codec", "apb0_spdif",
370 "apb0_ac97", "apb0_iis",
371 "apb0_pio", "apb0_ir0",
372 "apb0_ir1", "apb0_keypad";
377 compatible = "allwinner,sun4i-a10-apb1-clk";
378 reg = <0x01c20058 0x4>;
379 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
380 clock-output-names = "apb1";
383 apb1_gates: clk@01c2006c {
385 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
386 reg = <0x01c2006c 0x4>;
388 clock-indices = <0>, <1>,
396 clock-output-names = "apb1_i2c0", "apb1_i2c1",
397 "apb1_i2c2", "apb1_can",
398 "apb1_scr", "apb1_ps20",
399 "apb1_ps21", "apb1_uart0",
400 "apb1_uart1", "apb1_uart2",
401 "apb1_uart3", "apb1_uart4",
402 "apb1_uart5", "apb1_uart6",
406 nand_clk: clk@01c20080 {
408 compatible = "allwinner,sun4i-a10-mod0-clk";
409 reg = <0x01c20080 0x4>;
410 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
411 clock-output-names = "nand";
414 ms_clk: clk@01c20084 {
416 compatible = "allwinner,sun4i-a10-mod0-clk";
417 reg = <0x01c20084 0x4>;
418 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
419 clock-output-names = "ms";
422 mmc0_clk: clk@01c20088 {
424 compatible = "allwinner,sun4i-a10-mmc-clk";
425 reg = <0x01c20088 0x4>;
426 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
427 clock-output-names = "mmc0",
432 mmc1_clk: clk@01c2008c {
434 compatible = "allwinner,sun4i-a10-mmc-clk";
435 reg = <0x01c2008c 0x4>;
436 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
437 clock-output-names = "mmc1",
442 mmc2_clk: clk@01c20090 {
444 compatible = "allwinner,sun4i-a10-mmc-clk";
445 reg = <0x01c20090 0x4>;
446 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
447 clock-output-names = "mmc2",
452 mmc3_clk: clk@01c20094 {
454 compatible = "allwinner,sun4i-a10-mmc-clk";
455 reg = <0x01c20094 0x4>;
456 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
457 clock-output-names = "mmc3",
462 ts_clk: clk@01c20098 {
464 compatible = "allwinner,sun4i-a10-mod0-clk";
465 reg = <0x01c20098 0x4>;
466 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
467 clock-output-names = "ts";
470 ss_clk: clk@01c2009c {
472 compatible = "allwinner,sun4i-a10-mod0-clk";
473 reg = <0x01c2009c 0x4>;
474 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
475 clock-output-names = "ss";
478 spi0_clk: clk@01c200a0 {
480 compatible = "allwinner,sun4i-a10-mod0-clk";
481 reg = <0x01c200a0 0x4>;
482 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
483 clock-output-names = "spi0";
486 spi1_clk: clk@01c200a4 {
488 compatible = "allwinner,sun4i-a10-mod0-clk";
489 reg = <0x01c200a4 0x4>;
490 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
491 clock-output-names = "spi1";
494 spi2_clk: clk@01c200a8 {
496 compatible = "allwinner,sun4i-a10-mod0-clk";
497 reg = <0x01c200a8 0x4>;
498 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
499 clock-output-names = "spi2";
502 pata_clk: clk@01c200ac {
504 compatible = "allwinner,sun4i-a10-mod0-clk";
505 reg = <0x01c200ac 0x4>;
506 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
507 clock-output-names = "pata";
510 ir0_clk: clk@01c200b0 {
512 compatible = "allwinner,sun4i-a10-mod0-clk";
513 reg = <0x01c200b0 0x4>;
514 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
515 clock-output-names = "ir0";
518 ir1_clk: clk@01c200b4 {
520 compatible = "allwinner,sun4i-a10-mod0-clk";
521 reg = <0x01c200b4 0x4>;
522 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
523 clock-output-names = "ir1";
526 spdif_clk: clk@01c200c0 {
528 compatible = "allwinner,sun4i-a10-mod1-clk";
529 reg = <0x01c200c0 0x4>;
530 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
531 <&pll2 SUN4I_A10_PLL2_4X>,
532 <&pll2 SUN4I_A10_PLL2_2X>,
533 <&pll2 SUN4I_A10_PLL2_1X>;
534 clock-output-names = "spdif";
537 usb_clk: clk@01c200cc {
540 compatible = "allwinner,sun4i-a10-usb-clk";
541 reg = <0x01c200cc 0x4>;
543 clock-output-names = "usb_ohci0", "usb_ohci1",
547 spi3_clk: clk@01c200d4 {
549 compatible = "allwinner,sun4i-a10-mod0-clk";
550 reg = <0x01c200d4 0x4>;
551 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
552 clock-output-names = "spi3";
555 dram_gates: clk@01c20100 {
557 compatible = "allwinner,sun4i-a10-dram-gates-clk";
558 reg = <0x01c20100 0x4>;
569 clock-output-names = "dram_ve",
570 "dram_csi0", "dram_csi1",
573 "dram_tve0", "dram_tve1",
575 "dram_de_fe1", "dram_de_fe0",
576 "dram_de_be0", "dram_de_be1",
577 "dram_de_mp", "dram_ace";
580 ve_clk: clk@01c2013c {
583 compatible = "allwinner,sun4i-a10-ve-clk";
584 reg = <0x01c2013c 0x4>;
586 clock-output-names = "ve";
589 codec_clk: clk@01c20140 {
591 compatible = "allwinner,sun4i-a10-codec-clk";
592 reg = <0x01c20140 0x4>;
593 clocks = <&pll2 SUN4I_A10_PLL2_1X>;
594 clock-output-names = "codec";
599 compatible = "simple-bus";
600 #address-cells = <1>;
604 sram-controller@01c00000 {
605 compatible = "allwinner,sun4i-a10-sram-controller";
606 reg = <0x01c00000 0x30>;
607 #address-cells = <1>;
611 sram_a: sram@00000000 {
612 compatible = "mmio-sram";
613 reg = <0x00000000 0xc000>;
614 #address-cells = <1>;
616 ranges = <0 0x00000000 0xc000>;
618 emac_sram: sram-section@8000 {
619 compatible = "allwinner,sun4i-a10-sram-a3-a4";
620 reg = <0x8000 0x4000>;
625 sram_d: sram@00010000 {
626 compatible = "mmio-sram";
627 reg = <0x00010000 0x1000>;
628 #address-cells = <1>;
630 ranges = <0 0x00010000 0x1000>;
632 otg_sram: sram-section@0000 {
633 compatible = "allwinner,sun4i-a10-sram-d";
634 reg = <0x0000 0x1000>;
640 dma: dma-controller@01c02000 {
641 compatible = "allwinner,sun4i-a10-dma";
642 reg = <0x01c02000 0x1000>;
644 clocks = <&ahb_gates 6>;
649 compatible = "allwinner,sun4i-a10-spi";
650 reg = <0x01c05000 0x1000>;
652 clocks = <&ahb_gates 20>, <&spi0_clk>;
653 clock-names = "ahb", "mod";
654 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
655 <&dma SUN4I_DMA_DEDICATED 26>;
656 dma-names = "rx", "tx";
658 #address-cells = <1>;
663 compatible = "allwinner,sun4i-a10-spi";
664 reg = <0x01c06000 0x1000>;
666 clocks = <&ahb_gates 21>, <&spi1_clk>;
667 clock-names = "ahb", "mod";
668 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
669 <&dma SUN4I_DMA_DEDICATED 8>;
670 dma-names = "rx", "tx";
672 #address-cells = <1>;
676 emac: ethernet@01c0b000 {
677 compatible = "allwinner,sun4i-a10-emac";
678 reg = <0x01c0b000 0x1000>;
680 clocks = <&ahb_gates 17>;
681 allwinner,sram = <&emac_sram 1>;
685 mdio: mdio@01c0b080 {
686 compatible = "allwinner,sun4i-a10-mdio";
687 reg = <0x01c0b080 0x14>;
689 #address-cells = <1>;
694 compatible = "allwinner,sun4i-a10-mmc";
695 reg = <0x01c0f000 0x1000>;
696 clocks = <&ahb_gates 8>,
706 #address-cells = <1>;
711 compatible = "allwinner,sun4i-a10-mmc";
712 reg = <0x01c10000 0x1000>;
713 clocks = <&ahb_gates 9>,
723 #address-cells = <1>;
728 compatible = "allwinner,sun4i-a10-mmc";
729 reg = <0x01c11000 0x1000>;
730 clocks = <&ahb_gates 10>,
740 #address-cells = <1>;
745 compatible = "allwinner,sun4i-a10-mmc";
746 reg = <0x01c12000 0x1000>;
747 clocks = <&ahb_gates 11>,
757 #address-cells = <1>;
761 usb_otg: usb@01c13000 {
762 compatible = "allwinner,sun4i-a10-musb";
763 reg = <0x01c13000 0x0400>;
764 clocks = <&ahb_gates 0>;
766 interrupt-names = "mc";
769 extcon = <&usbphy 0>;
770 allwinner,sram = <&otg_sram 1>;
774 usbphy: phy@01c13400 {
776 compatible = "allwinner,sun4i-a10-usb-phy";
777 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
778 reg-names = "phy_ctrl", "pmu1", "pmu2";
779 clocks = <&usb_clk 8>;
780 clock-names = "usb_phy";
781 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
782 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
786 ehci0: usb@01c14000 {
787 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
788 reg = <0x01c14000 0x100>;
790 clocks = <&ahb_gates 1>;
796 ohci0: usb@01c14400 {
797 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
798 reg = <0x01c14400 0x100>;
800 clocks = <&usb_clk 6>, <&ahb_gates 2>;
806 crypto: crypto-engine@01c15000 {
807 compatible = "allwinner,sun4i-a10-crypto";
808 reg = <0x01c15000 0x1000>;
810 clocks = <&ahb_gates 5>, <&ss_clk>;
811 clock-names = "ahb", "mod";
815 compatible = "allwinner,sun4i-a10-spi";
816 reg = <0x01c17000 0x1000>;
818 clocks = <&ahb_gates 22>, <&spi2_clk>;
819 clock-names = "ahb", "mod";
820 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
821 <&dma SUN4I_DMA_DEDICATED 28>;
822 dma-names = "rx", "tx";
824 #address-cells = <1>;
828 ahci: sata@01c18000 {
829 compatible = "allwinner,sun4i-a10-ahci";
830 reg = <0x01c18000 0x1000>;
832 clocks = <&pll6 0>, <&ahb_gates 25>;
836 ehci1: usb@01c1c000 {
837 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
838 reg = <0x01c1c000 0x100>;
840 clocks = <&ahb_gates 3>;
846 ohci1: usb@01c1c400 {
847 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
848 reg = <0x01c1c400 0x100>;
850 clocks = <&usb_clk 7>, <&ahb_gates 4>;
857 compatible = "allwinner,sun4i-a10-spi";
858 reg = <0x01c1f000 0x1000>;
860 clocks = <&ahb_gates 23>, <&spi3_clk>;
861 clock-names = "ahb", "mod";
862 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
863 <&dma SUN4I_DMA_DEDICATED 30>;
864 dma-names = "rx", "tx";
866 #address-cells = <1>;
870 intc: interrupt-controller@01c20400 {
871 compatible = "allwinner,sun4i-a10-ic";
872 reg = <0x01c20400 0x400>;
873 interrupt-controller;
874 #interrupt-cells = <1>;
877 pio: pinctrl@01c20800 {
878 compatible = "allwinner,sun4i-a10-pinctrl";
879 reg = <0x01c20800 0x400>;
881 clocks = <&apb0_gates 5>;
883 interrupt-controller;
884 #interrupt-cells = <3>;
887 pwm0_pins_a: pwm0@0 {
888 allwinner,pins = "PB2";
889 allwinner,function = "pwm";
890 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
891 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
894 pwm1_pins_a: pwm1@0 {
895 allwinner,pins = "PI3";
896 allwinner,function = "pwm";
897 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
898 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
901 uart0_pins_a: uart0@0 {
902 allwinner,pins = "PB22", "PB23";
903 allwinner,function = "uart0";
904 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
905 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
908 uart0_pins_b: uart0@1 {
909 allwinner,pins = "PF2", "PF4";
910 allwinner,function = "uart0";
911 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
912 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
915 uart1_pins_a: uart1@0 {
916 allwinner,pins = "PA10", "PA11";
917 allwinner,function = "uart1";
918 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
919 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
922 i2c0_pins_a: i2c0@0 {
923 allwinner,pins = "PB0", "PB1";
924 allwinner,function = "i2c0";
925 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
926 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
929 i2c1_pins_a: i2c1@0 {
930 allwinner,pins = "PB18", "PB19";
931 allwinner,function = "i2c1";
932 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
933 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
936 i2c2_pins_a: i2c2@0 {
937 allwinner,pins = "PB20", "PB21";
938 allwinner,function = "i2c2";
939 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
940 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
943 emac_pins_a: emac0@0 {
944 allwinner,pins = "PA0", "PA1", "PA2",
945 "PA3", "PA4", "PA5", "PA6",
946 "PA7", "PA8", "PA9", "PA10",
947 "PA11", "PA12", "PA13", "PA14",
949 allwinner,function = "emac";
950 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
951 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
954 mmc0_pins_a: mmc0@0 {
955 allwinner,pins = "PF0", "PF1", "PF2",
957 allwinner,function = "mmc0";
958 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
959 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
962 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
963 allwinner,pins = "PH1";
964 allwinner,function = "gpio_in";
965 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
966 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
969 ir0_rx_pins_a: ir0@0 {
970 allwinner,pins = "PB4";
971 allwinner,function = "ir0";
972 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
973 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
976 ir0_tx_pins_a: ir0@1 {
977 allwinner,pins = "PB3";
978 allwinner,function = "ir0";
979 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
980 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
983 ir1_rx_pins_a: ir1@0 {
984 allwinner,pins = "PB23";
985 allwinner,function = "ir1";
986 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
987 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
990 ir1_tx_pins_a: ir1@1 {
991 allwinner,pins = "PB22";
992 allwinner,function = "ir1";
993 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
994 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
997 spi0_pins_a: spi0@0 {
998 allwinner,pins = "PI11", "PI12", "PI13";
999 allwinner,function = "spi0";
1000 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1001 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1004 spi0_cs0_pins_a: spi0_cs0@0 {
1005 allwinner,pins = "PI10";
1006 allwinner,function = "spi0";
1007 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1008 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1011 spi1_pins_a: spi1@0 {
1012 allwinner,pins = "PI17", "PI18", "PI19";
1013 allwinner,function = "spi1";
1014 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1015 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1018 spi1_cs0_pins_a: spi1_cs0@0 {
1019 allwinner,pins = "PI16";
1020 allwinner,function = "spi1";
1021 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1022 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1025 spi2_pins_a: spi2@0 {
1026 allwinner,pins = "PC20", "PC21", "PC22";
1027 allwinner,function = "spi2";
1028 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1029 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1032 spi2_pins_b: spi2@1 {
1033 allwinner,pins = "PB15", "PB16", "PB17";
1034 allwinner,function = "spi2";
1035 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1036 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1039 spi2_cs0_pins_a: spi2_cs0@0 {
1040 allwinner,pins = "PC19";
1041 allwinner,function = "spi2";
1042 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1043 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1046 spi2_cs0_pins_b: spi2_cs0@1 {
1047 allwinner,pins = "PB14";
1048 allwinner,function = "spi2";
1049 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1050 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1053 ps20_pins_a: ps20@0 {
1054 allwinner,pins = "PI20", "PI21";
1055 allwinner,function = "ps2";
1056 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1057 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1060 ps21_pins_a: ps21@0 {
1061 allwinner,pins = "PH12", "PH13";
1062 allwinner,function = "ps2";
1063 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1064 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1067 spdif_tx_pins_a: spdif@0 {
1068 allwinner,pins = "PB13";
1069 allwinner,function = "spdif";
1070 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1071 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1076 compatible = "allwinner,sun4i-a10-timer";
1077 reg = <0x01c20c00 0x90>;
1082 wdt: watchdog@01c20c90 {
1083 compatible = "allwinner,sun4i-a10-wdt";
1084 reg = <0x01c20c90 0x10>;
1088 compatible = "allwinner,sun4i-a10-rtc";
1089 reg = <0x01c20d00 0x20>;
1094 compatible = "allwinner,sun4i-a10-pwm";
1095 reg = <0x01c20e00 0xc>;
1098 status = "disabled";
1101 spdif: spdif@01c21000 {
1102 #sound-dai-cells = <0>;
1103 compatible = "allwinner,sun4i-a10-spdif";
1104 reg = <0x01c21000 0x400>;
1106 clocks = <&apb0_gates 1>, <&spdif_clk>;
1107 clock-names = "apb", "spdif";
1108 dmas = <&dma SUN4I_DMA_NORMAL 2>,
1109 <&dma SUN4I_DMA_NORMAL 2>;
1110 dma-names = "rx", "tx";
1111 status = "disabled";
1115 compatible = "allwinner,sun4i-a10-ir";
1116 clocks = <&apb0_gates 6>, <&ir0_clk>;
1117 clock-names = "apb", "ir";
1119 reg = <0x01c21800 0x40>;
1120 status = "disabled";
1124 compatible = "allwinner,sun4i-a10-ir";
1125 clocks = <&apb0_gates 7>, <&ir1_clk>;
1126 clock-names = "apb", "ir";
1128 reg = <0x01c21c00 0x40>;
1129 status = "disabled";
1132 lradc: lradc@01c22800 {
1133 compatible = "allwinner,sun4i-a10-lradc-keys";
1134 reg = <0x01c22800 0x100>;
1136 status = "disabled";
1139 codec: codec@01c22c00 {
1140 #sound-dai-cells = <0>;
1141 compatible = "allwinner,sun4i-a10-codec";
1142 reg = <0x01c22c00 0x40>;
1144 clocks = <&apb0_gates 0>, <&codec_clk>;
1145 clock-names = "apb", "codec";
1146 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1147 <&dma SUN4I_DMA_NORMAL 19>;
1148 dma-names = "rx", "tx";
1149 status = "disabled";
1152 sid: eeprom@01c23800 {
1153 compatible = "allwinner,sun4i-a10-sid";
1154 reg = <0x01c23800 0x10>;
1158 compatible = "allwinner,sun4i-a10-ts";
1159 reg = <0x01c25000 0x100>;
1161 #thermal-sensor-cells = <0>;
1164 uart0: serial@01c28000 {
1165 compatible = "snps,dw-apb-uart";
1166 reg = <0x01c28000 0x400>;
1170 clocks = <&apb1_gates 16>;
1171 status = "disabled";
1174 uart1: serial@01c28400 {
1175 compatible = "snps,dw-apb-uart";
1176 reg = <0x01c28400 0x400>;
1180 clocks = <&apb1_gates 17>;
1181 status = "disabled";
1184 uart2: serial@01c28800 {
1185 compatible = "snps,dw-apb-uart";
1186 reg = <0x01c28800 0x400>;
1190 clocks = <&apb1_gates 18>;
1191 status = "disabled";
1194 uart3: serial@01c28c00 {
1195 compatible = "snps,dw-apb-uart";
1196 reg = <0x01c28c00 0x400>;
1200 clocks = <&apb1_gates 19>;
1201 status = "disabled";
1204 uart4: serial@01c29000 {
1205 compatible = "snps,dw-apb-uart";
1206 reg = <0x01c29000 0x400>;
1210 clocks = <&apb1_gates 20>;
1211 status = "disabled";
1214 uart5: serial@01c29400 {
1215 compatible = "snps,dw-apb-uart";
1216 reg = <0x01c29400 0x400>;
1220 clocks = <&apb1_gates 21>;
1221 status = "disabled";
1224 uart6: serial@01c29800 {
1225 compatible = "snps,dw-apb-uart";
1226 reg = <0x01c29800 0x400>;
1230 clocks = <&apb1_gates 22>;
1231 status = "disabled";
1234 uart7: serial@01c29c00 {
1235 compatible = "snps,dw-apb-uart";
1236 reg = <0x01c29c00 0x400>;
1240 clocks = <&apb1_gates 23>;
1241 status = "disabled";
1244 i2c0: i2c@01c2ac00 {
1245 compatible = "allwinner,sun4i-a10-i2c";
1246 reg = <0x01c2ac00 0x400>;
1248 clocks = <&apb1_gates 0>;
1249 status = "disabled";
1250 #address-cells = <1>;
1254 i2c1: i2c@01c2b000 {
1255 compatible = "allwinner,sun4i-a10-i2c";
1256 reg = <0x01c2b000 0x400>;
1258 clocks = <&apb1_gates 1>;
1259 status = "disabled";
1260 #address-cells = <1>;
1264 i2c2: i2c@01c2b400 {
1265 compatible = "allwinner,sun4i-a10-i2c";
1266 reg = <0x01c2b400 0x400>;
1268 clocks = <&apb1_gates 2>;
1269 status = "disabled";
1270 #address-cells = <1>;
1274 ps20: ps2@01c2a000 {
1275 compatible = "allwinner,sun4i-a10-ps2";
1276 reg = <0x01c2a000 0x400>;
1278 clocks = <&apb1_gates 6>;
1279 status = "disabled";
1282 ps21: ps2@01c2a400 {
1283 compatible = "allwinner,sun4i-a10-ps2";
1284 reg = <0x01c2a400 0x400>;
1286 clocks = <&apb1_gates 7>;
1287 status = "disabled";