2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
48 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
51 interrupt-parent = <&gic>;
60 simplefb_lcd: framebuffer-lcd0 {
61 compatible = "allwinner,simple-framebuffer",
63 allwinner,pipeline = "de_be0-lcd0";
64 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
65 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
66 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
72 /* compatible gets set in SoC specific dtsi file */
73 allwinner,pipelines = <&fe0>;
78 compatible = "arm,armv7-timer";
79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
82 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
83 clock-frequency = <24000000>;
84 arm,cpu-registers-not-fw-configured;
88 enable-method = "allwinner,sun8i-a23";
93 compatible = "arm,cortex-a7";
99 compatible = "arm,cortex-a7";
106 #address-cells = <1>;
112 compatible = "fixed-clock";
113 clock-frequency = <24000000>;
114 clock-accuracy = <50000>;
115 clock-output-names = "osc24M";
118 ext_osc32k: ext_osc32k_clk {
120 compatible = "fixed-clock";
121 clock-frequency = <32768>;
122 clock-accuracy = <50000>;
123 clock-output-names = "ext-osc32k";
128 compatible = "simple-bus";
129 #address-cells = <1>;
133 system-control@1c00000 {
134 compatible = "allwinner,sun8i-a23-system-control";
135 reg = <0x01c00000 0x30>;
136 #address-cells = <1>;
140 sram_c: sram@1d00000 {
141 compatible = "mmio-sram";
142 reg = <0x01d00000 0x80000>;
143 #address-cells = <1>;
145 ranges = <0 0x01d00000 0x80000>;
147 ve_sram: sram-section@0 {
148 compatible = "allwinner,sun8i-a23-sram-c1",
149 "allwinner,sun4i-a10-sram-c1";
150 reg = <0x000000 0x80000>;
155 dma: dma-controller@1c02000 {
156 compatible = "allwinner,sun8i-a23-dma";
157 reg = <0x01c02000 0x1000>;
158 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&ccu CLK_BUS_DMA>;
160 resets = <&ccu RST_BUS_DMA>;
164 nfc: nand-controller@1c03000 {
165 compatible = "allwinner,sun8i-a23-nand-controller";
166 reg = <0x01c03000 0x1000>;
167 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
169 clock-names = "ahb", "mod";
170 resets = <&ccu RST_BUS_NAND>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
177 #address-cells = <1>;
181 tcon0: lcd-controller@1c0c000 {
182 /* compatible gets set in SoC specific dtsi file */
183 reg = <0x01c0c000 0x1000>;
184 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&ccu CLK_BUS_LCD>,
189 clock-output-names = "tcon-pixel-clock";
191 resets = <&ccu RST_BUS_LCD>;
196 #address-cells = <1>;
202 tcon0_in_drc0: endpoint {
203 remote-endpoint = <&drc0_out_tcon0>;
214 compatible = "allwinner,sun7i-a20-mmc";
215 reg = <0x01c0f000 0x1000>;
216 clocks = <&ccu CLK_BUS_MMC0>,
218 <&ccu CLK_MMC0_OUTPUT>,
219 <&ccu CLK_MMC0_SAMPLE>;
224 resets = <&ccu RST_BUS_MMC0>;
226 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
227 pinctrl-names = "default";
228 pinctrl-0 = <&mmc0_pins>;
230 #address-cells = <1>;
235 compatible = "allwinner,sun7i-a20-mmc";
236 reg = <0x01c10000 0x1000>;
237 clocks = <&ccu CLK_BUS_MMC1>,
239 <&ccu CLK_MMC1_OUTPUT>,
240 <&ccu CLK_MMC1_SAMPLE>;
245 resets = <&ccu RST_BUS_MMC1>;
247 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
249 #address-cells = <1>;
254 compatible = "allwinner,sun7i-a20-mmc";
255 reg = <0x01c11000 0x1000>;
256 clocks = <&ccu CLK_BUS_MMC2>,
258 <&ccu CLK_MMC2_OUTPUT>,
259 <&ccu CLK_MMC2_SAMPLE>;
264 resets = <&ccu RST_BUS_MMC2>;
266 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
268 #address-cells = <1>;
272 usb_otg: usb@1c19000 {
273 /* compatible gets set in SoC specific dtsi file */
274 reg = <0x01c19000 0x0400>;
275 clocks = <&ccu CLK_BUS_OTG>;
276 resets = <&ccu RST_BUS_OTG>;
277 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
278 interrupt-names = "mc";
281 extcon = <&usbphy 0>;
286 usbphy: phy@1c19400 {
288 * compatible and address regions get set in
289 * SoC specific dtsi file
291 clocks = <&ccu CLK_USB_PHY0>,
293 clock-names = "usb0_phy",
295 resets = <&ccu RST_USB_PHY0>,
297 reset-names = "usb0_reset",
304 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
305 reg = <0x01c1a000 0x100>;
306 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&ccu CLK_BUS_EHCI>;
308 resets = <&ccu RST_BUS_EHCI>;
315 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
316 reg = <0x01c1a400 0x100>;
317 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
319 resets = <&ccu RST_BUS_OHCI>;
326 reg = <0x01c20000 0x400>;
327 clocks = <&osc24M>, <&rtc 0>;
328 clock-names = "hosc", "losc";
333 pio: pinctrl@1c20800 {
334 /* compatible gets set in SoC specific dtsi file */
335 reg = <0x01c20800 0x400>;
336 /* interrupts get set in SoC specific dtsi file */
337 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
338 clock-names = "apb", "hosc", "losc";
340 interrupt-controller;
341 #interrupt-cells = <3>;
344 i2c0_pins: i2c0-pins {
349 i2c1_pins: i2c1-pins {
354 i2c2_pins: i2c2-pins {
355 pins = "PE12", "PE13";
359 lcd_rgb666_pins: lcd-rgb666-pins {
360 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
361 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
362 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
363 "PD24", "PD25", "PD26", "PD27";
367 mmc0_pins: mmc0-pins {
368 pins = "PF0", "PF1", "PF2",
371 drive-strength = <30>;
375 mmc1_pg_pins: mmc1-pg-pins {
376 pins = "PG0", "PG1", "PG2",
379 drive-strength = <30>;
383 mmc2_8bit_pins: mmc2-8bit-pins {
384 pins = "PC5", "PC6", "PC8",
385 "PC9", "PC10", "PC11",
386 "PC12", "PC13", "PC14",
389 drive-strength = <30>;
393 nand_pins: nand-pins {
394 pins = "PC0", "PC1", "PC2", "PC5",
395 "PC8", "PC9", "PC10", "PC11",
396 "PC12", "PC13", "PC14", "PC15";
400 nand_cs0_pin: nand-cs0-pin {
406 nand_cs1_pin: nand-cs1-pin {
412 nand_rb0_pin: nand-rb0-pin {
418 nand_rb1_pin: nand-rb1-pin {
429 uart0_pf_pins: uart0-pf-pins {
434 uart1_pg_pins: uart1-pg-pins {
439 uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
446 compatible = "allwinner,sun4i-a10-timer";
447 reg = <0x01c20c00 0xa0>;
448 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
453 wdt0: watchdog@1c20ca0 {
454 compatible = "allwinner,sun6i-a31-wdt";
455 reg = <0x01c20ca0 0x20>;
456 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
460 compatible = "allwinner,sun7i-a20-pwm";
461 reg = <0x01c21400 0xc>;
467 lradc: lradc@1c22800 {
468 compatible = "allwinner,sun4i-a10-lradc-keys";
469 reg = <0x01c22800 0x100>;
470 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
474 uart0: serial@1c28000 {
475 compatible = "snps,dw-apb-uart";
476 reg = <0x01c28000 0x400>;
477 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&ccu CLK_BUS_UART0>;
481 resets = <&ccu RST_BUS_UART0>;
482 dmas = <&dma 6>, <&dma 6>;
483 dma-names = "rx", "tx";
487 uart1: serial@1c28400 {
488 compatible = "snps,dw-apb-uart";
489 reg = <0x01c28400 0x400>;
490 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&ccu CLK_BUS_UART1>;
494 resets = <&ccu RST_BUS_UART1>;
495 dmas = <&dma 7>, <&dma 7>;
496 dma-names = "rx", "tx";
500 uart2: serial@1c28800 {
501 compatible = "snps,dw-apb-uart";
502 reg = <0x01c28800 0x400>;
503 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&ccu CLK_BUS_UART2>;
507 resets = <&ccu RST_BUS_UART2>;
508 dmas = <&dma 8>, <&dma 8>;
509 dma-names = "rx", "tx";
513 uart3: serial@1c28c00 {
514 compatible = "snps,dw-apb-uart";
515 reg = <0x01c28c00 0x400>;
516 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&ccu CLK_BUS_UART3>;
520 resets = <&ccu RST_BUS_UART3>;
521 dmas = <&dma 9>, <&dma 9>;
522 dma-names = "rx", "tx";
526 uart4: serial@1c29000 {
527 compatible = "snps,dw-apb-uart";
528 reg = <0x01c29000 0x400>;
529 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&ccu CLK_BUS_UART4>;
533 resets = <&ccu RST_BUS_UART4>;
534 dmas = <&dma 10>, <&dma 10>;
535 dma-names = "rx", "tx";
540 compatible = "allwinner,sun6i-a31-i2c";
541 reg = <0x01c2ac00 0x400>;
542 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&ccu CLK_BUS_I2C0>;
544 resets = <&ccu RST_BUS_I2C0>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&i2c0_pins>;
548 #address-cells = <1>;
553 compatible = "allwinner,sun6i-a31-i2c";
554 reg = <0x01c2b000 0x400>;
555 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&ccu CLK_BUS_I2C1>;
557 resets = <&ccu RST_BUS_I2C1>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&i2c1_pins>;
561 #address-cells = <1>;
566 compatible = "allwinner,sun6i-a31-i2c";
567 reg = <0x01c2b400 0x400>;
568 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&ccu CLK_BUS_I2C2>;
570 resets = <&ccu RST_BUS_I2C2>;
571 pinctrl-names = "default";
572 pinctrl-0 = <&i2c2_pins>;
574 #address-cells = <1>;
579 compatible = "allwinner,sun8i-a23-mali",
580 "allwinner,sun7i-a20-mali", "arm,mali-400";
581 reg = <0x01c40000 0x10000>;
582 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
589 interrupt-names = "gp",
596 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
597 clock-names = "bus", "core";
598 resets = <&ccu RST_BUS_GPU>;
599 #cooling-cells = <2>;
601 assigned-clocks = <&ccu CLK_GPU>;
602 assigned-clock-rates = <384000000>;
605 gic: interrupt-controller@1c81000 {
606 compatible = "arm,gic-400";
607 reg = <0x01c81000 0x1000>,
611 interrupt-controller;
612 #interrupt-cells = <3>;
613 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
616 fe0: display-frontend@1e00000 {
617 /* compatible gets set in SoC specific dtsi file */
618 reg = <0x01e00000 0x20000>;
619 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
621 <&ccu CLK_DRAM_DE_FE>;
622 clock-names = "ahb", "mod",
624 resets = <&ccu RST_BUS_DE_FE>;
627 #address-cells = <1>;
633 fe0_out_be0: endpoint {
634 remote-endpoint = <&be0_in_fe0>;
640 be0: display-backend@1e60000 {
641 /* compatible gets set in SoC specific dtsi file */
642 reg = <0x01e60000 0x10000>;
643 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
645 <&ccu CLK_DRAM_DE_BE>;
646 clock-names = "ahb", "mod",
648 resets = <&ccu RST_BUS_DE_BE>;
651 #address-cells = <1>;
657 be0_in_fe0: endpoint {
658 remote-endpoint = <&fe0_out_be0>;
665 be0_out_drc0: endpoint {
666 remote-endpoint = <&drc0_in_be0>;
673 /* compatible gets set in SoC specific dtsi file */
674 reg = <0x01e70000 0x10000>;
675 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
678 clock-names = "ahb", "mod", "ram";
679 resets = <&ccu RST_BUS_DRC>;
681 assigned-clocks = <&ccu CLK_DRC>;
682 assigned-clock-rates = <300000000>;
685 #address-cells = <1>;
691 drc0_in_be0: endpoint {
692 remote-endpoint = <&be0_out_drc0>;
699 drc0_out_tcon0: endpoint {
700 remote-endpoint = <&tcon0_in_drc0>;
707 compatible = "allwinner,sun8i-a23-rtc";
708 reg = <0x01f00000 0x400>;
709 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
711 clock-output-names = "osc32k", "osc32k-out";
712 clocks = <&ext_osc32k>;
716 nmi_intc: interrupt-controller@1f00c00 {
717 compatible = "allwinner,sun6i-a31-r-intc";
718 interrupt-controller;
719 #interrupt-cells = <2>;
720 reg = <0x01f00c00 0x400>;
721 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
725 compatible = "allwinner,sun8i-a23-prcm";
726 reg = <0x01f01400 0x200>;
729 compatible = "fixed-factor-clock";
734 clock-output-names = "ar100";
738 compatible = "fixed-factor-clock";
743 clock-output-names = "ahb0";
747 compatible = "allwinner,sun8i-a23-apb0-clk";
750 clock-output-names = "apb0";
753 apb0_gates: apb0_gates_clk {
754 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
757 clock-output-names = "apb0_pio", "apb0_timer",
758 "apb0_rsb", "apb0_uart",
763 compatible = "allwinner,sun6i-a31-clock-reset";
767 codec_analog: codec-analog {
768 compatible = "allwinner,sun8i-a23-codec-analog";
773 compatible = "allwinner,sun8i-a23-cpuconfig";
774 reg = <0x01f01c00 0x300>;
777 r_uart: serial@1f02800 {
778 compatible = "snps,dw-apb-uart";
779 reg = <0x01f02800 0x400>;
780 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
783 clocks = <&apb0_gates 4>;
784 resets = <&apb0_rst 4>;
789 compatible = "allwinner,sun8i-a23-i2c",
790 "allwinner,sun6i-a31-i2c";
791 reg = <0x01f02400 0x400>;
792 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
793 pinctrl-names = "default";
794 pinctrl-0 = <&r_i2c_pins>;
795 clocks = <&apb0_gates 6>;
796 resets = <&apb0_rst 6>;
798 #address-cells = <1>;
802 r_pio: pinctrl@1f02c00 {
803 compatible = "allwinner,sun8i-a23-r-pinctrl";
804 reg = <0x01f02c00 0x400>;
805 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
807 clock-names = "apb", "hosc", "losc";
808 resets = <&apb0_rst 0>;
810 interrupt-controller;
811 #interrupt-cells = <3>;
814 r_i2c_pins: r-i2c-pins {
820 r_rsb_pins: r-rsb-pins {
823 drive-strength = <20>;
827 r_uart_pins_a: r-uart-pins {
834 compatible = "allwinner,sun8i-a23-rsb";
835 reg = <0x01f03400 0x400>;
836 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&apb0_gates 3>;
838 clock-frequency = <3000000>;
839 resets = <&apb0_rst 3>;
840 pinctrl-names = "default";
841 pinctrl-0 = <&r_rsb_pins>;
843 #address-cells = <1>;