arch/arm/boot/dts/sun8i-r40.dtsi

   1 /*
   2  * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
   3  * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/interrupt-controller/arm-gic.h>
  45 #include <dt-bindings/clock/sun8i-de2.h>
  46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
  47 #include <dt-bindings/reset/sun8i-r40-ccu.h>
  48 #include <dt-bindings/reset/sun8i-de2.h>
  49
  50 / {
  51         #address-cells = <1>;
  52         #size-cells = <1>;
  53         interrupt-parent = <&gic>;
  54
  55         clocks {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 ranges;
  59
  60                 osc24M: osc24M {
  61                         #clock-cells = <0>;
  62                         compatible = "fixed-clock";
  63                         clock-frequency = <24000000>;
  64                         clock-accuracy = <50000>;
  65                         clock-output-names = "osc24M";
  66                 };
  67
  68                 osc32k: osc32k {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <32768>;
  72                         clock-accuracy = <20000>;
  73                         clock-output-names = "ext-osc32k";
  74                 };
  75         };
  76
  77         cpus {
  78                 #address-cells = <1>;
  79                 #size-cells = <0>;
  80
  81                 cpu@0 {
  82                         compatible = "arm,cortex-a7";
  83                         device_type = "cpu";
  84                         reg = <0>;
  85                 };
  86
  87                 cpu@1 {
  88                         compatible = "arm,cortex-a7";
  89                         device_type = "cpu";
  90                         reg = <1>;
  91                 };
  92
  93                 cpu@2 {
  94                         compatible = "arm,cortex-a7";
  95                         device_type = "cpu";
  96                         reg = <2>;
  97                 };
  98
  99                 cpu@3 {
 100                         compatible = "arm,cortex-a7";
 101                         device_type = "cpu";
 102                         reg = <3>;
 103                 };
 104         };
 105
 106         de: display-engine {
 107                 compatible = "allwinner,sun8i-r40-display-engine";
 108                 allwinner,pipelines = <&mixer0>, <&mixer1>;
 109                 status = "disabled";
 110         };
 111
 112         soc {
 113                 compatible = "simple-bus";
 114                 #address-cells = <1>;
 115                 #size-cells = <1>;
 116                 ranges;
 117
 118                 display_clocks: clock@1000000 {
 119                         compatible = "allwinner,sun8i-r40-de2-clk",
 120                                      "allwinner,sun8i-h3-de2-clk";
 121                         reg = <0x01000000 0x100000>;
 122                         clocks = <&ccu CLK_BUS_DE>,
 123                                  <&ccu CLK_DE>;
 124                         clock-names = "bus",
 125                                       "mod";
 126                         resets = <&ccu RST_BUS_DE>;
 127                         #clock-cells = <1>;
 128                         #reset-cells = <1>;
 129                 };
 130
 131                 mixer0: mixer@1100000 {
 132                         compatible = "allwinner,sun8i-r40-de2-mixer-0";
 133                         reg = <0x01100000 0x100000>;
 134                         clocks = <&display_clocks CLK_BUS_MIXER0>,
 135                                  <&display_clocks CLK_MIXER0>;
 136                         clock-names = "bus",
 137                                       "mod";
 138                         resets = <&display_clocks RST_MIXER0>;
 139
 140                         ports {
 141                                 #address-cells = <1>;
 142                                 #size-cells = <0>;
 143
 144                                 mixer0_out: port@1 {
 145                                         reg = <1>;
 146                                         mixer0_out_tcon_top: endpoint {
 147                                                 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
 148                                         };
 149                                 };
 150                         };
 151                 };
 152
 153                 mixer1: mixer@1200000 {
 154                         compatible = "allwinner,sun8i-r40-de2-mixer-1";
 155                         reg = <0x01200000 0x100000>;
 156                         clocks = <&display_clocks CLK_BUS_MIXER1>,
 157                                  <&display_clocks CLK_MIXER1>;
 158                         clock-names = "bus",
 159                                       "mod";
 160                         resets = <&display_clocks RST_WB>;
 161
 162                         ports {
 163                                 #address-cells = <1>;
 164                                 #size-cells = <0>;
 165
 166                                 mixer1_out: port@1 {
 167                                         reg = <1>;
 168                                         mixer1_out_tcon_top: endpoint {
 169                                                 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
 170                                         };
 171                                 };
 172                         };
 173                 };
 174
 175                 nmi_intc: interrupt-controller@1c00030 {
 176                         compatible = "allwinner,sun7i-a20-sc-nmi";
 177                         interrupt-controller;
 178                         #interrupt-cells = <2>;
 179                         reg = <0x01c00030 0x0c>;
 180                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 181                 };
 182
 183                 mmc0: mmc@1c0f000 {
 184                         compatible = "allwinner,sun8i-r40-mmc",
 185                                      "allwinner,sun50i-a64-mmc";
 186                         reg = <0x01c0f000 0x1000>;
 187                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 188                         clock-names = "ahb", "mmc";
 189                         resets = <&ccu RST_BUS_MMC0>;
 190                         reset-names = "ahb";
 191                         pinctrl-0 = <&mmc0_pins>;
 192                         pinctrl-names = "default";
 193                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 194                         status = "disabled";
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                 };
 198
 199                 mmc1: mmc@1c10000 {
 200                         compatible = "allwinner,sun8i-r40-mmc",
 201                                      "allwinner,sun50i-a64-mmc";
 202                         reg = <0x01c10000 0x1000>;
 203                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 204                         clock-names = "ahb", "mmc";
 205                         resets = <&ccu RST_BUS_MMC1>;
 206                         reset-names = "ahb";
 207                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 208                         status = "disabled";
 209                         #address-cells = <1>;
 210                         #size-cells = <0>;
 211                 };
 212
 213                 mmc2: mmc@1c11000 {
 214                         compatible = "allwinner,sun8i-r40-emmc",
 215                                      "allwinner,sun50i-a64-emmc";
 216                         reg = <0x01c11000 0x1000>;
 217                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 218                         clock-names = "ahb", "mmc";
 219                         resets = <&ccu RST_BUS_MMC2>;
 220                         reset-names = "ahb";
 221                         pinctrl-0 = <&mmc2_pins>;
 222                         pinctrl-names = "default";
 223                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 224                         status = "disabled";
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227                 };
 228
 229                 mmc3: mmc@1c12000 {
 230                         compatible = "allwinner,sun8i-r40-mmc",
 231                                      "allwinner,sun50i-a64-mmc";
 232                         reg = <0x01c12000 0x1000>;
 233                         clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
 234                         clock-names = "ahb", "mmc";
 235                         resets = <&ccu RST_BUS_MMC3>;
 236                         reset-names = "ahb";
 237                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 238                         status = "disabled";
 239                         #address-cells = <1>;
 240                         #size-cells = <0>;
 241                 };
 242
 243                 usbphy: phy@1c13400 {
 244                         compatible = "allwinner,sun8i-r40-usb-phy";
 245                         reg = <0x01c13400 0x14>,
 246                               <0x01c14800 0x4>,
 247                               <0x01c19800 0x4>,
 248                               <0x01c1c800 0x4>;
 249                         reg-names = "phy_ctrl",
 250                                     "pmu0",
 251                                     "pmu1",
 252                                     "pmu2";
 253                         clocks = <&ccu CLK_USB_PHY0>,
 254                                  <&ccu CLK_USB_PHY1>,
 255                                  <&ccu CLK_USB_PHY2>;
 256                         clock-names = "usb0_phy",
 257                                       "usb1_phy",
 258                                       "usb2_phy";
 259                         resets = <&ccu RST_USB_PHY0>,
 260                                  <&ccu RST_USB_PHY1>,
 261                                  <&ccu RST_USB_PHY2>;
 262                         reset-names = "usb0_reset",
 263                                       "usb1_reset",
 264                                       "usb2_reset";
 265                         status = "disabled";
 266                         #phy-cells = <1>;
 267                 };
 268
 269                 ehci1: usb@1c19000 {
 270                         compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
 271                         reg = <0x01c19000 0x100>;
 272                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 273                         clocks = <&ccu CLK_BUS_EHCI1>;
 274                         resets = <&ccu RST_BUS_EHCI1>;
 275                         phys = <&usbphy 1>;
 276                         status = "disabled";
 277                 };
 278
 279                 ohci1: usb@1c19400 {
 280                         compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
 281                         reg = <0x01c19400 0x100>;
 282                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 283                         clocks = <&ccu CLK_BUS_OHCI1>,
 284                                  <&ccu CLK_USB_OHCI1>;
 285                         resets = <&ccu RST_BUS_OHCI1>;
 286                         phys = <&usbphy 1>;
 287                         status = "disabled";
 288                 };
 289
 290                 ehci2: usb@1c1c000 {
 291                         compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
 292                         reg = <0x01c1c000 0x100>;
 293                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 294                         clocks = <&ccu CLK_BUS_EHCI2>;
 295                         resets = <&ccu RST_BUS_EHCI2>;
 296                         phys = <&usbphy 2>;
 297                         status = "disabled";
 298                 };
 299
 300                 ohci2: usb@1c1c400 {
 301                         compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
 302                         reg = <0x01c1c400 0x100>;
 303                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 304                         clocks = <&ccu CLK_BUS_OHCI2>,
 305                                  <&ccu CLK_USB_OHCI2>;
 306                         resets = <&ccu RST_BUS_OHCI2>;
 307                         phys = <&usbphy 2>;
 308                         status = "disabled";
 309                 };
 310
 311                 ccu: clock@1c20000 {
 312                         compatible = "allwinner,sun8i-r40-ccu";
 313                         reg = <0x01c20000 0x400>;
 314                         clocks = <&osc24M>, <&rtc 0>;
 315                         clock-names = "hosc", "losc";
 316                         #clock-cells = <1>;
 317                         #reset-cells = <1>;
 318                 };
 319
 320                 rtc: rtc@1c20400 {
 321                         compatible = "allwinner,sun8i-r40-rtc";
 322                         reg = <0x01c20400 0x400>;
 323                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 324                         clock-output-names = "osc32k", "osc32k-out";
 325                         clocks = <&osc32k>;
 326                         #clock-cells = <1>;
 327                 };
 328
 329                 pio: pinctrl@1c20800 {
 330                         compatible = "allwinner,sun8i-r40-pinctrl";
 331                         reg = <0x01c20800 0x400>;
 332                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 333                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 334                         clock-names = "apb", "hosc", "losc";
 335                         gpio-controller;
 336                         interrupt-controller;
 337                         #interrupt-cells = <3>;
 338                         #gpio-cells = <3>;
 339
 340                         clk_out_a_pin: clk-out-a-pin {
 341                                 pins = "PI12";
 342                                 function = "clk_out_a";
 343                         };
 344
 345                         gmac_rgmii_pins: gmac-rgmii-pins {
 346                                 pins = "PA0", "PA1", "PA2", "PA3",
 347                                        "PA4", "PA5", "PA6", "PA7",
 348                                        "PA8", "PA10", "PA11", "PA12",
 349                                        "PA13", "PA15", "PA16";
 350                                 function = "gmac";
 351                                 /*
 352                                  * data lines in RGMII mode use DDR mode
 353                                  * and need a higher signal drive strength
 354                                  */
 355                                 drive-strength = <40>;
 356                         };
 357
 358                         i2c0_pins: i2c0-pins {
 359                                 pins = "PB0", "PB1";
 360                                 function = "i2c0";
 361                         };
 362
 363                         mmc0_pins: mmc0-pins {
 364                                 pins = "PF0", "PF1", "PF2",
 365                                        "PF3", "PF4", "PF5";
 366                                 function = "mmc0";
 367                                 drive-strength = <30>;
 368                                 bias-pull-up;
 369                         };
 370
 371                         mmc1_pg_pins: mmc1-pg-pins {
 372                                 pins = "PG0", "PG1", "PG2",
 373                                        "PG3", "PG4", "PG5";
 374                                 function = "mmc1";
 375                                 drive-strength = <30>;
 376                                 bias-pull-up;
 377                         };
 378
 379                         mmc2_pins: mmc2-pins {
 380                                 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
 381                                        "PC10", "PC11", "PC12", "PC13", "PC14",
 382                                        "PC15", "PC24";
 383                                 function = "mmc2";
 384                                 drive-strength = <30>;
 385                                 bias-pull-up;
 386                         };
 387
 388                         uart0_pb_pins: uart0-pb-pins {
 389                                 pins = "PB22", "PB23";
 390                                 function = "uart0";
 391                         };
 392
 393                         uart3_pg_pins: uart3-pg-pins {
 394                                 pins = "PG6", "PG7";
 395                                 function = "uart3";
 396                         };
 397
 398                         uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
 399                                 pins = "PG8", "PG9";
 400                                 function = "uart3";
 401                         };
 402                 };
 403
 404                 wdt: watchdog@1c20c90 {
 405                         compatible = "allwinner,sun4i-a10-wdt";
 406                         reg = <0x01c20c90 0x10>;
 407                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 408                         clocks = <&osc24M>;
 409                 };
 410
 411                 uart0: serial@1c28000 {
 412                         compatible = "snps,dw-apb-uart";
 413                         reg = <0x01c28000 0x400>;
 414                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 415                         reg-shift = <2>;
 416                         reg-io-width = <4>;
 417                         clocks = <&ccu CLK_BUS_UART0>;
 418                         resets = <&ccu RST_BUS_UART0>;
 419                         status = "disabled";
 420                 };
 421
 422                 uart1: serial@1c28400 {
 423                         compatible = "snps,dw-apb-uart";
 424                         reg = <0x01c28400 0x400>;
 425                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 426                         reg-shift = <2>;
 427                         reg-io-width = <4>;
 428                         clocks = <&ccu CLK_BUS_UART1>;
 429                         resets = <&ccu RST_BUS_UART1>;
 430                         status = "disabled";
 431                 };
 432
 433                 uart2: serial@1c28800 {
 434                         compatible = "snps,dw-apb-uart";
 435                         reg = <0x01c28800 0x400>;
 436                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 437                         reg-shift = <2>;
 438                         reg-io-width = <4>;
 439                         clocks = <&ccu CLK_BUS_UART2>;
 440                         resets = <&ccu RST_BUS_UART2>;
 441                         status = "disabled";
 442                 };
 443
 444                 uart3: serial@1c28c00 {
 445                         compatible = "snps,dw-apb-uart";
 446                         reg = <0x01c28c00 0x400>;
 447                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 448                         reg-shift = <2>;
 449                         reg-io-width = <4>;
 450                         clocks = <&ccu CLK_BUS_UART3>;
 451                         resets = <&ccu RST_BUS_UART3>;
 452                         status = "disabled";
 453                 };
 454
 455                 uart4: serial@1c29000 {
 456                         compatible = "snps,dw-apb-uart";
 457                         reg = <0x01c29000 0x400>;
 458                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 459                         reg-shift = <2>;
 460                         reg-io-width = <4>;
 461                         clocks = <&ccu CLK_BUS_UART4>;
 462                         resets = <&ccu RST_BUS_UART4>;
 463                         status = "disabled";
 464                 };
 465
 466                 uart5: serial@1c29400 {
 467                         compatible = "snps,dw-apb-uart";
 468                         reg = <0x01c29400 0x400>;
 469                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 470                         reg-shift = <2>;
 471                         reg-io-width = <4>;
 472                         clocks = <&ccu CLK_BUS_UART5>;
 473                         resets = <&ccu RST_BUS_UART5>;
 474                         status = "disabled";
 475                 };
 476
 477                 uart6: serial@1c29800 {
 478                         compatible = "snps,dw-apb-uart";
 479                         reg = <0x01c29800 0x400>;
 480                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 481                         reg-shift = <2>;
 482                         reg-io-width = <4>;
 483                         clocks = <&ccu CLK_BUS_UART6>;
 484                         resets = <&ccu RST_BUS_UART6>;
 485                         status = "disabled";
 486                 };
 487
 488                 uart7: serial@1c29c00 {
 489                         compatible = "snps,dw-apb-uart";
 490                         reg = <0x01c29c00 0x400>;
 491                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 492                         reg-shift = <2>;
 493                         reg-io-width = <4>;
 494                         clocks = <&ccu CLK_BUS_UART7>;
 495                         resets = <&ccu RST_BUS_UART7>;
 496                         status = "disabled";
 497                 };
 498
 499                 i2c0: i2c@1c2ac00 {
 500                         compatible = "allwinner,sun6i-a31-i2c";
 501                         reg = <0x01c2ac00 0x400>;
 502                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 503                         clocks = <&ccu CLK_BUS_I2C0>;
 504                         resets = <&ccu RST_BUS_I2C0>;
 505                         pinctrl-0 = <&i2c0_pins>;
 506                         pinctrl-names = "default";
 507                         status = "disabled";
 508                         #address-cells = <1>;
 509                         #size-cells = <0>;
 510                 };
 511
 512                 i2c1: i2c@1c2b000 {
 513                         compatible = "allwinner,sun6i-a31-i2c";
 514                         reg = <0x01c2b000 0x400>;
 515                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 516                         clocks = <&ccu CLK_BUS_I2C1>;
 517                         resets = <&ccu RST_BUS_I2C1>;
 518                         status = "disabled";
 519                         #address-cells = <1>;
 520                         #size-cells = <0>;
 521                 };
 522
 523                 i2c2: i2c@1c2b400 {
 524                         compatible = "allwinner,sun6i-a31-i2c";
 525                         reg = <0x01c2b400 0x400>;
 526                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 527                         clocks = <&ccu CLK_BUS_I2C2>;
 528                         resets = <&ccu RST_BUS_I2C2>;
 529                         status = "disabled";
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                 };
 533
 534                 i2c3: i2c@1c2b800 {
 535                         compatible = "allwinner,sun6i-a31-i2c";
 536                         reg = <0x01c2b800 0x400>;
 537                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 538                         clocks = <&ccu CLK_BUS_I2C3>;
 539                         resets = <&ccu RST_BUS_I2C3>;
 540                         status = "disabled";
 541                         #address-cells = <1>;
 542                         #size-cells = <0>;
 543                 };
 544
 545                 i2c4: i2c@1c2c000 {
 546                         compatible = "allwinner,sun6i-a31-i2c";
 547                         reg = <0x01c2c000 0x400>;
 548                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 549                         clocks = <&ccu CLK_BUS_I2C4>;
 550                         resets = <&ccu RST_BUS_I2C4>;
 551                         status = "disabled";
 552                         #address-cells = <1>;
 553                         #size-cells = <0>;
 554                 };
 555
 556                 ahci: sata@1c18000 {
 557                         compatible = "allwinner,sun8i-r40-ahci";
 558                         reg = <0x01c18000 0x1000>;
 559                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 560                         clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
 561                         resets = <&ccu RST_BUS_SATA>;
 562                         reset-names = "ahci";
 563                         status = "disabled";
 564
 565                 };
 566
 567                 gmac: ethernet@1c50000 {
 568                         compatible = "allwinner,sun8i-r40-gmac";
 569                         syscon = <&ccu>;
 570                         reg = <0x01c50000 0x10000>;
 571                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 572                         interrupt-names = "macirq";
 573                         resets = <&ccu RST_BUS_GMAC>;
 574                         reset-names = "stmmaceth";
 575                         clocks = <&ccu CLK_BUS_GMAC>;
 576                         clock-names = "stmmaceth";
 577                         status = "disabled";
 578
 579                         gmac_mdio: mdio {
 580                                 compatible = "snps,dwmac-mdio";
 581                                 #address-cells = <1>;
 582                                 #size-cells = <0>;
 583                         };
 584                 };
 585
 586                 tcon_top: tcon-top@1c70000 {
 587                         compatible = "allwinner,sun8i-r40-tcon-top";
 588                         reg = <0x01c70000 0x1000>;
 589                         clocks = <&ccu CLK_BUS_TCON_TOP>,
 590                                  <&ccu CLK_TCON_TV0>,
 591                                  <&ccu CLK_TVE0>,
 592                                  <&ccu CLK_TCON_TV1>,
 593                                  <&ccu CLK_TVE1>,
 594                                  <&ccu CLK_DSI_DPHY>;
 595                         clock-names = "bus",
 596                                       "tcon-tv0",
 597                                       "tve0",
 598                                       "tcon-tv1",
 599                                       "tve1",
 600                                       "dsi";
 601                         clock-output-names = "tcon-top-tv0",
 602                                              "tcon-top-tv1",
 603                                              "tcon-top-dsi";
 604                         resets = <&ccu RST_BUS_TCON_TOP>;
 605                         #clock-cells = <1>;
 606
 607                         ports {
 608                                 #address-cells = <1>;
 609                                 #size-cells = <0>;
 610
 611                                 tcon_top_mixer0_in: port@0 {
 612                                         reg = <0>;
 613
 614                                         tcon_top_mixer0_in_mixer0: endpoint {
 615                                                 remote-endpoint = <&mixer0_out_tcon_top>;
 616                                         };
 617                                 };
 618
 619                                 tcon_top_mixer0_out: port@1 {
 620                                         #address-cells = <1>;
 621                                         #size-cells = <0>;
 622                                         reg = <1>;
 623
 624                                         tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
 625                                                 reg = <0>;
 626                                         };
 627
 628                                         tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
 629                                                 reg = <1>;
 630                                         };
 631
 632                                         tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
 633                                                 reg = <2>;
 634                                                 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
 635                                         };
 636
 637                                         tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
 638                                                 reg = <3>;
 639                                                 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
 640                                         };
 641                                 };
 642
 643                                 tcon_top_mixer1_in: port@2 {
 644                                         #address-cells = <1>;
 645                                         #size-cells = <0>;
 646                                         reg = <2>;
 647
 648                                         tcon_top_mixer1_in_mixer1: endpoint@1 {
 649                                                 reg = <1>;
 650                                                 remote-endpoint = <&mixer1_out_tcon_top>;
 651                                         };
 652                                 };
 653
 654                                 tcon_top_mixer1_out: port@3 {
 655                                         #address-cells = <1>;
 656                                         #size-cells = <0>;
 657                                         reg = <3>;
 658
 659                                         tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
 660                                                 reg = <0>;
 661                                         };
 662
 663                                         tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
 664                                                 reg = <1>;
 665                                         };
 666
 667                                         tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
 668                                                 reg = <2>;
 669                                                 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
 670                                         };
 671
 672                                         tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
 673                                                 reg = <3>;
 674                                                 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
 675                                         };
 676                                 };
 677
 678                                 tcon_top_hdmi_in: port@4 {
 679                                         #address-cells = <1>;
 680                                         #size-cells = <0>;
 681                                         reg = <4>;
 682
 683                                         tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
 684                                                 reg = <0>;
 685                                                 remote-endpoint = <&tcon_tv0_out_tcon_top>;
 686                                         };
 687
 688                                         tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
 689                                                 reg = <1>;
 690                                                 remote-endpoint = <&tcon_tv1_out_tcon_top>;
 691                                         };
 692                                 };
 693
 694                                 tcon_top_hdmi_out: port@5 {
 695                                         reg = <5>;
 696
 697                                         tcon_top_hdmi_out_hdmi: endpoint {
 698                                                 remote-endpoint = <&hdmi_in_tcon_top>;
 699                                         };
 700                                 };
 701                         };
 702                 };
 703
 704                 tcon_tv0: lcd-controller@1c73000 {
 705                         compatible = "allwinner,sun8i-r40-tcon-tv";
 706                         reg = <0x01c73000 0x1000>;
 707                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 708                         clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
 709                         clock-names = "ahb", "tcon-ch1";
 710                         resets = <&ccu RST_BUS_TCON_TV0>;
 711                         reset-names = "lcd";
 712                         status = "disabled";
 713
 714                         ports {
 715                                 #address-cells = <1>;
 716                                 #size-cells = <0>;
 717
 718                                 tcon_tv0_in: port@0 {
 719                                         #address-cells = <1>;
 720                                         #size-cells = <0>;
 721                                         reg = <0>;
 722
 723                                         tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
 724                                                 reg = <0>;
 725                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
 726                                         };
 727
 728                                         tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
 729                                                 reg = <1>;
 730                                                 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
 731                                         };
 732                                 };
 733
 734                                 tcon_tv0_out: port@1 {
 735                                         #address-cells = <1>;
 736                                         #size-cells = <0>;
 737                                         reg = <1>;
 738
 739                                         tcon_tv0_out_tcon_top: endpoint@1 {
 740                                                 reg = <1>;
 741                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
 742                                         };
 743                                 };
 744                         };
 745                 };
 746
 747                 tcon_tv1: lcd-controller@1c74000 {
 748                         compatible = "allwinner,sun8i-r40-tcon-tv";
 749                         reg = <0x01c74000 0x1000>;
 750                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 751                         clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
 752                         clock-names = "ahb", "tcon-ch1";
 753                         resets = <&ccu RST_BUS_TCON_TV1>;
 754                         reset-names = "lcd";
 755                         status = "disabled";
 756
 757                         ports {
 758                                 #address-cells = <1>;
 759                                 #size-cells = <0>;
 760
 761                                 tcon_tv1_in: port@0 {
 762                                         #address-cells = <1>;
 763                                         #size-cells = <0>;
 764                                         reg = <0>;
 765
 766                                         tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
 767                                                 reg = <0>;
 768                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
 769                                         };
 770
 771                                         tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
 772                                                 reg = <1>;
 773                                                 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
 774                                         };
 775                                 };
 776
 777                                 tcon_tv1_out: port@1 {
 778                                         #address-cells = <1>;
 779                                         #size-cells = <0>;
 780                                         reg = <1>;
 781
 782                                         tcon_tv1_out_tcon_top: endpoint@1 {
 783                                                 reg = <1>;
 784                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
 785                                         };
 786                                 };
 787                         };
 788                 };
 789
 790                 gic: interrupt-controller@1c81000 {
 791                         compatible = "arm,gic-400";
 792                         reg = <0x01c81000 0x1000>,
 793                               <0x01c82000 0x1000>,
 794                               <0x01c84000 0x2000>,
 795                               <0x01c86000 0x2000>;
 796                         interrupt-controller;
 797                         #interrupt-cells = <3>;
 798                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 799                 };
 800
 801                 hdmi: hdmi@1ee0000 {
 802                         compatible = "allwinner,sun8i-r40-dw-hdmi",
 803                                      "allwinner,sun8i-a83t-dw-hdmi";
 804                         reg = <0x01ee0000 0x10000>;
 805                         reg-io-width = <1>;
 806                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 807                         clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
 808                                  <&ccu CLK_HDMI>;
 809                         clock-names = "iahb", "isfr", "tmds";
 810                         resets = <&ccu RST_BUS_HDMI1>;
 811                         reset-names = "ctrl";
 812                         phys = <&hdmi_phy>;
 813                         phy-names = "phy";
 814                         status = "disabled";
 815
 816                         ports {
 817                                 #address-cells = <1>;
 818                                 #size-cells = <0>;
 819
 820                                 hdmi_in: port@0 {
 821                                         reg = <0>;
 822
 823                                         hdmi_in_tcon_top: endpoint {
 824                                                 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
 825                                         };
 826                                 };
 827
 828                                 hdmi_out: port@1 {
 829                                         reg = <1>;
 830                                 };
 831                         };
 832                 };
 833
 834                 hdmi_phy: hdmi-phy@1ef0000 {
 835                         compatible = "allwinner,sun8i-r40-hdmi-phy";
 836                         reg = <0x01ef0000 0x10000>;
 837                         clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
 838                                  <&ccu 7>, <&ccu 16>;
 839                         clock-names = "bus", "mod", "pll-0", "pll-1";
 840                         resets = <&ccu RST_BUS_HDMI0>;
 841                         reset-names = "phy";
 842                         #phy-cells = <0>;
 843                 };
 844         };
 845
 846         timer {
 847                 compatible = "arm,armv7-timer";
 848                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 849                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 850                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 851                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 852         };
 853 };