2 * arch/arm/mach-at91/pm.c
3 * AT91 Power Management
5 * Copyright (C) 2005 David Brownell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/genalloc.h>
15 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include <linux/parser.h>
19 #include <linux/suspend.h>
21 #include <linux/clk/at91_pmc.h>
23 #include <asm/cacheflush.h>
24 #include <asm/fncpy.h>
25 #include <asm/system_misc.h>
26 #include <asm/suspend.h>
32 * FIXME: this is needed to communicate between the pinctrl driver and
33 * the PM implementation in the machine. Possibly part of the PM
34 * implementation should be moved down into the pinctrl driver and get
35 * called as part of the generic suspend/resume path.
37 #ifdef CONFIG_PINCTRL_AT91
38 extern void at91_pinctrl_gpio_suspend(void);
39 extern void at91_pinctrl_gpio_resume(void);
42 static const match_table_t pm_modes __initconst = {
43 { AT91_PM_STANDBY, "standby" },
44 { AT91_PM_ULP0, "ulp0" },
45 { AT91_PM_ULP1, "ulp1" },
46 { AT91_PM_BACKUP, "backup" },
50 static struct at91_pm_data pm_data = {
51 .standby_mode = AT91_PM_STANDBY,
52 .suspend_mode = AT91_PM_ULP0,
55 #define at91_ramc_read(id, field) \
56 __raw_readl(pm_data.ramc[id] + field)
58 #define at91_ramc_write(id, field, value) \
59 __raw_writel(value, pm_data.ramc[id] + field)
61 static int at91_pm_valid_state(suspend_state_t state)
65 case PM_SUSPEND_STANDBY:
74 static int canary = 0xA5A5A5A5;
76 static struct at91_pm_bu {
78 unsigned long reserved;
83 struct wakeup_source_info {
84 unsigned int pmc_fsmr_bit;
85 unsigned int shdwc_mr_bit;
89 static const struct wakeup_source_info ws_info[] = {
90 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
91 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
92 { .pmc_fsmr_bit = AT91_PMC_USBAL },
93 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
96 static const struct of_device_id sama5d2_ws_ids[] = {
97 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
98 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] },
99 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
100 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
101 { .compatible = "usb-ohci", .data = &ws_info[2] },
102 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
103 { .compatible = "usb-ehci", .data = &ws_info[2] },
104 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
108 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
110 const struct wakeup_source_info *wsi;
111 const struct of_device_id *match;
112 struct platform_device *pdev;
113 struct device_node *np;
114 unsigned int mode = 0, polarity = 0, val = 0;
116 if (pm_mode != AT91_PM_ULP1)
119 if (!pm_data.pmc || !pm_data.shdwc)
123 writel(mode, pm_data.pmc + AT91_PMC_FSMR);
128 val = readl(pm_data.shdwc + 0x0c);
129 mode |= (val & 0x3ff);
130 polarity |= ((val >> 16) & 0x3ff);
133 val = readl(pm_data.shdwc + 0x04);
135 /* Loop through defined wakeup sources. */
136 for_each_matching_node_and_match(np, sama5d2_ws_ids, &match) {
137 pdev = of_find_device_by_node(np);
141 if (device_may_wakeup(&pdev->dev)) {
144 /* Check if enabled on SHDWC. */
145 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
148 mode |= wsi->pmc_fsmr_bit;
149 if (wsi->set_polarity)
150 polarity |= wsi->pmc_fsmr_bit;
154 put_device(&pdev->dev);
158 writel(mode, pm_data.pmc + AT91_PMC_FSMR);
159 writel(polarity, pm_data.pmc + AT91_PMC_FSPR);
161 pr_err("AT91: PM: no ULP1 wakeup sources found!");
164 return mode ? 0 : -EPERM;
168 * Called after processes are frozen, but before we shutdown devices.
170 static int at91_pm_begin(suspend_state_t state)
174 pm_data.mode = pm_data.suspend_mode;
177 case PM_SUSPEND_STANDBY:
178 pm_data.mode = pm_data.standby_mode;
185 return at91_pm_config_ws(pm_data.mode, true);
189 * Verify that all the clocks are correct before entering
192 static int at91_pm_verify_clocks(void)
197 scsr = readl(pm_data.pmc + AT91_PMC_SCSR);
199 /* USB must not be using PLLB */
200 if ((scsr & pm_data.uhp_udp_mask) != 0) {
201 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
205 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
206 for (i = 0; i < 4; i++) {
209 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
211 css = readl(pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
212 if (css != AT91_PMC_CSS_SLOW) {
213 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
222 * Call this from platform driver suspend() to see how deeply to suspend.
223 * For example, some controllers (like OHCI) need one of the PLL clocks
224 * in order to act as a wakeup source, and those are not available when
225 * going into slow clock mode.
227 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
228 * the very same problem (but not using at91 main_clk), and it'd be better
229 * to add one generic API rather than lots of platform-specific ones.
231 int at91_suspend_entering_slow_clock(void)
233 return (pm_data.mode >= AT91_PM_ULP0);
235 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
237 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
238 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
239 extern u32 at91_pm_suspend_in_sram_sz;
241 static int at91_suspend_finish(unsigned long val)
246 at91_suspend_sram_fn(&pm_data);
251 static void at91_pm_suspend(suspend_state_t state)
253 if (pm_data.mode == AT91_PM_BACKUP) {
254 pm_bu->suspended = 1;
256 cpu_suspend(0, at91_suspend_finish);
258 /* The SRAM is lost between suspend cycles */
259 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
260 &at91_pm_suspend_in_sram,
261 at91_pm_suspend_in_sram_sz);
263 at91_suspend_finish(0);
270 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
271 * event sources; and reduces DRAM power. But otherwise it's identical to
272 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
274 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
275 * suspend more deeply, the master clock switches to the clk32k and turns off
276 * the main oscillator
278 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
280 static int at91_pm_enter(suspend_state_t state)
282 #ifdef CONFIG_PINCTRL_AT91
283 at91_pinctrl_gpio_suspend();
288 case PM_SUSPEND_STANDBY:
290 * Ensure that clocks are in a valid state.
292 if (pm_data.mode >= AT91_PM_ULP0 &&
293 !at91_pm_verify_clocks())
296 at91_pm_suspend(state);
305 pr_debug("AT91: PM - bogus suspend state %d\n", state);
310 #ifdef CONFIG_PINCTRL_AT91
311 at91_pinctrl_gpio_resume();
317 * Called right prior to thawing processes.
319 static void at91_pm_end(void)
321 at91_pm_config_ws(pm_data.mode, false);
325 static const struct platform_suspend_ops at91_pm_ops = {
326 .valid = at91_pm_valid_state,
327 .begin = at91_pm_begin,
328 .enter = at91_pm_enter,
332 static struct platform_device at91_cpuidle_device = {
333 .name = "cpuidle-at91",
337 * The AT91RM9200 goes into self-refresh mode with this command, and will
338 * terminate self-refresh automatically on the next SDRAM access.
340 * Self-refresh mode is exited as soon as a memory access is made, but we don't
341 * know for sure when that happens. However, we need to restore the low-power
342 * mode if it was enabled before going idle. Restoring low-power mode while
343 * still in self-refresh is "not recommended", but seems to work.
345 static void at91rm9200_standby(void)
350 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
351 " str %2, [%1, %3]\n\t"
352 " mcr p15, 0, %0, c7, c0, 4\n\t"
354 : "r" (0), "r" (pm_data.ramc[0]),
355 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
358 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
361 static void at91_ddr_standby(void)
363 /* Those two values allow us to delay self-refresh activation
366 u32 mdr, saved_mdr0, saved_mdr1 = 0;
367 u32 saved_lpr0, saved_lpr1 = 0;
369 /* LPDDR1 --> force DDR2 mode during self-refresh */
370 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
371 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
372 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
373 mdr |= AT91_DDRSDRC_MD_DDR2;
374 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
377 if (pm_data.ramc[1]) {
378 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
379 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
380 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
381 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
382 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
383 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
384 mdr |= AT91_DDRSDRC_MD_DDR2;
385 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
389 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
390 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
391 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
393 /* self-refresh mode now */
394 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
396 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
400 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
401 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
402 if (pm_data.ramc[1]) {
403 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
404 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
408 static void sama5d3_ddr_standby(void)
413 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
414 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
415 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
417 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
421 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
424 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
427 static void at91sam9_sdram_standby(void)
430 u32 saved_lpr0, saved_lpr1 = 0;
432 if (pm_data.ramc[1]) {
433 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
434 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
435 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
438 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
439 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
440 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
442 /* self-refresh mode now */
443 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
445 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
449 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
451 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
456 unsigned int memctrl;
459 static const struct ramc_info ramc_infos[] __initconst = {
460 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
461 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
462 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
463 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
466 static const struct of_device_id ramc_ids[] __initconst = {
467 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
468 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
469 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
470 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
474 static __init void at91_dt_ramc(void)
476 struct device_node *np;
477 const struct of_device_id *of_id;
479 void *standby = NULL;
480 const struct ramc_info *ramc;
482 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
483 pm_data.ramc[idx] = of_iomap(np, 0);
484 if (!pm_data.ramc[idx])
485 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
489 standby = ramc->idle;
490 pm_data.memctrl = ramc->memctrl;
496 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
499 pr_warn("ramc no standby function available\n");
503 at91_cpuidle_device.dev.platform_data = standby;
506 static void at91rm9200_idle(void)
509 * Disable the processor clock. The processor will be automatically
510 * re-enabled by an interrupt or by a reset.
512 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
515 static void at91sam9_idle(void)
517 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
521 static void __init at91_pm_sram_init(void)
523 struct gen_pool *sram_pool;
524 phys_addr_t sram_pbase;
525 unsigned long sram_base;
526 struct device_node *node;
527 struct platform_device *pdev = NULL;
529 for_each_compatible_node(node, NULL, "mmio-sram") {
530 pdev = of_find_device_by_node(node);
538 pr_warn("%s: failed to find sram device!\n", __func__);
542 sram_pool = gen_pool_get(&pdev->dev, NULL);
544 pr_warn("%s: sram pool unavailable!\n", __func__);
548 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
550 pr_warn("%s: unable to alloc sram!\n", __func__);
554 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
555 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
556 at91_pm_suspend_in_sram_sz, false);
557 if (!at91_suspend_sram_fn) {
558 pr_warn("SRAM: Could not map\n");
562 /* Copy the pm suspend handler to SRAM */
563 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
564 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
567 static bool __init at91_is_pm_mode_active(int pm_mode)
569 return (pm_data.standby_mode == pm_mode ||
570 pm_data.suspend_mode == pm_mode);
573 static int __init at91_pm_backup_init(void)
575 struct gen_pool *sram_pool;
576 struct device_node *np;
577 struct platform_device *pdev = NULL;
580 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
583 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
585 pr_warn("%s: failed to find sfrbu!\n", __func__);
589 pm_data.sfrbu = of_iomap(np, 0);
592 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
596 pdev = of_find_device_by_node(np);
599 pr_warn("%s: failed to find securam device!\n", __func__);
603 sram_pool = gen_pool_get(&pdev->dev, NULL);
605 pr_warn("%s: securam pool unavailable!\n", __func__);
609 pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
611 pr_warn("%s: unable to alloc securam!\n", __func__);
616 pm_bu->suspended = 0;
617 pm_bu->canary = __pa_symbol(&canary);
618 pm_bu->resume = __pa_symbol(cpu_resume);
623 iounmap(pm_data.sfrbu);
624 pm_data.sfrbu = NULL;
628 static void __init at91_pm_use_default_mode(int pm_mode)
630 if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP)
633 if (pm_data.standby_mode == pm_mode)
634 pm_data.standby_mode = AT91_PM_ULP0;
635 if (pm_data.suspend_mode == pm_mode)
636 pm_data.suspend_mode = AT91_PM_ULP0;
639 static void __init at91_pm_modes_init(void)
641 struct device_node *np;
644 if (!at91_is_pm_mode_active(AT91_PM_BACKUP) &&
645 !at91_is_pm_mode_active(AT91_PM_ULP1))
648 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc");
650 pr_warn("%s: failed to find shdwc!\n", __func__);
654 pm_data.shdwc = of_iomap(np, 0);
657 ret = at91_pm_backup_init();
659 if (!at91_is_pm_mode_active(AT91_PM_ULP1))
668 iounmap(pm_data.shdwc);
669 pm_data.shdwc = NULL;
671 at91_pm_use_default_mode(AT91_PM_ULP1);
673 at91_pm_use_default_mode(AT91_PM_BACKUP);
677 unsigned long uhp_udp_mask;
680 static const struct pmc_info pmc_infos[] __initconst = {
681 { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP },
682 { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP },
683 { .uhp_udp_mask = AT91SAM926x_PMC_UHP },
684 { .uhp_udp_mask = 0 },
687 static const struct of_device_id atmel_pmc_ids[] __initconst = {
688 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
689 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
690 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
691 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
692 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
693 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
694 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
695 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
696 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
697 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
698 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
702 static void __init at91_pm_init(void (*pm_idle)(void))
704 struct device_node *pmc_np;
705 const struct of_device_id *of_id;
706 const struct pmc_info *pmc;
708 if (at91_cpuidle_device.dev.platform_data)
709 platform_device_register(&at91_cpuidle_device);
711 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
712 pm_data.pmc = of_iomap(pmc_np, 0);
714 pr_err("AT91: PM not supported, PMC not found\n");
719 pm_data.uhp_udp_mask = pmc->uhp_udp_mask;
722 arm_pm_idle = pm_idle;
726 if (at91_suspend_sram_fn) {
727 suspend_set_ops(&at91_pm_ops);
728 pr_info("AT91: PM: standby: %s, suspend: %s\n",
729 pm_modes[pm_data.standby_mode].pattern,
730 pm_modes[pm_data.suspend_mode].pattern);
732 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
736 void __init at91rm9200_pm_init(void)
738 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
744 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
746 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
748 at91_pm_init(at91rm9200_idle);
751 void __init at91sam9_pm_init(void)
753 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
757 at91_pm_init(at91sam9_idle);
760 void __init sama5_pm_init(void)
762 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
769 void __init sama5d2_pm_init(void)
771 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
774 at91_pm_modes_init();
778 static int __init at91_pm_modes_select(char *str)
781 substring_t args[MAX_OPT_ARGS];
782 int standby, suspend;
787 s = strsep(&str, ",");
788 standby = match_token(s, pm_modes, args);
792 suspend = match_token(str, pm_modes, args);
796 pm_data.standby_mode = standby;
797 pm_data.suspend_mode = suspend;
801 early_param("atmel.pm_modes", at91_pm_modes_select);