2 * arch/arm/mach-at91/pm.c
3 * AT91 Power Management
5 * Copyright (C) 2005 David Brownell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/genalloc.h>
15 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include <linux/parser.h>
19 #include <linux/suspend.h>
21 #include <linux/clk/at91_pmc.h>
23 #include <asm/cacheflush.h>
24 #include <asm/fncpy.h>
25 #include <asm/system_misc.h>
26 #include <asm/suspend.h>
32 * FIXME: this is needed to communicate between the pinctrl driver and
33 * the PM implementation in the machine. Possibly part of the PM
34 * implementation should be moved down into the pinctrl driver and get
35 * called as part of the generic suspend/resume path.
37 #ifdef CONFIG_PINCTRL_AT91
38 extern void at91_pinctrl_gpio_suspend(void);
39 extern void at91_pinctrl_gpio_resume(void);
43 struct at91_pm_data data;
46 static struct at91_soc_pm soc_pm = {
48 .standby_mode = AT91_PM_STANDBY,
49 .suspend_mode = AT91_PM_ULP0,
53 static const match_table_t pm_modes __initconst = {
54 { AT91_PM_STANDBY, "standby" },
55 { AT91_PM_ULP0, "ulp0" },
56 { AT91_PM_ULP1, "ulp1" },
57 { AT91_PM_BACKUP, "backup" },
61 #define at91_ramc_read(id, field) \
62 __raw_readl(soc_pm.data.ramc[id] + field)
64 #define at91_ramc_write(id, field, value) \
65 __raw_writel(value, soc_pm.data.ramc[id] + field)
67 static int at91_pm_valid_state(suspend_state_t state)
71 case PM_SUSPEND_STANDBY:
80 static int canary = 0xA5A5A5A5;
82 static struct at91_pm_bu {
84 unsigned long reserved;
89 struct wakeup_source_info {
90 unsigned int pmc_fsmr_bit;
91 unsigned int shdwc_mr_bit;
95 static const struct wakeup_source_info ws_info[] = {
96 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
97 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
98 { .pmc_fsmr_bit = AT91_PMC_USBAL },
99 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
102 static const struct of_device_id sama5d2_ws_ids[] = {
103 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
104 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] },
105 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
106 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
107 { .compatible = "usb-ohci", .data = &ws_info[2] },
108 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
109 { .compatible = "usb-ehci", .data = &ws_info[2] },
110 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
114 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
116 const struct wakeup_source_info *wsi;
117 const struct of_device_id *match;
118 struct platform_device *pdev;
119 struct device_node *np;
120 unsigned int mode = 0, polarity = 0, val = 0;
122 if (pm_mode != AT91_PM_ULP1)
125 if (!soc_pm.data.pmc || !soc_pm.data.shdwc)
129 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
134 val = readl(soc_pm.data.shdwc + 0x0c);
135 mode |= (val & 0x3ff);
136 polarity |= ((val >> 16) & 0x3ff);
139 val = readl(soc_pm.data.shdwc + 0x04);
141 /* Loop through defined wakeup sources. */
142 for_each_matching_node_and_match(np, sama5d2_ws_ids, &match) {
143 pdev = of_find_device_by_node(np);
147 if (device_may_wakeup(&pdev->dev)) {
150 /* Check if enabled on SHDWC. */
151 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
154 mode |= wsi->pmc_fsmr_bit;
155 if (wsi->set_polarity)
156 polarity |= wsi->pmc_fsmr_bit;
160 put_device(&pdev->dev);
164 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
165 writel(polarity, soc_pm.data.pmc + AT91_PMC_FSPR);
167 pr_err("AT91: PM: no ULP1 wakeup sources found!");
170 return mode ? 0 : -EPERM;
174 * Called after processes are frozen, but before we shutdown devices.
176 static int at91_pm_begin(suspend_state_t state)
180 soc_pm.data.mode = soc_pm.data.suspend_mode;
183 case PM_SUSPEND_STANDBY:
184 soc_pm.data.mode = soc_pm.data.standby_mode;
188 soc_pm.data.mode = -1;
191 return at91_pm_config_ws(soc_pm.data.mode, true);
195 * Verify that all the clocks are correct before entering
198 static int at91_pm_verify_clocks(void)
203 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
205 /* USB must not be using PLLB */
206 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
207 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
211 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
212 for (i = 0; i < 4; i++) {
215 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
217 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
218 if (css != AT91_PMC_CSS_SLOW) {
219 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
228 * Call this from platform driver suspend() to see how deeply to suspend.
229 * For example, some controllers (like OHCI) need one of the PLL clocks
230 * in order to act as a wakeup source, and those are not available when
231 * going into slow clock mode.
233 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
234 * the very same problem (but not using at91 main_clk), and it'd be better
235 * to add one generic API rather than lots of platform-specific ones.
237 int at91_suspend_entering_slow_clock(void)
239 return (soc_pm.data.mode >= AT91_PM_ULP0);
241 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
243 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
244 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
245 extern u32 at91_pm_suspend_in_sram_sz;
247 static int at91_suspend_finish(unsigned long val)
252 at91_suspend_sram_fn(&soc_pm.data);
257 static void at91_pm_suspend(suspend_state_t state)
259 if (soc_pm.data.mode == AT91_PM_BACKUP) {
260 pm_bu->suspended = 1;
262 cpu_suspend(0, at91_suspend_finish);
264 /* The SRAM is lost between suspend cycles */
265 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
266 &at91_pm_suspend_in_sram,
267 at91_pm_suspend_in_sram_sz);
269 at91_suspend_finish(0);
276 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
277 * event sources; and reduces DRAM power. But otherwise it's identical to
278 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
280 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
281 * suspend more deeply, the master clock switches to the clk32k and turns off
282 * the main oscillator
284 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
286 static int at91_pm_enter(suspend_state_t state)
288 #ifdef CONFIG_PINCTRL_AT91
289 at91_pinctrl_gpio_suspend();
294 case PM_SUSPEND_STANDBY:
296 * Ensure that clocks are in a valid state.
298 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
299 !at91_pm_verify_clocks())
302 at91_pm_suspend(state);
311 pr_debug("AT91: PM - bogus suspend state %d\n", state);
316 #ifdef CONFIG_PINCTRL_AT91
317 at91_pinctrl_gpio_resume();
323 * Called right prior to thawing processes.
325 static void at91_pm_end(void)
327 at91_pm_config_ws(soc_pm.data.mode, false);
331 static const struct platform_suspend_ops at91_pm_ops = {
332 .valid = at91_pm_valid_state,
333 .begin = at91_pm_begin,
334 .enter = at91_pm_enter,
338 static struct platform_device at91_cpuidle_device = {
339 .name = "cpuidle-at91",
343 * The AT91RM9200 goes into self-refresh mode with this command, and will
344 * terminate self-refresh automatically on the next SDRAM access.
346 * Self-refresh mode is exited as soon as a memory access is made, but we don't
347 * know for sure when that happens. However, we need to restore the low-power
348 * mode if it was enabled before going idle. Restoring low-power mode while
349 * still in self-refresh is "not recommended", but seems to work.
351 static void at91rm9200_standby(void)
356 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
357 " str %2, [%1, %3]\n\t"
358 " mcr p15, 0, %0, c7, c0, 4\n\t"
360 : "r" (0), "r" (soc_pm.data.ramc[0]),
361 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
364 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
367 static void at91_ddr_standby(void)
369 /* Those two values allow us to delay self-refresh activation
372 u32 mdr, saved_mdr0, saved_mdr1 = 0;
373 u32 saved_lpr0, saved_lpr1 = 0;
375 /* LPDDR1 --> force DDR2 mode during self-refresh */
376 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
377 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
378 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
379 mdr |= AT91_DDRSDRC_MD_DDR2;
380 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
383 if (soc_pm.data.ramc[1]) {
384 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
385 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
386 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
387 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
388 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
389 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
390 mdr |= AT91_DDRSDRC_MD_DDR2;
391 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
395 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
396 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
397 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
399 /* self-refresh mode now */
400 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
401 if (soc_pm.data.ramc[1])
402 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
406 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
407 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
408 if (soc_pm.data.ramc[1]) {
409 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
410 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
414 static void sama5d3_ddr_standby(void)
419 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
420 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
421 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
423 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
427 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
430 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
433 static void at91sam9_sdram_standby(void)
436 u32 saved_lpr0, saved_lpr1 = 0;
438 if (soc_pm.data.ramc[1]) {
439 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
440 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
441 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
444 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
445 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
446 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
448 /* self-refresh mode now */
449 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
450 if (soc_pm.data.ramc[1])
451 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
455 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
456 if (soc_pm.data.ramc[1])
457 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
462 unsigned int memctrl;
465 static const struct ramc_info ramc_infos[] __initconst = {
466 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
467 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
468 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
469 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
472 static const struct of_device_id ramc_ids[] __initconst = {
473 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
474 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
475 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
476 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
480 static __init void at91_dt_ramc(void)
482 struct device_node *np;
483 const struct of_device_id *of_id;
485 void *standby = NULL;
486 const struct ramc_info *ramc;
488 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
489 soc_pm.data.ramc[idx] = of_iomap(np, 0);
490 if (!soc_pm.data.ramc[idx])
491 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
495 standby = ramc->idle;
496 soc_pm.data.memctrl = ramc->memctrl;
502 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
505 pr_warn("ramc no standby function available\n");
509 at91_cpuidle_device.dev.platform_data = standby;
512 static void at91rm9200_idle(void)
515 * Disable the processor clock. The processor will be automatically
516 * re-enabled by an interrupt or by a reset.
518 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
521 static void at91sam9_idle(void)
523 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
527 static void __init at91_pm_sram_init(void)
529 struct gen_pool *sram_pool;
530 phys_addr_t sram_pbase;
531 unsigned long sram_base;
532 struct device_node *node;
533 struct platform_device *pdev = NULL;
535 for_each_compatible_node(node, NULL, "mmio-sram") {
536 pdev = of_find_device_by_node(node);
544 pr_warn("%s: failed to find sram device!\n", __func__);
548 sram_pool = gen_pool_get(&pdev->dev, NULL);
550 pr_warn("%s: sram pool unavailable!\n", __func__);
554 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
556 pr_warn("%s: unable to alloc sram!\n", __func__);
560 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
561 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
562 at91_pm_suspend_in_sram_sz, false);
563 if (!at91_suspend_sram_fn) {
564 pr_warn("SRAM: Could not map\n");
568 /* Copy the pm suspend handler to SRAM */
569 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
570 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
573 static bool __init at91_is_pm_mode_active(int pm_mode)
575 return (soc_pm.data.standby_mode == pm_mode ||
576 soc_pm.data.suspend_mode == pm_mode);
579 static int __init at91_pm_backup_init(void)
581 struct gen_pool *sram_pool;
582 struct device_node *np;
583 struct platform_device *pdev = NULL;
586 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
589 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
591 pr_warn("%s: failed to find sfrbu!\n", __func__);
595 soc_pm.data.sfrbu = of_iomap(np, 0);
598 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
602 pdev = of_find_device_by_node(np);
605 pr_warn("%s: failed to find securam device!\n", __func__);
609 sram_pool = gen_pool_get(&pdev->dev, NULL);
611 pr_warn("%s: securam pool unavailable!\n", __func__);
615 pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
617 pr_warn("%s: unable to alloc securam!\n", __func__);
622 pm_bu->suspended = 0;
623 pm_bu->canary = __pa_symbol(&canary);
624 pm_bu->resume = __pa_symbol(cpu_resume);
629 iounmap(soc_pm.data.sfrbu);
630 soc_pm.data.sfrbu = NULL;
634 static void __init at91_pm_use_default_mode(int pm_mode)
636 if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP)
639 if (soc_pm.data.standby_mode == pm_mode)
640 soc_pm.data.standby_mode = AT91_PM_ULP0;
641 if (soc_pm.data.suspend_mode == pm_mode)
642 soc_pm.data.suspend_mode = AT91_PM_ULP0;
645 static void __init at91_pm_modes_init(void)
647 struct device_node *np;
650 if (!at91_is_pm_mode_active(AT91_PM_BACKUP) &&
651 !at91_is_pm_mode_active(AT91_PM_ULP1))
654 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc");
656 pr_warn("%s: failed to find shdwc!\n", __func__);
660 soc_pm.data.shdwc = of_iomap(np, 0);
663 ret = at91_pm_backup_init();
665 if (!at91_is_pm_mode_active(AT91_PM_ULP1))
674 iounmap(soc_pm.data.shdwc);
675 soc_pm.data.shdwc = NULL;
677 at91_pm_use_default_mode(AT91_PM_ULP1);
679 at91_pm_use_default_mode(AT91_PM_BACKUP);
683 unsigned long uhp_udp_mask;
686 static const struct pmc_info pmc_infos[] __initconst = {
687 { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP },
688 { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP },
689 { .uhp_udp_mask = AT91SAM926x_PMC_UHP },
690 { .uhp_udp_mask = 0 },
693 static const struct of_device_id atmel_pmc_ids[] __initconst = {
694 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
695 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
696 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
697 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
698 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
699 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
700 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
701 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
702 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
703 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
704 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
708 static void __init at91_pm_init(void (*pm_idle)(void))
710 struct device_node *pmc_np;
711 const struct of_device_id *of_id;
712 const struct pmc_info *pmc;
714 if (at91_cpuidle_device.dev.platform_data)
715 platform_device_register(&at91_cpuidle_device);
717 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
718 soc_pm.data.pmc = of_iomap(pmc_np, 0);
719 if (!soc_pm.data.pmc) {
720 pr_err("AT91: PM not supported, PMC not found\n");
725 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
728 arm_pm_idle = pm_idle;
732 if (at91_suspend_sram_fn) {
733 suspend_set_ops(&at91_pm_ops);
734 pr_info("AT91: PM: standby: %s, suspend: %s\n",
735 pm_modes[soc_pm.data.standby_mode].pattern,
736 pm_modes[soc_pm.data.suspend_mode].pattern);
738 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
742 void __init at91rm9200_pm_init(void)
744 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
750 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
752 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
754 at91_pm_init(at91rm9200_idle);
757 void __init at91sam9_pm_init(void)
759 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
763 at91_pm_init(at91sam9_idle);
766 void __init sama5_pm_init(void)
768 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
775 void __init sama5d2_pm_init(void)
777 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
780 at91_pm_modes_init();
784 static int __init at91_pm_modes_select(char *str)
787 substring_t args[MAX_OPT_ARGS];
788 int standby, suspend;
793 s = strsep(&str, ",");
794 standby = match_token(s, pm_modes, args);
798 suspend = match_token(str, pm_modes, args);
802 soc_pm.data.standby_mode = standby;
803 soc_pm.data.suspend_mode = suspend;
807 early_param("atmel.pm_modes", at91_pm_modes_select);