1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/mach-at91/pm.c
4 * AT91 Power Management
6 * Copyright (C) 2005 David Brownell
9 #include <linux/genalloc.h>
11 #include <linux/of_address.h>
13 #include <linux/of_platform.h>
14 #include <linux/parser.h>
15 #include <linux/suspend.h>
17 #include <linux/clk/at91_pmc.h>
19 #include <asm/cacheflush.h>
20 #include <asm/fncpy.h>
21 #include <asm/system_misc.h>
22 #include <asm/suspend.h>
28 * FIXME: this is needed to communicate between the pinctrl driver and
29 * the PM implementation in the machine. Possibly part of the PM
30 * implementation should be moved down into the pinctrl driver and get
31 * called as part of the generic suspend/resume path.
33 #ifdef CONFIG_PINCTRL_AT91
34 extern void at91_pinctrl_gpio_suspend(void);
35 extern void at91_pinctrl_gpio_resume(void);
39 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
40 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
41 const struct of_device_id *ws_ids;
42 struct at91_pm_data data;
45 static struct at91_soc_pm soc_pm = {
47 .standby_mode = AT91_PM_STANDBY,
48 .suspend_mode = AT91_PM_ULP0,
52 static const match_table_t pm_modes __initconst = {
53 { AT91_PM_STANDBY, "standby" },
54 { AT91_PM_ULP0, "ulp0" },
55 { AT91_PM_ULP1, "ulp1" },
56 { AT91_PM_BACKUP, "backup" },
60 #define at91_ramc_read(id, field) \
61 __raw_readl(soc_pm.data.ramc[id] + field)
63 #define at91_ramc_write(id, field, value) \
64 __raw_writel(value, soc_pm.data.ramc[id] + field)
66 static int at91_pm_valid_state(suspend_state_t state)
70 case PM_SUSPEND_STANDBY:
79 static int canary = 0xA5A5A5A5;
81 static struct at91_pm_bu {
83 unsigned long reserved;
88 struct wakeup_source_info {
89 unsigned int pmc_fsmr_bit;
90 unsigned int shdwc_mr_bit;
94 static const struct wakeup_source_info ws_info[] = {
95 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
96 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
97 { .pmc_fsmr_bit = AT91_PMC_USBAL },
98 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
99 { .pmc_fsmr_bit = AT91_PMC_RTTAL },
100 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
103 static const struct of_device_id sama5d2_ws_ids[] = {
104 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
105 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] },
106 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
107 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
108 { .compatible = "usb-ohci", .data = &ws_info[2] },
109 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
110 { .compatible = "usb-ehci", .data = &ws_info[2] },
111 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
115 static const struct of_device_id sam9x60_ws_ids[] = {
116 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
117 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
118 { .compatible = "usb-ohci", .data = &ws_info[2] },
119 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
120 { .compatible = "usb-ehci", .data = &ws_info[2] },
121 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
122 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
126 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
128 const struct wakeup_source_info *wsi;
129 const struct of_device_id *match;
130 struct platform_device *pdev;
131 struct device_node *np;
132 unsigned int mode = 0, polarity = 0, val = 0;
134 if (pm_mode != AT91_PM_ULP1)
137 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
141 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
145 if (soc_pm.config_shdwc_ws)
146 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
149 val = readl(soc_pm.data.shdwc + 0x04);
151 /* Loop through defined wakeup sources. */
152 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
153 pdev = of_find_device_by_node(np);
157 if (device_may_wakeup(&pdev->dev)) {
160 /* Check if enabled on SHDWC. */
161 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
164 mode |= wsi->pmc_fsmr_bit;
165 if (wsi->set_polarity)
166 polarity |= wsi->pmc_fsmr_bit;
170 put_device(&pdev->dev);
174 if (soc_pm.config_pmc_ws)
175 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
177 pr_err("AT91: PM: no ULP1 wakeup sources found!");
180 return mode ? 0 : -EPERM;
183 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
189 val = readl(shdwc + 0x0c);
190 *mode |= (val & 0x3ff);
191 *polarity |= ((val >> 16) & 0x3ff);
196 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
198 writel(mode, pmc + AT91_PMC_FSMR);
199 writel(polarity, pmc + AT91_PMC_FSPR);
204 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
206 writel(mode, pmc + AT91_PMC_FSMR);
212 * Called after processes are frozen, but before we shutdown devices.
214 static int at91_pm_begin(suspend_state_t state)
218 soc_pm.data.mode = soc_pm.data.suspend_mode;
221 case PM_SUSPEND_STANDBY:
222 soc_pm.data.mode = soc_pm.data.standby_mode;
226 soc_pm.data.mode = -1;
229 return at91_pm_config_ws(soc_pm.data.mode, true);
233 * Verify that all the clocks are correct before entering
236 static int at91_pm_verify_clocks(void)
241 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
243 /* USB must not be using PLLB */
244 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
245 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
249 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
250 for (i = 0; i < 4; i++) {
253 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
255 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
256 if (css != AT91_PMC_CSS_SLOW) {
257 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
266 * Call this from platform driver suspend() to see how deeply to suspend.
267 * For example, some controllers (like OHCI) need one of the PLL clocks
268 * in order to act as a wakeup source, and those are not available when
269 * going into slow clock mode.
271 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
272 * the very same problem (but not using at91 main_clk), and it'd be better
273 * to add one generic API rather than lots of platform-specific ones.
275 int at91_suspend_entering_slow_clock(void)
277 return (soc_pm.data.mode >= AT91_PM_ULP0);
279 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
281 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
282 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
283 extern u32 at91_pm_suspend_in_sram_sz;
285 static int at91_suspend_finish(unsigned long val)
290 at91_suspend_sram_fn(&soc_pm.data);
295 static void at91_pm_suspend(suspend_state_t state)
297 if (soc_pm.data.mode == AT91_PM_BACKUP) {
298 pm_bu->suspended = 1;
300 cpu_suspend(0, at91_suspend_finish);
302 /* The SRAM is lost between suspend cycles */
303 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
304 &at91_pm_suspend_in_sram,
305 at91_pm_suspend_in_sram_sz);
307 at91_suspend_finish(0);
314 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
315 * event sources; and reduces DRAM power. But otherwise it's identical to
316 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
318 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
319 * suspend more deeply, the master clock switches to the clk32k and turns off
320 * the main oscillator
322 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
324 static int at91_pm_enter(suspend_state_t state)
326 #ifdef CONFIG_PINCTRL_AT91
327 at91_pinctrl_gpio_suspend();
332 case PM_SUSPEND_STANDBY:
334 * Ensure that clocks are in a valid state.
336 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
337 !at91_pm_verify_clocks())
340 at91_pm_suspend(state);
349 pr_debug("AT91: PM - bogus suspend state %d\n", state);
354 #ifdef CONFIG_PINCTRL_AT91
355 at91_pinctrl_gpio_resume();
361 * Called right prior to thawing processes.
363 static void at91_pm_end(void)
365 at91_pm_config_ws(soc_pm.data.mode, false);
369 static const struct platform_suspend_ops at91_pm_ops = {
370 .valid = at91_pm_valid_state,
371 .begin = at91_pm_begin,
372 .enter = at91_pm_enter,
376 static struct platform_device at91_cpuidle_device = {
377 .name = "cpuidle-at91",
381 * The AT91RM9200 goes into self-refresh mode with this command, and will
382 * terminate self-refresh automatically on the next SDRAM access.
384 * Self-refresh mode is exited as soon as a memory access is made, but we don't
385 * know for sure when that happens. However, we need to restore the low-power
386 * mode if it was enabled before going idle. Restoring low-power mode while
387 * still in self-refresh is "not recommended", but seems to work.
389 static void at91rm9200_standby(void)
394 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
395 " str %2, [%1, %3]\n\t"
396 " mcr p15, 0, %0, c7, c0, 4\n\t"
398 : "r" (0), "r" (soc_pm.data.ramc[0]),
399 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
402 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
405 static void at91_ddr_standby(void)
407 /* Those two values allow us to delay self-refresh activation
410 u32 mdr, saved_mdr0, saved_mdr1 = 0;
411 u32 saved_lpr0, saved_lpr1 = 0;
413 /* LPDDR1 --> force DDR2 mode during self-refresh */
414 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
415 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
416 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
417 mdr |= AT91_DDRSDRC_MD_DDR2;
418 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
421 if (soc_pm.data.ramc[1]) {
422 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
423 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
424 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
425 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
426 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
427 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
428 mdr |= AT91_DDRSDRC_MD_DDR2;
429 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
433 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
434 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
435 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
437 /* self-refresh mode now */
438 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
439 if (soc_pm.data.ramc[1])
440 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
444 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
445 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
446 if (soc_pm.data.ramc[1]) {
447 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
448 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
452 static void sama5d3_ddr_standby(void)
457 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
458 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
459 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
461 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
465 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
468 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
471 static void at91sam9_sdram_standby(void)
474 u32 saved_lpr0, saved_lpr1 = 0;
476 if (soc_pm.data.ramc[1]) {
477 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
478 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
479 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
482 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
483 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
484 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
486 /* self-refresh mode now */
487 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
488 if (soc_pm.data.ramc[1])
489 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
493 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
494 if (soc_pm.data.ramc[1])
495 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
500 unsigned int memctrl;
503 static const struct ramc_info ramc_infos[] __initconst = {
504 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
505 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
506 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
507 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
510 static const struct of_device_id ramc_ids[] __initconst = {
511 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
512 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
513 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
514 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
518 static __init void at91_dt_ramc(void)
520 struct device_node *np;
521 const struct of_device_id *of_id;
523 void *standby = NULL;
524 const struct ramc_info *ramc;
526 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
527 soc_pm.data.ramc[idx] = of_iomap(np, 0);
528 if (!soc_pm.data.ramc[idx])
529 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
533 standby = ramc->idle;
534 soc_pm.data.memctrl = ramc->memctrl;
540 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
543 pr_warn("ramc no standby function available\n");
547 at91_cpuidle_device.dev.platform_data = standby;
550 static void at91rm9200_idle(void)
553 * Disable the processor clock. The processor will be automatically
554 * re-enabled by an interrupt or by a reset.
556 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
559 static void at91sam9x60_idle(void)
564 static void at91sam9_idle(void)
566 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
570 static void __init at91_pm_sram_init(void)
572 struct gen_pool *sram_pool;
573 phys_addr_t sram_pbase;
574 unsigned long sram_base;
575 struct device_node *node;
576 struct platform_device *pdev = NULL;
578 for_each_compatible_node(node, NULL, "mmio-sram") {
579 pdev = of_find_device_by_node(node);
587 pr_warn("%s: failed to find sram device!\n", __func__);
591 sram_pool = gen_pool_get(&pdev->dev, NULL);
593 pr_warn("%s: sram pool unavailable!\n", __func__);
597 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
599 pr_warn("%s: unable to alloc sram!\n", __func__);
603 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
604 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
605 at91_pm_suspend_in_sram_sz, false);
606 if (!at91_suspend_sram_fn) {
607 pr_warn("SRAM: Could not map\n");
611 /* Copy the pm suspend handler to SRAM */
612 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
613 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
616 static bool __init at91_is_pm_mode_active(int pm_mode)
618 return (soc_pm.data.standby_mode == pm_mode ||
619 soc_pm.data.suspend_mode == pm_mode);
622 static int __init at91_pm_backup_init(void)
624 struct gen_pool *sram_pool;
625 struct device_node *np;
626 struct platform_device *pdev = NULL;
629 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
632 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
635 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
637 pr_warn("%s: failed to find sfrbu!\n", __func__);
641 soc_pm.data.sfrbu = of_iomap(np, 0);
644 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
646 goto securam_fail_no_ref_dev;
648 pdev = of_find_device_by_node(np);
651 pr_warn("%s: failed to find securam device!\n", __func__);
652 goto securam_fail_no_ref_dev;
655 sram_pool = gen_pool_get(&pdev->dev, NULL);
657 pr_warn("%s: securam pool unavailable!\n", __func__);
661 pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
663 pr_warn("%s: unable to alloc securam!\n", __func__);
668 pm_bu->suspended = 0;
669 pm_bu->canary = __pa_symbol(&canary);
670 pm_bu->resume = __pa_symbol(cpu_resume);
675 put_device(&pdev->dev);
676 securam_fail_no_ref_dev:
677 iounmap(soc_pm.data.sfrbu);
678 soc_pm.data.sfrbu = NULL;
682 static void __init at91_pm_use_default_mode(int pm_mode)
684 if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP)
687 if (soc_pm.data.standby_mode == pm_mode)
688 soc_pm.data.standby_mode = AT91_PM_ULP0;
689 if (soc_pm.data.suspend_mode == pm_mode)
690 soc_pm.data.suspend_mode = AT91_PM_ULP0;
693 static void __init at91_pm_modes_init(void)
695 struct device_node *np;
698 if (!at91_is_pm_mode_active(AT91_PM_BACKUP) &&
699 !at91_is_pm_mode_active(AT91_PM_ULP1))
702 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc");
704 pr_warn("%s: failed to find shdwc!\n", __func__);
708 soc_pm.data.shdwc = of_iomap(np, 0);
711 ret = at91_pm_backup_init();
713 if (!at91_is_pm_mode_active(AT91_PM_ULP1))
722 iounmap(soc_pm.data.shdwc);
723 soc_pm.data.shdwc = NULL;
725 at91_pm_use_default_mode(AT91_PM_ULP1);
727 at91_pm_use_default_mode(AT91_PM_BACKUP);
731 unsigned long uhp_udp_mask;
734 static const struct pmc_info pmc_infos[] __initconst = {
735 { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP },
736 { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP },
737 { .uhp_udp_mask = AT91SAM926x_PMC_UHP },
738 { .uhp_udp_mask = 0 },
741 static const struct of_device_id atmel_pmc_ids[] __initconst = {
742 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
743 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
744 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
745 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
746 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
747 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
748 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
749 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
750 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
751 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
752 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
756 static void __init at91_pm_init(void (*pm_idle)(void))
758 struct device_node *pmc_np;
759 const struct of_device_id *of_id;
760 const struct pmc_info *pmc;
762 if (at91_cpuidle_device.dev.platform_data)
763 platform_device_register(&at91_cpuidle_device);
765 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
766 soc_pm.data.pmc = of_iomap(pmc_np, 0);
767 if (!soc_pm.data.pmc) {
768 pr_err("AT91: PM not supported, PMC not found\n");
773 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
776 arm_pm_idle = pm_idle;
780 if (at91_suspend_sram_fn) {
781 suspend_set_ops(&at91_pm_ops);
782 pr_info("AT91: PM: standby: %s, suspend: %s\n",
783 pm_modes[soc_pm.data.standby_mode].pattern,
784 pm_modes[soc_pm.data.suspend_mode].pattern);
786 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
790 void __init at91rm9200_pm_init(void)
792 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
798 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
800 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
802 at91_pm_init(at91rm9200_idle);
805 void __init sam9x60_pm_init(void)
807 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
810 at91_pm_modes_init();
812 at91_pm_init(at91sam9x60_idle);
814 soc_pm.ws_ids = sam9x60_ws_ids;
815 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
818 void __init at91sam9_pm_init(void)
820 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
824 at91_pm_init(at91sam9_idle);
827 void __init sama5_pm_init(void)
829 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
836 void __init sama5d2_pm_init(void)
838 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
841 at91_pm_modes_init();
844 soc_pm.ws_ids = sama5d2_ws_ids;
845 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
846 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
849 static int __init at91_pm_modes_select(char *str)
852 substring_t args[MAX_OPT_ARGS];
853 int standby, suspend;
858 s = strsep(&str, ",");
859 standby = match_token(s, pm_modes, args);
863 suspend = match_token(str, pm_modes, args);
867 soc_pm.data.standby_mode = standby;
868 soc_pm.data.suspend_mode = suspend;
872 early_param("atmel.pm_modes", at91_pm_modes_select);