1 /* linux/arch/arm/mach-exynos4/clock.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/err.h>
16 #include <linux/syscore_ops.h>
18 #include <plat/cpu-freq.h>
19 #include <plat/clock.h>
22 #include <plat/s5p-clock.h>
23 #include <plat/clock-clksrc.h>
27 #include <mach/regs-clock.h>
28 #include <mach/sysmmu.h>
29 #include <mach/exynos4-clock.h>
33 #ifdef CONFIG_PM_SLEEP
34 static struct sleep_save exynos4_clock_save[] = {
35 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
36 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
37 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
38 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
39 SAVE_ITEM(S5P_CLKSRC_TOP0),
40 SAVE_ITEM(S5P_CLKSRC_TOP1),
41 SAVE_ITEM(S5P_CLKSRC_CAM),
42 SAVE_ITEM(S5P_CLKSRC_TV),
43 SAVE_ITEM(S5P_CLKSRC_MFC),
44 SAVE_ITEM(S5P_CLKSRC_G3D),
45 SAVE_ITEM(S5P_CLKSRC_LCD0),
46 SAVE_ITEM(S5P_CLKSRC_MAUDIO),
47 SAVE_ITEM(S5P_CLKSRC_FSYS),
48 SAVE_ITEM(S5P_CLKSRC_PERIL0),
49 SAVE_ITEM(S5P_CLKSRC_PERIL1),
50 SAVE_ITEM(S5P_CLKDIV_CAM),
51 SAVE_ITEM(S5P_CLKDIV_TV),
52 SAVE_ITEM(S5P_CLKDIV_MFC),
53 SAVE_ITEM(S5P_CLKDIV_G3D),
54 SAVE_ITEM(S5P_CLKDIV_LCD0),
55 SAVE_ITEM(S5P_CLKDIV_MAUDIO),
56 SAVE_ITEM(S5P_CLKDIV_FSYS0),
57 SAVE_ITEM(S5P_CLKDIV_FSYS1),
58 SAVE_ITEM(S5P_CLKDIV_FSYS2),
59 SAVE_ITEM(S5P_CLKDIV_FSYS3),
60 SAVE_ITEM(S5P_CLKDIV_PERIL0),
61 SAVE_ITEM(S5P_CLKDIV_PERIL1),
62 SAVE_ITEM(S5P_CLKDIV_PERIL2),
63 SAVE_ITEM(S5P_CLKDIV_PERIL3),
64 SAVE_ITEM(S5P_CLKDIV_PERIL4),
65 SAVE_ITEM(S5P_CLKDIV_PERIL5),
66 SAVE_ITEM(S5P_CLKDIV_TOP),
67 SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
68 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
69 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
70 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
71 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
72 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
73 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
74 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
75 SAVE_ITEM(S5P_CLKDIV2_RATIO),
76 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
77 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
78 SAVE_ITEM(S5P_CLKGATE_IP_TV),
79 SAVE_ITEM(S5P_CLKGATE_IP_MFC),
80 SAVE_ITEM(S5P_CLKGATE_IP_G3D),
81 SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
82 SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
83 SAVE_ITEM(S5P_CLKGATE_IP_GPS),
84 SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
85 SAVE_ITEM(S5P_CLKGATE_BLOCK),
86 SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
87 SAVE_ITEM(S5P_CLKSRC_DMC),
88 SAVE_ITEM(S5P_CLKDIV_DMC0),
89 SAVE_ITEM(S5P_CLKDIV_DMC1),
90 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
91 SAVE_ITEM(S5P_CLKSRC_CPU),
92 SAVE_ITEM(S5P_CLKDIV_CPU),
93 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
94 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
95 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
99 struct clk clk_sclk_hdmi27m = {
100 .name = "sclk_hdmi27m",
104 struct clk clk_sclk_hdmiphy = {
105 .name = "sclk_hdmiphy",
108 struct clk clk_sclk_usbphy0 = {
109 .name = "sclk_usbphy0",
113 struct clk clk_sclk_usbphy1 = {
114 .name = "sclk_usbphy1",
117 static struct clk dummy_apb_pclk = {
122 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
124 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
127 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
129 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
132 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
134 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
137 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
139 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
142 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
144 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
147 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
149 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
152 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
154 return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
157 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
159 return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
162 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
164 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
167 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
169 return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
172 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
174 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
177 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
179 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
182 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
184 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
187 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
189 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
192 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
194 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
197 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
199 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
202 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
204 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
207 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
209 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
212 /* Core list of CMU_CPU side */
214 static struct clksrc_clk clk_mout_apll = {
218 .sources = &clk_src_apll,
219 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
222 struct clksrc_clk clk_sclk_apll = {
225 .parent = &clk_mout_apll.clk,
227 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
230 struct clksrc_clk clk_mout_epll = {
234 .sources = &clk_src_epll,
235 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
238 struct clksrc_clk clk_mout_mpll = {
242 .sources = &clk_src_mpll,
244 /* reg_src will be added in each SoCs' clock */
247 static struct clk *clkset_moutcore_list[] = {
248 [0] = &clk_mout_apll.clk,
249 [1] = &clk_mout_mpll.clk,
252 static struct clksrc_sources clkset_moutcore = {
253 .sources = clkset_moutcore_list,
254 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
257 static struct clksrc_clk clk_moutcore = {
261 .sources = &clkset_moutcore,
262 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
265 static struct clksrc_clk clk_coreclk = {
268 .parent = &clk_moutcore.clk,
270 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
273 static struct clksrc_clk clk_armclk = {
276 .parent = &clk_coreclk.clk,
280 static struct clksrc_clk clk_aclk_corem0 = {
282 .name = "aclk_corem0",
283 .parent = &clk_coreclk.clk,
285 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
288 static struct clksrc_clk clk_aclk_cores = {
290 .name = "aclk_cores",
291 .parent = &clk_coreclk.clk,
293 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
296 static struct clksrc_clk clk_aclk_corem1 = {
298 .name = "aclk_corem1",
299 .parent = &clk_coreclk.clk,
301 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
304 static struct clksrc_clk clk_periphclk = {
307 .parent = &clk_coreclk.clk,
309 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
312 /* Core list of CMU_CORE side */
314 struct clk *clkset_corebus_list[] = {
315 [0] = &clk_mout_mpll.clk,
316 [1] = &clk_sclk_apll.clk,
319 struct clksrc_sources clkset_mout_corebus = {
320 .sources = clkset_corebus_list,
321 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
324 static struct clksrc_clk clk_mout_corebus = {
326 .name = "mout_corebus",
328 .sources = &clkset_mout_corebus,
329 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
332 static struct clksrc_clk clk_sclk_dmc = {
335 .parent = &clk_mout_corebus.clk,
337 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
340 static struct clksrc_clk clk_aclk_cored = {
342 .name = "aclk_cored",
343 .parent = &clk_sclk_dmc.clk,
345 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
348 static struct clksrc_clk clk_aclk_corep = {
350 .name = "aclk_corep",
351 .parent = &clk_aclk_cored.clk,
353 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
356 static struct clksrc_clk clk_aclk_acp = {
359 .parent = &clk_mout_corebus.clk,
361 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
364 static struct clksrc_clk clk_pclk_acp = {
367 .parent = &clk_aclk_acp.clk,
369 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
372 /* Core list of CMU_TOP side */
374 struct clk *clkset_aclk_top_list[] = {
375 [0] = &clk_mout_mpll.clk,
376 [1] = &clk_sclk_apll.clk,
379 struct clksrc_sources clkset_aclk = {
380 .sources = clkset_aclk_top_list,
381 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
384 static struct clksrc_clk clk_aclk_200 = {
388 .sources = &clkset_aclk,
389 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
390 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
393 static struct clksrc_clk clk_aclk_100 = {
397 .sources = &clkset_aclk,
398 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
399 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
402 static struct clksrc_clk clk_aclk_160 = {
406 .sources = &clkset_aclk,
407 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
408 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
411 struct clksrc_clk clk_aclk_133 = {
415 .sources = &clkset_aclk,
416 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
417 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
420 static struct clk *clkset_vpllsrc_list[] = {
422 [1] = &clk_sclk_hdmi27m,
425 static struct clksrc_sources clkset_vpllsrc = {
426 .sources = clkset_vpllsrc_list,
427 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
430 static struct clksrc_clk clk_vpllsrc = {
433 .enable = exynos4_clksrc_mask_top_ctrl,
436 .sources = &clkset_vpllsrc,
437 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
440 static struct clk *clkset_sclk_vpll_list[] = {
441 [0] = &clk_vpllsrc.clk,
442 [1] = &clk_fout_vpll,
445 static struct clksrc_sources clkset_sclk_vpll = {
446 .sources = clkset_sclk_vpll_list,
447 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
450 struct clksrc_clk clk_sclk_vpll = {
454 .sources = &clkset_sclk_vpll,
455 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
458 static struct clk init_clocks_off[] = {
461 .parent = &clk_aclk_100.clk,
462 .enable = exynos4_clk_ip_peril_ctrl,
466 .devname = "s5p-mipi-csis.0",
467 .enable = exynos4_clk_ip_cam_ctrl,
471 .devname = "s5p-mipi-csis.1",
472 .enable = exynos4_clk_ip_cam_ctrl,
477 .enable = exynos4_clk_ip_cam_ctrl,
481 .devname = "exynos4-fimc.0",
482 .enable = exynos4_clk_ip_cam_ctrl,
486 .devname = "exynos4-fimc.1",
487 .enable = exynos4_clk_ip_cam_ctrl,
491 .devname = "exynos4-fimc.2",
492 .enable = exynos4_clk_ip_cam_ctrl,
496 .devname = "exynos4-fimc.3",
497 .enable = exynos4_clk_ip_cam_ctrl,
501 .devname = "exynos4-fb.0",
502 .enable = exynos4_clk_ip_lcd0_ctrl,
506 .devname = "s3c-sdhci.0",
507 .parent = &clk_aclk_133.clk,
508 .enable = exynos4_clk_ip_fsys_ctrl,
512 .devname = "s3c-sdhci.1",
513 .parent = &clk_aclk_133.clk,
514 .enable = exynos4_clk_ip_fsys_ctrl,
518 .devname = "s3c-sdhci.2",
519 .parent = &clk_aclk_133.clk,
520 .enable = exynos4_clk_ip_fsys_ctrl,
524 .devname = "s3c-sdhci.3",
525 .parent = &clk_aclk_133.clk,
526 .enable = exynos4_clk_ip_fsys_ctrl,
530 .parent = &clk_aclk_133.clk,
531 .enable = exynos4_clk_ip_fsys_ctrl,
535 .devname = "s5p-sdo",
536 .enable = exynos4_clk_ip_tv_ctrl,
540 .devname = "s5p-mixer",
541 .enable = exynos4_clk_ip_tv_ctrl,
545 .devname = "s5p-mixer",
546 .enable = exynos4_clk_ip_tv_ctrl,
550 .devname = "exynos4-hdmi",
551 .enable = exynos4_clk_ip_tv_ctrl,
555 .devname = "exynos4-hdmi",
556 .enable = exynos4_clk_hdmiphy_ctrl,
560 .devname = "s5p-sdo",
561 .enable = exynos4_clk_dac_ctrl,
565 .enable = exynos4_clk_ip_peril_ctrl,
566 .ctrlbit = (1 << 15),
569 .enable = exynos4_clk_ip_perir_ctrl,
570 .ctrlbit = (1 << 16),
573 .enable = exynos4_clk_ip_perir_ctrl,
574 .ctrlbit = (1 << 15),
577 .parent = &clk_aclk_100.clk,
578 .enable = exynos4_clk_ip_perir_ctrl,
579 .ctrlbit = (1 << 14),
582 .enable = exynos4_clk_ip_fsys_ctrl ,
583 .ctrlbit = (1 << 12),
586 .enable = exynos4_clk_ip_fsys_ctrl,
587 .ctrlbit = (1 << 13),
590 .devname = "s3c64xx-spi.0",
591 .enable = exynos4_clk_ip_peril_ctrl,
592 .ctrlbit = (1 << 16),
595 .devname = "s3c64xx-spi.1",
596 .enable = exynos4_clk_ip_peril_ctrl,
597 .ctrlbit = (1 << 17),
600 .devname = "s3c64xx-spi.2",
601 .enable = exynos4_clk_ip_peril_ctrl,
602 .ctrlbit = (1 << 18),
605 .devname = "samsung-i2s.0",
606 .enable = exynos4_clk_ip_peril_ctrl,
607 .ctrlbit = (1 << 19),
610 .devname = "samsung-i2s.1",
611 .enable = exynos4_clk_ip_peril_ctrl,
612 .ctrlbit = (1 << 20),
615 .devname = "samsung-i2s.2",
616 .enable = exynos4_clk_ip_peril_ctrl,
617 .ctrlbit = (1 << 21),
620 .devname = "samsung-ac97",
621 .enable = exynos4_clk_ip_peril_ctrl,
622 .ctrlbit = (1 << 27),
625 .enable = exynos4_clk_ip_image_ctrl,
629 .devname = "s5p-mfc",
630 .enable = exynos4_clk_ip_mfc_ctrl,
634 .devname = "s3c2440-i2c.0",
635 .parent = &clk_aclk_100.clk,
636 .enable = exynos4_clk_ip_peril_ctrl,
640 .devname = "s3c2440-i2c.1",
641 .parent = &clk_aclk_100.clk,
642 .enable = exynos4_clk_ip_peril_ctrl,
646 .devname = "s3c2440-i2c.2",
647 .parent = &clk_aclk_100.clk,
648 .enable = exynos4_clk_ip_peril_ctrl,
652 .devname = "s3c2440-i2c.3",
653 .parent = &clk_aclk_100.clk,
654 .enable = exynos4_clk_ip_peril_ctrl,
658 .devname = "s3c2440-i2c.4",
659 .parent = &clk_aclk_100.clk,
660 .enable = exynos4_clk_ip_peril_ctrl,
661 .ctrlbit = (1 << 10),
664 .devname = "s3c2440-i2c.5",
665 .parent = &clk_aclk_100.clk,
666 .enable = exynos4_clk_ip_peril_ctrl,
667 .ctrlbit = (1 << 11),
670 .devname = "s3c2440-i2c.6",
671 .parent = &clk_aclk_100.clk,
672 .enable = exynos4_clk_ip_peril_ctrl,
673 .ctrlbit = (1 << 12),
676 .devname = "s3c2440-i2c.7",
677 .parent = &clk_aclk_100.clk,
678 .enable = exynos4_clk_ip_peril_ctrl,
679 .ctrlbit = (1 << 13),
682 .devname = "s3c2440-hdmiphy-i2c",
683 .parent = &clk_aclk_100.clk,
684 .enable = exynos4_clk_ip_peril_ctrl,
685 .ctrlbit = (1 << 14),
687 .name = "SYSMMU_MDMA",
688 .enable = exynos4_clk_ip_image_ctrl,
691 .name = "SYSMMU_FIMC0",
692 .enable = exynos4_clk_ip_cam_ctrl,
695 .name = "SYSMMU_FIMC1",
696 .enable = exynos4_clk_ip_cam_ctrl,
699 .name = "SYSMMU_FIMC2",
700 .enable = exynos4_clk_ip_cam_ctrl,
703 .name = "SYSMMU_FIMC3",
704 .enable = exynos4_clk_ip_cam_ctrl,
705 .ctrlbit = (1 << 10),
707 .name = "SYSMMU_JPEG",
708 .enable = exynos4_clk_ip_cam_ctrl,
709 .ctrlbit = (1 << 11),
711 .name = "SYSMMU_FIMD0",
712 .enable = exynos4_clk_ip_lcd0_ctrl,
715 .name = "SYSMMU_FIMD1",
716 .enable = exynos4_clk_ip_lcd1_ctrl,
719 .name = "SYSMMU_PCIe",
720 .enable = exynos4_clk_ip_fsys_ctrl,
721 .ctrlbit = (1 << 18),
723 .name = "SYSMMU_G2D",
724 .enable = exynos4_clk_ip_image_ctrl,
727 .name = "SYSMMU_ROTATOR",
728 .enable = exynos4_clk_ip_image_ctrl,
732 .enable = exynos4_clk_ip_tv_ctrl,
735 .name = "SYSMMU_MFC_L",
736 .enable = exynos4_clk_ip_mfc_ctrl,
739 .name = "SYSMMU_MFC_R",
740 .enable = exynos4_clk_ip_mfc_ctrl,
745 static struct clk init_clocks[] = {
748 .devname = "s5pv210-uart.0",
749 .enable = exynos4_clk_ip_peril_ctrl,
753 .devname = "s5pv210-uart.1",
754 .enable = exynos4_clk_ip_peril_ctrl,
758 .devname = "s5pv210-uart.2",
759 .enable = exynos4_clk_ip_peril_ctrl,
763 .devname = "s5pv210-uart.3",
764 .enable = exynos4_clk_ip_peril_ctrl,
768 .devname = "s5pv210-uart.4",
769 .enable = exynos4_clk_ip_peril_ctrl,
773 .devname = "s5pv210-uart.5",
774 .enable = exynos4_clk_ip_peril_ctrl,
779 static struct clk clk_pdma0 = {
781 .devname = "dma-pl330.0",
782 .enable = exynos4_clk_ip_fsys_ctrl,
786 static struct clk clk_pdma1 = {
788 .devname = "dma-pl330.1",
789 .enable = exynos4_clk_ip_fsys_ctrl,
793 struct clk *clkset_group_list[] = {
794 [0] = &clk_ext_xtal_mux,
796 [2] = &clk_sclk_hdmi27m,
797 [3] = &clk_sclk_usbphy0,
798 [4] = &clk_sclk_usbphy1,
799 [5] = &clk_sclk_hdmiphy,
800 [6] = &clk_mout_mpll.clk,
801 [7] = &clk_mout_epll.clk,
802 [8] = &clk_sclk_vpll.clk,
805 struct clksrc_sources clkset_group = {
806 .sources = clkset_group_list,
807 .nr_sources = ARRAY_SIZE(clkset_group_list),
810 static struct clk *clkset_mout_g2d0_list[] = {
811 [0] = &clk_mout_mpll.clk,
812 [1] = &clk_sclk_apll.clk,
815 static struct clksrc_sources clkset_mout_g2d0 = {
816 .sources = clkset_mout_g2d0_list,
817 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
820 static struct clksrc_clk clk_mout_g2d0 = {
824 .sources = &clkset_mout_g2d0,
825 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
828 static struct clk *clkset_mout_g2d1_list[] = {
829 [0] = &clk_mout_epll.clk,
830 [1] = &clk_sclk_vpll.clk,
833 static struct clksrc_sources clkset_mout_g2d1 = {
834 .sources = clkset_mout_g2d1_list,
835 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
838 static struct clksrc_clk clk_mout_g2d1 = {
842 .sources = &clkset_mout_g2d1,
843 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
846 static struct clk *clkset_mout_g2d_list[] = {
847 [0] = &clk_mout_g2d0.clk,
848 [1] = &clk_mout_g2d1.clk,
851 static struct clksrc_sources clkset_mout_g2d = {
852 .sources = clkset_mout_g2d_list,
853 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
856 static struct clk *clkset_mout_mfc0_list[] = {
857 [0] = &clk_mout_mpll.clk,
858 [1] = &clk_sclk_apll.clk,
861 static struct clksrc_sources clkset_mout_mfc0 = {
862 .sources = clkset_mout_mfc0_list,
863 .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
866 static struct clksrc_clk clk_mout_mfc0 = {
870 .sources = &clkset_mout_mfc0,
871 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
874 static struct clk *clkset_mout_mfc1_list[] = {
875 [0] = &clk_mout_epll.clk,
876 [1] = &clk_sclk_vpll.clk,
879 static struct clksrc_sources clkset_mout_mfc1 = {
880 .sources = clkset_mout_mfc1_list,
881 .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
884 static struct clksrc_clk clk_mout_mfc1 = {
888 .sources = &clkset_mout_mfc1,
889 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
892 static struct clk *clkset_mout_mfc_list[] = {
893 [0] = &clk_mout_mfc0.clk,
894 [1] = &clk_mout_mfc1.clk,
897 static struct clksrc_sources clkset_mout_mfc = {
898 .sources = clkset_mout_mfc_list,
899 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
902 static struct clk *clkset_sclk_dac_list[] = {
903 [0] = &clk_sclk_vpll.clk,
904 [1] = &clk_sclk_hdmiphy,
907 static struct clksrc_sources clkset_sclk_dac = {
908 .sources = clkset_sclk_dac_list,
909 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
912 static struct clksrc_clk clk_sclk_dac = {
915 .enable = exynos4_clksrc_mask_tv_ctrl,
918 .sources = &clkset_sclk_dac,
919 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
922 static struct clksrc_clk clk_sclk_pixel = {
924 .name = "sclk_pixel",
925 .parent = &clk_sclk_vpll.clk,
927 .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
930 static struct clk *clkset_sclk_hdmi_list[] = {
931 [0] = &clk_sclk_pixel.clk,
932 [1] = &clk_sclk_hdmiphy,
935 static struct clksrc_sources clkset_sclk_hdmi = {
936 .sources = clkset_sclk_hdmi_list,
937 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
940 static struct clksrc_clk clk_sclk_hdmi = {
943 .enable = exynos4_clksrc_mask_tv_ctrl,
946 .sources = &clkset_sclk_hdmi,
947 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
950 static struct clk *clkset_sclk_mixer_list[] = {
951 [0] = &clk_sclk_dac.clk,
952 [1] = &clk_sclk_hdmi.clk,
955 static struct clksrc_sources clkset_sclk_mixer = {
956 .sources = clkset_sclk_mixer_list,
957 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
960 static struct clksrc_clk clk_sclk_mixer = {
962 .name = "sclk_mixer",
963 .enable = exynos4_clksrc_mask_tv_ctrl,
966 .sources = &clkset_sclk_mixer,
967 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
970 static struct clksrc_clk *sclk_tv[] = {
977 static struct clksrc_clk clk_dout_mmc0 = {
981 .sources = &clkset_group,
982 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
983 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
986 static struct clksrc_clk clk_dout_mmc1 = {
990 .sources = &clkset_group,
991 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
992 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
995 static struct clksrc_clk clk_dout_mmc2 = {
999 .sources = &clkset_group,
1000 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
1001 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1004 static struct clksrc_clk clk_dout_mmc3 = {
1006 .name = "dout_mmc3",
1008 .sources = &clkset_group,
1009 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
1010 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1013 static struct clksrc_clk clk_dout_mmc4 = {
1015 .name = "dout_mmc4",
1017 .sources = &clkset_group,
1018 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
1019 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1022 static struct clksrc_clk clksrcs[] = {
1026 .enable = exynos4_clksrc_mask_peril0_ctrl,
1027 .ctrlbit = (1 << 24),
1029 .sources = &clkset_group,
1030 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1031 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1034 .name = "sclk_csis",
1035 .devname = "s5p-mipi-csis.0",
1036 .enable = exynos4_clksrc_mask_cam_ctrl,
1037 .ctrlbit = (1 << 24),
1039 .sources = &clkset_group,
1040 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
1041 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
1044 .name = "sclk_csis",
1045 .devname = "s5p-mipi-csis.1",
1046 .enable = exynos4_clksrc_mask_cam_ctrl,
1047 .ctrlbit = (1 << 28),
1049 .sources = &clkset_group,
1050 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
1051 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
1054 .name = "sclk_cam0",
1055 .enable = exynos4_clksrc_mask_cam_ctrl,
1056 .ctrlbit = (1 << 16),
1058 .sources = &clkset_group,
1059 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
1060 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
1063 .name = "sclk_cam1",
1064 .enable = exynos4_clksrc_mask_cam_ctrl,
1065 .ctrlbit = (1 << 20),
1067 .sources = &clkset_group,
1068 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
1069 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
1072 .name = "sclk_fimc",
1073 .devname = "exynos4-fimc.0",
1074 .enable = exynos4_clksrc_mask_cam_ctrl,
1075 .ctrlbit = (1 << 0),
1077 .sources = &clkset_group,
1078 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
1079 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
1082 .name = "sclk_fimc",
1083 .devname = "exynos4-fimc.1",
1084 .enable = exynos4_clksrc_mask_cam_ctrl,
1085 .ctrlbit = (1 << 4),
1087 .sources = &clkset_group,
1088 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
1089 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
1092 .name = "sclk_fimc",
1093 .devname = "exynos4-fimc.2",
1094 .enable = exynos4_clksrc_mask_cam_ctrl,
1095 .ctrlbit = (1 << 8),
1097 .sources = &clkset_group,
1098 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
1099 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
1102 .name = "sclk_fimc",
1103 .devname = "exynos4-fimc.3",
1104 .enable = exynos4_clksrc_mask_cam_ctrl,
1105 .ctrlbit = (1 << 12),
1107 .sources = &clkset_group,
1108 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
1109 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
1112 .name = "sclk_fimd",
1113 .devname = "exynos4-fb.0",
1114 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1115 .ctrlbit = (1 << 0),
1117 .sources = &clkset_group,
1118 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
1119 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1122 .name = "sclk_fimg2d",
1124 .sources = &clkset_mout_g2d,
1125 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1126 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1130 .devname = "s5p-mfc",
1132 .sources = &clkset_mout_mfc,
1133 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1134 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1137 .name = "sclk_dwmmc",
1138 .parent = &clk_dout_mmc4.clk,
1139 .enable = exynos4_clksrc_mask_fsys_ctrl,
1140 .ctrlbit = (1 << 16),
1142 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1146 static struct clksrc_clk clk_sclk_uart0 = {
1149 .devname = "exynos4210-uart.0",
1150 .enable = exynos4_clksrc_mask_peril0_ctrl,
1151 .ctrlbit = (1 << 0),
1153 .sources = &clkset_group,
1154 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1155 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1158 static struct clksrc_clk clk_sclk_uart1 = {
1161 .devname = "exynos4210-uart.1",
1162 .enable = exynos4_clksrc_mask_peril0_ctrl,
1163 .ctrlbit = (1 << 4),
1165 .sources = &clkset_group,
1166 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1167 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1170 static struct clksrc_clk clk_sclk_uart2 = {
1173 .devname = "exynos4210-uart.2",
1174 .enable = exynos4_clksrc_mask_peril0_ctrl,
1175 .ctrlbit = (1 << 8),
1177 .sources = &clkset_group,
1178 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1179 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1182 static struct clksrc_clk clk_sclk_uart3 = {
1185 .devname = "exynos4210-uart.3",
1186 .enable = exynos4_clksrc_mask_peril0_ctrl,
1187 .ctrlbit = (1 << 12),
1189 .sources = &clkset_group,
1190 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1191 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1194 static struct clksrc_clk clk_sclk_mmc0 = {
1197 .devname = "s3c-sdhci.0",
1198 .parent = &clk_dout_mmc0.clk,
1199 .enable = exynos4_clksrc_mask_fsys_ctrl,
1200 .ctrlbit = (1 << 0),
1202 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1205 static struct clksrc_clk clk_sclk_mmc1 = {
1208 .devname = "s3c-sdhci.1",
1209 .parent = &clk_dout_mmc1.clk,
1210 .enable = exynos4_clksrc_mask_fsys_ctrl,
1211 .ctrlbit = (1 << 4),
1213 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1216 static struct clksrc_clk clk_sclk_mmc2 = {
1219 .devname = "s3c-sdhci.2",
1220 .parent = &clk_dout_mmc2.clk,
1221 .enable = exynos4_clksrc_mask_fsys_ctrl,
1222 .ctrlbit = (1 << 8),
1224 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1227 static struct clksrc_clk clk_sclk_mmc3 = {
1230 .devname = "s3c-sdhci.3",
1231 .parent = &clk_dout_mmc3.clk,
1232 .enable = exynos4_clksrc_mask_fsys_ctrl,
1233 .ctrlbit = (1 << 12),
1235 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1238 static struct clksrc_clk clk_sclk_spi0 = {
1241 .devname = "s3c64xx-spi.0",
1242 .enable = exynos4_clksrc_mask_peril1_ctrl,
1243 .ctrlbit = (1 << 16),
1245 .sources = &clkset_group,
1246 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1247 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1250 static struct clksrc_clk clk_sclk_spi1 = {
1253 .devname = "s3c64xx-spi.1",
1254 .enable = exynos4_clksrc_mask_peril1_ctrl,
1255 .ctrlbit = (1 << 20),
1257 .sources = &clkset_group,
1258 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1259 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1262 static struct clksrc_clk clk_sclk_spi2 = {
1265 .devname = "s3c64xx-spi.2",
1266 .enable = exynos4_clksrc_mask_peril1_ctrl,
1267 .ctrlbit = (1 << 24),
1269 .sources = &clkset_group,
1270 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1271 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1274 /* Clock initialization code */
1275 static struct clksrc_clk *sysclks[] = {
1308 static struct clk *clk_cdev[] = {
1313 static struct clksrc_clk *clksrc_cdev[] = {
1328 static struct clk_lookup exynos4_clk_lookup[] = {
1329 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
1330 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
1331 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
1332 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
1333 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1334 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1335 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1336 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1337 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1338 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1339 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
1340 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
1341 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
1344 static int xtal_rate;
1346 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1348 if (soc_is_exynos4210())
1349 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1351 else if (soc_is_exynos4212() || soc_is_exynos4412())
1352 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1357 static struct clk_ops exynos4_fout_apll_ops = {
1358 .get_rate = exynos4_fout_apll_get_rate,
1361 static u32 vpll_div[][8] = {
1362 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1363 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1366 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1371 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1373 unsigned int vpll_con0, vpll_con1 = 0;
1376 /* Return if nothing changed */
1377 if (clk->rate == rate)
1380 vpll_con0 = __raw_readl(S5P_VPLL_CON0);
1381 vpll_con0 &= ~(0x1 << 27 | \
1382 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1383 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1384 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1386 vpll_con1 = __raw_readl(S5P_VPLL_CON1);
1387 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1388 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1389 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1391 for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1392 if (vpll_div[i][0] == rate) {
1393 vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1394 vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1395 vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1396 vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1397 vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1398 vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1399 vpll_con0 |= vpll_div[i][7] << 27;
1404 if (i == ARRAY_SIZE(vpll_div)) {
1405 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1410 __raw_writel(vpll_con0, S5P_VPLL_CON0);
1411 __raw_writel(vpll_con1, S5P_VPLL_CON1);
1413 /* Wait for VPLL lock */
1414 while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1421 static struct clk_ops exynos4_vpll_ops = {
1422 .get_rate = exynos4_vpll_get_rate,
1423 .set_rate = exynos4_vpll_set_rate,
1426 void __init_or_cpufreq exynos4_setup_clocks(void)
1428 struct clk *xtal_clk;
1429 unsigned long apll = 0;
1430 unsigned long mpll = 0;
1431 unsigned long epll = 0;
1432 unsigned long vpll = 0;
1433 unsigned long vpllsrc;
1435 unsigned long armclk;
1436 unsigned long sclk_dmc;
1437 unsigned long aclk_200;
1438 unsigned long aclk_100;
1439 unsigned long aclk_160;
1440 unsigned long aclk_133;
1443 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1445 xtal_clk = clk_get(NULL, "xtal");
1446 BUG_ON(IS_ERR(xtal_clk));
1448 xtal = clk_get_rate(xtal_clk);
1454 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1456 if (soc_is_exynos4210()) {
1457 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1459 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1461 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1462 __raw_readl(S5P_EPLL_CON1), pll_4600);
1464 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1465 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1466 __raw_readl(S5P_VPLL_CON1), pll_4650c);
1467 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1468 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1469 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1470 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1471 __raw_readl(S5P_EPLL_CON1));
1473 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1474 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1475 __raw_readl(S5P_VPLL_CON1));
1480 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1481 clk_fout_mpll.rate = mpll;
1482 clk_fout_epll.rate = epll;
1483 clk_fout_vpll.ops = &exynos4_vpll_ops;
1484 clk_fout_vpll.rate = vpll;
1486 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1487 apll, mpll, epll, vpll);
1489 armclk = clk_get_rate(&clk_armclk.clk);
1490 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1492 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1493 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1494 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1495 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1497 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1498 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1499 armclk, sclk_dmc, aclk_200,
1500 aclk_100, aclk_160, aclk_133);
1502 clk_f.rate = armclk;
1503 clk_h.rate = sclk_dmc;
1504 clk_p.rate = aclk_100;
1506 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1507 s3c_set_clksrc(&clksrcs[ptr], true);
1510 static struct clk *clks[] __initdata = {
1517 #ifdef CONFIG_PM_SLEEP
1518 static int exynos4_clock_suspend(void)
1520 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1524 static void exynos4_clock_resume(void)
1526 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1530 #define exynos4_clock_suspend NULL
1531 #define exynos4_clock_resume NULL
1534 struct syscore_ops exynos4_clock_syscore_ops = {
1535 .suspend = exynos4_clock_suspend,
1536 .resume = exynos4_clock_resume,
1539 void __init exynos4_register_clocks(void)
1543 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1545 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1546 s3c_register_clksrc(sysclks[ptr], 1);
1548 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1549 s3c_register_clksrc(sclk_tv[ptr], 1);
1551 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1552 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1554 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1555 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1557 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1558 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1559 s3c_disable_clocks(clk_cdev[ptr], 1);
1561 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1562 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1563 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1565 register_syscore_ops(&exynos4_clock_syscore_ops);
1566 s3c24xx_register_clock(&dummy_apb_pclk);