2 * Copyright 2011-2014 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/delay.h>
14 #include <linux/init.h>
16 #include <linux/irq.h>
17 #include <linux/genalloc.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
21 #include <linux/of_address.h>
22 #include <linux/of_platform.h>
23 #include <linux/regmap.h>
24 #include <linux/suspend.h>
25 #include <asm/cacheflush.h>
26 #include <asm/fncpy.h>
27 #include <asm/proc-fns.h>
28 #include <asm/suspend.h>
35 #define BM_CCR_WB_COUNT (0x7 << 16)
36 #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
37 #define BM_CCR_RBC_EN (0x1 << 27)
40 #define BP_CLPCR_LPM 0
41 #define BM_CLPCR_LPM (0x3 << 0)
42 #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
43 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
44 #define BM_CLPCR_SBYOS (0x1 << 6)
45 #define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
46 #define BM_CLPCR_VSTBY (0x1 << 8)
47 #define BP_CLPCR_STBY_COUNT 9
48 #define BM_CLPCR_STBY_COUNT (0x3 << 9)
49 #define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
50 #define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
51 #define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
52 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
53 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
54 #define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
55 #define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
56 #define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
57 #define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
58 #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
59 #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
62 #define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17)
64 #define MX6Q_SUSPEND_OCRAM_SIZE 0x1000
65 #define MX6_MAX_MMDC_IO_NUM 33
67 static void __iomem *ccm_base;
68 static void __iomem *suspend_ocram_base;
69 static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
72 * suspend ocram space layout:
73 * ======================== high address ======================
81 * PM_INFO structure(imx6_cpu_pm_info)
82 * ======================== low address =======================
90 struct imx6_pm_socdata {
92 const char *mmdc_compat;
93 const char *src_compat;
94 const char *iomuxc_compat;
95 const char *gpc_compat;
96 const char *pl310_compat;
97 const u32 mmdc_io_num;
98 const u32 *mmdc_io_offset;
101 static const u32 imx6q_mmdc_io_offset[] __initconst = {
102 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
103 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
104 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
105 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
106 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
107 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
108 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
109 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
110 0x74c, /* GPR_ADDS */
113 static const u32 imx6dl_mmdc_io_offset[] __initconst = {
114 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
115 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
116 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
117 0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
118 0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
119 0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
120 0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
121 0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
122 0x74c, /* GPR_ADDS */
125 static const u32 imx6sl_mmdc_io_offset[] __initconst = {
126 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
127 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
128 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
129 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
130 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */
133 static const u32 imx6sll_mmdc_io_offset[] __initconst = {
134 0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */
135 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */
136 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */
137 0x2a4, 0x2a8, /* SDCKE0, SDCKE1*/
140 static const u32 imx6sx_mmdc_io_offset[] __initconst = {
141 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
142 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
143 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
144 0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
145 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
148 static const u32 imx6ul_mmdc_io_offset[] __initconst = {
149 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */
150 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */
151 0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */
152 0x494, 0x4b0, /* MODE_CTL, MODE, */
155 static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
156 .mmdc_compat = "fsl,imx6q-mmdc",
157 .src_compat = "fsl,imx6q-src",
158 .iomuxc_compat = "fsl,imx6q-iomuxc",
159 .gpc_compat = "fsl,imx6q-gpc",
160 .pl310_compat = "arm,pl310-cache",
161 .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
162 .mmdc_io_offset = imx6q_mmdc_io_offset,
165 static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
166 .mmdc_compat = "fsl,imx6q-mmdc",
167 .src_compat = "fsl,imx6q-src",
168 .iomuxc_compat = "fsl,imx6dl-iomuxc",
169 .gpc_compat = "fsl,imx6q-gpc",
170 .pl310_compat = "arm,pl310-cache",
171 .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
172 .mmdc_io_offset = imx6dl_mmdc_io_offset,
175 static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
176 .mmdc_compat = "fsl,imx6sl-mmdc",
177 .src_compat = "fsl,imx6sl-src",
178 .iomuxc_compat = "fsl,imx6sl-iomuxc",
179 .gpc_compat = "fsl,imx6sl-gpc",
180 .pl310_compat = "arm,pl310-cache",
181 .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
182 .mmdc_io_offset = imx6sl_mmdc_io_offset,
185 static const struct imx6_pm_socdata imx6sll_pm_data __initconst = {
186 .mmdc_compat = "fsl,imx6sll-mmdc",
187 .src_compat = "fsl,imx6sll-src",
188 .iomuxc_compat = "fsl,imx6sll-iomuxc",
189 .gpc_compat = "fsl,imx6sll-gpc",
190 .pl310_compat = "arm,pl310-cache",
191 .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset),
192 .mmdc_io_offset = imx6sll_mmdc_io_offset,
195 static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
196 .mmdc_compat = "fsl,imx6sx-mmdc",
197 .src_compat = "fsl,imx6sx-src",
198 .iomuxc_compat = "fsl,imx6sx-iomuxc",
199 .gpc_compat = "fsl,imx6sx-gpc",
200 .pl310_compat = "arm,pl310-cache",
201 .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
202 .mmdc_io_offset = imx6sx_mmdc_io_offset,
205 static const struct imx6_pm_socdata imx6ul_pm_data __initconst = {
206 .mmdc_compat = "fsl,imx6ul-mmdc",
207 .src_compat = "fsl,imx6ul-src",
208 .iomuxc_compat = "fsl,imx6ul-iomuxc",
209 .gpc_compat = "fsl,imx6ul-gpc",
210 .pl310_compat = NULL,
211 .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset),
212 .mmdc_io_offset = imx6ul_mmdc_io_offset,
216 * This structure is for passing necessary data for low level ocram
217 * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
218 * definition is changed, the offset definition in
219 * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
220 * otherwise, the suspend to ocram function will be broken!
222 struct imx6_cpu_pm_info {
223 phys_addr_t pbase; /* The physical address of pm_info. */
224 phys_addr_t resume_addr; /* The physical resume address for asm code */
226 u32 pm_info_size; /* Size of pm_info. */
227 struct imx6_pm_base mmdc_base;
228 struct imx6_pm_base src_base;
229 struct imx6_pm_base iomuxc_base;
230 struct imx6_pm_base ccm_base;
231 struct imx6_pm_base gpc_base;
232 struct imx6_pm_base l2_base;
233 u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
234 u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
237 void imx6_set_int_mem_clk_lpm(bool enable)
239 u32 val = readl_relaxed(ccm_base + CGPR);
241 val &= ~BM_CGPR_INT_MEM_CLK_LPM;
243 val |= BM_CGPR_INT_MEM_CLK_LPM;
244 writel_relaxed(val, ccm_base + CGPR);
247 void imx6_enable_rbc(bool enable)
252 * need to mask all interrupts in GPC before
253 * operating RBC configurations
257 /* configure RBC enable bit */
258 val = readl_relaxed(ccm_base + CCR);
259 val &= ~BM_CCR_RBC_EN;
260 val |= enable ? BM_CCR_RBC_EN : 0;
261 writel_relaxed(val, ccm_base + CCR);
263 /* configure RBC count */
264 val = readl_relaxed(ccm_base + CCR);
265 val &= ~BM_CCR_RBC_BYPASS_COUNT;
266 val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
267 writel(val, ccm_base + CCR);
270 * need to delay at least 2 cycles of CKIL(32K)
271 * due to hardware design requirement, which is
272 * ~61us, here we use 65us for safe
276 /* restore GPC interrupt mask settings */
277 imx_gpc_restore_all();
280 static void imx6q_enable_wb(bool enable)
284 /* configure well bias enable bit */
285 val = readl_relaxed(ccm_base + CLPCR);
286 val &= ~BM_CLPCR_WB_PER_AT_LPM;
287 val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
288 writel_relaxed(val, ccm_base + CLPCR);
290 /* configure well bias count */
291 val = readl_relaxed(ccm_base + CCR);
292 val &= ~BM_CCR_WB_COUNT;
293 val |= enable ? BM_CCR_WB_COUNT : 0;
294 writel_relaxed(val, ccm_base + CCR);
297 int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
299 u32 val = readl_relaxed(ccm_base + CLPCR);
301 val &= ~BM_CLPCR_LPM;
306 val |= 0x1 << BP_CLPCR_LPM;
307 val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
310 val |= 0x2 << BP_CLPCR_LPM;
311 val &= ~BM_CLPCR_VSTBY;
312 val &= ~BM_CLPCR_SBYOS;
314 val |= BM_CLPCR_BYPASS_PMIC_READY;
315 if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
316 cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz())
317 val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
319 val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
321 case WAIT_UNCLOCKED_POWER_OFF:
322 val |= 0x1 << BP_CLPCR_LPM;
323 val &= ~BM_CLPCR_VSTBY;
324 val &= ~BM_CLPCR_SBYOS;
327 val |= 0x2 << BP_CLPCR_LPM;
328 val |= 0x3 << BP_CLPCR_STBY_COUNT;
329 val |= BM_CLPCR_VSTBY;
330 val |= BM_CLPCR_SBYOS;
331 if (cpu_is_imx6sl() || cpu_is_imx6sx())
332 val |= BM_CLPCR_BYPASS_PMIC_READY;
333 if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
334 cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz())
335 val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
337 val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
344 * ERR007265: CCM: When improper low-power sequence is used,
345 * the SoC enters low power mode before the ARM core executes WFI.
347 * Software workaround:
348 * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
349 * by setting IOMUX_GPR1_GINT.
350 * 2) Software should then unmask IRQ #32 in GPC before setting CCM
352 * 3) Software should mask IRQ #32 right after CCM Low-Power mode
353 * is set (set bits 0-1 of CCM_CLPCR).
355 * Note that IRQ #32 is GIC SPI #0.
357 if (mode != WAIT_CLOCKED)
358 imx_gpc_hwirq_unmask(0);
359 writel_relaxed(val, ccm_base + CLPCR);
360 if (mode != WAIT_CLOCKED)
361 imx_gpc_hwirq_mask(0);
366 static int imx6q_suspend_finish(unsigned long val)
368 if (!imx6_suspend_in_ocram_fn) {
372 * call low level suspend function in ocram,
373 * as we need to float DDR IO.
375 local_flush_tlb_all();
376 /* check if need to flush internal L2 cache */
377 if (!((struct imx6_cpu_pm_info *)
378 suspend_ocram_base)->l2_base.vbase)
380 imx6_suspend_in_ocram_fn(suspend_ocram_base);
386 static int imx6q_pm_enter(suspend_state_t state)
389 case PM_SUSPEND_STANDBY:
390 imx6_set_lpm(STOP_POWER_ON);
391 imx6_set_int_mem_clk_lpm(true);
392 imx_gpc_pre_suspend(false);
394 imx6sl_set_wait_clk(true);
398 imx6sl_set_wait_clk(false);
399 imx_gpc_post_resume();
400 imx6_set_lpm(WAIT_CLOCKED);
403 imx6_set_lpm(STOP_POWER_OFF);
404 imx6_set_int_mem_clk_lpm(false);
405 imx6q_enable_wb(true);
407 * For suspend into ocram, asm code already take care of
408 * RBC setting, so we do NOT need to do that here.
410 if (!imx6_suspend_in_ocram_fn)
411 imx6_enable_rbc(true);
412 imx_gpc_pre_suspend(true);
413 imx_anatop_pre_suspend();
415 cpu_suspend(0, imx6q_suspend_finish);
416 if (cpu_is_imx6q() || cpu_is_imx6dl())
418 imx_anatop_post_resume();
419 imx_gpc_post_resume();
420 imx6_enable_rbc(false);
421 imx6q_enable_wb(false);
422 imx6_set_int_mem_clk_lpm(true);
423 imx6_set_lpm(WAIT_CLOCKED);
432 static int imx6q_pm_valid(suspend_state_t state)
434 return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
437 static const struct platform_suspend_ops imx6q_pm_ops = {
438 .enter = imx6q_pm_enter,
439 .valid = imx6q_pm_valid,
442 static int __init imx6_pm_get_base(struct imx6_pm_base *base,
445 struct device_node *node;
449 node = of_find_compatible_node(NULL, NULL, compat);
453 ret = of_address_to_resource(node, 0, &res);
457 base->pbase = res.start;
458 base->vbase = ioremap(res.start, resource_size(&res));
467 static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
469 phys_addr_t ocram_pbase;
470 struct device_node *node;
471 struct platform_device *pdev;
472 struct imx6_cpu_pm_info *pm_info;
473 struct gen_pool *ocram_pool;
474 unsigned long ocram_base;
476 const u32 *mmdc_offset_array;
478 suspend_set_ops(&imx6q_pm_ops);
481 pr_warn("%s: invalid argument!\n", __func__);
485 node = of_find_compatible_node(NULL, NULL, "mmio-sram");
487 pr_warn("%s: failed to find ocram node!\n", __func__);
491 pdev = of_find_device_by_node(node);
493 pr_warn("%s: failed to find ocram device!\n", __func__);
498 ocram_pool = gen_pool_get(&pdev->dev, NULL);
500 pr_warn("%s: ocram pool unavailable!\n", __func__);
505 ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
507 pr_warn("%s: unable to alloc ocram!\n", __func__);
512 ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
514 suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
515 MX6Q_SUSPEND_OCRAM_SIZE, false);
517 memset(suspend_ocram_base, 0, sizeof(*pm_info));
518 pm_info = suspend_ocram_base;
519 pm_info->pbase = ocram_pbase;
520 pm_info->resume_addr = __pa_symbol(v7_cpu_resume);
521 pm_info->pm_info_size = sizeof(*pm_info);
524 * ccm physical address is not used by asm code currently,
525 * so get ccm virtual address directly.
527 pm_info->ccm_base.vbase = ccm_base;
529 ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
531 pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
535 ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
537 pr_warn("%s: failed to get src base %d!\n", __func__, ret);
541 ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
543 pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
544 goto iomuxc_map_failed;
547 ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
549 pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
553 if (socdata->pl310_compat) {
554 ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat);
556 pr_warn("%s: failed to get pl310-cache base %d!\n",
558 goto pl310_cache_map_failed;
562 pm_info->ddr_type = imx_mmdc_get_ddr_type();
563 pm_info->mmdc_io_num = socdata->mmdc_io_num;
564 mmdc_offset_array = socdata->mmdc_io_offset;
566 for (i = 0; i < pm_info->mmdc_io_num; i++) {
567 pm_info->mmdc_io_val[i][0] =
568 mmdc_offset_array[i];
569 pm_info->mmdc_io_val[i][1] =
570 readl_relaxed(pm_info->iomuxc_base.vbase +
571 mmdc_offset_array[i]);
574 imx6_suspend_in_ocram_fn = fncpy(
575 suspend_ocram_base + sizeof(*pm_info),
577 MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
581 pl310_cache_map_failed:
582 iounmap(pm_info->gpc_base.vbase);
584 iounmap(pm_info->iomuxc_base.vbase);
586 iounmap(pm_info->src_base.vbase);
588 iounmap(pm_info->mmdc_base.vbase);
595 static void __init imx6_pm_common_init(const struct imx6_pm_socdata
603 if (IS_ENABLED(CONFIG_SUSPEND)) {
604 ret = imx6q_suspend_init(socdata);
606 pr_warn("%s: No DDR LPM support with suspend %d!\n",
611 * This is for SW workaround step #1 of ERR007265, see comments
612 * in imx6_set_lpm for details of this errata.
613 * Force IOMUXC irq pending, so that the interrupt to GPC can be
614 * used to deassert dsm_request signal when the signal gets
615 * asserted unexpectedly.
617 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
619 regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
623 static void imx6_pm_stby_poweroff(void)
625 imx6_set_lpm(STOP_POWER_OFF);
626 imx6q_suspend_finish(0);
630 pr_emerg("Unable to poweroff system\n");
633 static int imx6_pm_stby_poweroff_probe(void)
636 pr_warn("%s: pm_power_off already claimed %p %ps!\n",
637 __func__, pm_power_off, pm_power_off);
641 pm_power_off = imx6_pm_stby_poweroff;
645 void __init imx6_pm_ccm_init(const char *ccm_compat)
647 struct device_node *np;
650 np = of_find_compatible_node(NULL, NULL, ccm_compat);
651 ccm_base = of_iomap(np, 0);
655 * Initialize CCM_CLPCR_LPM into RUN mode to avoid ARM core
656 * clock being shut down unexpectedly by WAIT mode.
658 val = readl_relaxed(ccm_base + CLPCR);
659 val &= ~BM_CLPCR_LPM;
660 writel_relaxed(val, ccm_base + CLPCR);
662 if (of_property_read_bool(np, "fsl,pmic-stby-poweroff"))
663 imx6_pm_stby_poweroff_probe();
666 void __init imx6q_pm_init(void)
668 imx6_pm_common_init(&imx6q_pm_data);
671 void __init imx6dl_pm_init(void)
673 imx6_pm_common_init(&imx6dl_pm_data);
676 void __init imx6sl_pm_init(void)
680 if (cpu_is_imx6sl()) {
681 imx6_pm_common_init(&imx6sl_pm_data);
683 imx6_pm_common_init(&imx6sll_pm_data);
684 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
686 regmap_update_bits(gpr, IOMUXC_GPR5,
687 IMX6SLL_GPR5_AFCG_X_BYPASS_MASK, 0);
691 void __init imx6sx_pm_init(void)
693 imx6_pm_common_init(&imx6sx_pm_data);
696 void __init imx6ul_pm_init(void)
698 imx6_pm_common_init(&imx6ul_pm_data);