arch/arm/mach-ixp4xx/common.c

   1 /*
   2  * arch/arm/mach-ixp4xx/common.c
   3  *
   4  * Generic code shared across all IXP4XX platforms
   5  *
   6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2002 (c) Intel Corporation
   9  * Copyright 2003-2004 (c) MontaVista, Software, Inc.
  10  *
  11  * This file is licensed under  the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/init.h>
  19 #include <linux/serial.h>
  20 #include <linux/tty.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/bitops.h>
  25 #include <linux/io.h>
  26 #include <linux/export.h>
  27 #include <linux/cpu.h>
  28 #include <linux/pci.h>
  29 #include <linux/sched_clock.h>
  30 #include <linux/bitops.h>
  31 #include <linux/irqchip/irq-ixp4xx.h>
  32 #include <linux/platform_data/timer-ixp4xx.h>
  33 #include <mach/udc.h>
  34 #include <mach/hardware.h>
  35 #include <mach/io.h>
  36 #include <linux/uaccess.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/page.h>
  39 #include <asm/exception.h>
  40 #include <asm/irq.h>
  41 #include <asm/system_misc.h>
  42 #include <asm/mach/map.h>
  43 #include <asm/mach/irq.h>
  44 #include <asm/mach/time.h>
  45
  46 #include "irqs.h"
  47
  48 #define IXP4XX_TIMER_FREQ 66666000
  49
  50 /*************************************************************************
  51  * IXP4xx chipset I/O mapping
  52  *************************************************************************/
  53 static struct map_desc ixp4xx_io_desc[] __initdata = {
  54         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
  55                 .virtual        = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
  56                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
  57                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
  58                 .type           = MT_DEVICE
  59         }, {    /* Expansion Bus Config Registers */
  60                 .virtual        = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
  61                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
  62                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
  63                 .type           = MT_DEVICE
  64         }, {    /* PCI Registers */
  65                 .virtual        = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
  66                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
  67                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
  68                 .type           = MT_DEVICE
  69         },
  70 };
  71
  72 void __init ixp4xx_map_io(void)
  73 {
  74         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
  75 }
  76
  77 void __init ixp4xx_init_irq(void)
  78 {
  79         /*
  80          * ixp4xx does not implement the XScale PWRMODE register
  81          * so it must not call cpu_do_idle().
  82          */
  83         cpu_idle_poll_ctrl(true);
  84
  85         ixp4xx_irq_init(IXP4XX_INTC_BASE_PHYS,
  86                         (cpu_is_ixp46x() || cpu_is_ixp43x()));
  87 }
  88
  89 void __init ixp4xx_timer_init(void)
  90 {
  91         return ixp4xx_timer_setup(IXP4XX_TIMER_BASE_PHYS,
  92                                   IRQ_IXP4XX_TIMER1,
  93                                   IXP4XX_TIMER_FREQ);
  94 }
  95
  96 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
  97
  98 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
  99 {
 100         memcpy(&ixp4xx_udc_info, info, sizeof *info);
 101 }
 102
 103 static struct resource ixp4xx_udc_resources[] = {
 104         [0] = {
 105                 .start  = 0xc800b000,
 106                 .end    = 0xc800bfff,
 107                 .flags  = IORESOURCE_MEM,
 108         },
 109         [1] = {
 110                 .start  = IRQ_IXP4XX_USB,
 111                 .end    = IRQ_IXP4XX_USB,
 112                 .flags  = IORESOURCE_IRQ,
 113         },
 114 };
 115
 116 static struct resource ixp4xx_gpio_resource[] = {
 117         {
 118                 .start = IXP4XX_GPIO_BASE_PHYS,
 119                 .end = IXP4XX_GPIO_BASE_PHYS + 0xfff,
 120                 .flags = IORESOURCE_MEM,
 121         },
 122 };
 123
 124 static struct platform_device ixp4xx_gpio_device = {
 125         .name           = "ixp4xx-gpio",
 126         .id             = -1,
 127         .dev = {
 128                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 129         },
 130         .resource = ixp4xx_gpio_resource,
 131         .num_resources  = ARRAY_SIZE(ixp4xx_gpio_resource),
 132 };
 133
 134 /*
 135  * USB device controller. The IXP4xx uses the same controller as PXA25X,
 136  * so we just use the same device.
 137  */
 138 static struct platform_device ixp4xx_udc_device = {
 139         .name           = "pxa25x-udc",
 140         .id             = -1,
 141         .num_resources  = 2,
 142         .resource       = ixp4xx_udc_resources,
 143         .dev            = {
 144                 .platform_data = &ixp4xx_udc_info,
 145         },
 146 };
 147
 148 static struct resource ixp4xx_npe_resources[] = {
 149         {
 150                 .start = IXP4XX_NPEA_BASE_PHYS,
 151                 .end = IXP4XX_NPEA_BASE_PHYS + 0xfff,
 152                 .flags = IORESOURCE_MEM,
 153         },
 154         {
 155                 .start = IXP4XX_NPEB_BASE_PHYS,
 156                 .end = IXP4XX_NPEB_BASE_PHYS + 0xfff,
 157                 .flags = IORESOURCE_MEM,
 158         },
 159         {
 160                 .start = IXP4XX_NPEC_BASE_PHYS,
 161                 .end = IXP4XX_NPEC_BASE_PHYS + 0xfff,
 162                 .flags = IORESOURCE_MEM,
 163         },
 164
 165 };
 166
 167 static struct platform_device ixp4xx_npe_device = {
 168         .name           = "ixp4xx-npe",
 169         .id             = -1,
 170         .num_resources  = ARRAY_SIZE(ixp4xx_npe_resources),
 171         .resource       = ixp4xx_npe_resources,
 172 };
 173
 174 static struct resource ixp4xx_qmgr_resources[] = {
 175         {
 176                 .start = IXP4XX_QMGR_BASE_PHYS,
 177                 .end = IXP4XX_QMGR_BASE_PHYS + 0x3fff,
 178                 .flags = IORESOURCE_MEM,
 179         },
 180         {
 181                 .start = IRQ_IXP4XX_QM1,
 182                 .end = IRQ_IXP4XX_QM1,
 183                 .flags = IORESOURCE_IRQ,
 184         },
 185         {
 186                 .start = IRQ_IXP4XX_QM2,
 187                 .end = IRQ_IXP4XX_QM2,
 188                 .flags = IORESOURCE_IRQ,
 189         },
 190 };
 191
 192 static struct platform_device ixp4xx_qmgr_device = {
 193         .name           = "ixp4xx-qmgr",
 194         .id             = -1,
 195         .num_resources  = ARRAY_SIZE(ixp4xx_qmgr_resources),
 196         .resource       = ixp4xx_qmgr_resources,
 197 };
 198
 199 static struct platform_device *ixp4xx_devices[] __initdata = {
 200         &ixp4xx_npe_device,
 201         &ixp4xx_qmgr_device,
 202         &ixp4xx_gpio_device,
 203         &ixp4xx_udc_device,
 204 };
 205
 206 static struct resource ixp46x_i2c_resources[] = {
 207         [0] = {
 208                 .start  = 0xc8011000,
 209                 .end    = 0xc801101c,
 210                 .flags  = IORESOURCE_MEM,
 211         },
 212         [1] = {
 213                 .start  = IRQ_IXP4XX_I2C,
 214                 .end    = IRQ_IXP4XX_I2C,
 215                 .flags  = IORESOURCE_IRQ
 216         }
 217 };
 218
 219 /*
 220  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
 221  * we just use the same device name.
 222  */
 223 static struct platform_device ixp46x_i2c_controller = {
 224         .name           = "IOP3xx-I2C",
 225         .id             = 0,
 226         .num_resources  = 2,
 227         .resource       = ixp46x_i2c_resources
 228 };
 229
 230 static struct platform_device *ixp46x_devices[] __initdata = {
 231         &ixp46x_i2c_controller
 232 };
 233
 234 unsigned long ixp4xx_exp_bus_size;
 235 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
 236
 237 void __init ixp4xx_sys_init(void)
 238 {
 239         ixp4xx_exp_bus_size = SZ_16M;
 240
 241         platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
 242
 243         if (cpu_is_ixp46x()) {
 244                 int region;
 245
 246                 platform_add_devices(ixp46x_devices,
 247                                 ARRAY_SIZE(ixp46x_devices));
 248
 249                 for (region = 0; region < 7; region++) {
 250                         if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
 251                                 ixp4xx_exp_bus_size = SZ_32M;
 252                                 break;
 253                         }
 254                 }
 255         }
 256
 257         printk("IXP4xx: Using %luMiB expansion bus window size\n",
 258                         ixp4xx_exp_bus_size >> 20);
 259 }
 260
 261 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
 262 EXPORT_SYMBOL(ixp4xx_timer_freq);
 263
 264 void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
 265 {
 266         if (mode == REBOOT_SOFT) {
 267                 /* Jump into ROM at address 0 */
 268                 soft_restart(0);
 269         } else {
 270                 /* Use on-chip reset capability */
 271
 272                 /* set the "key" register to enable access to
 273                  * "timer" and "enable" registers
 274                  */
 275                 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
 276
 277                 /* write 0 to the timer register for an immediate reset */
 278                 *IXP4XX_OSWT = 0;
 279
 280                 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
 281         }
 282 }
 283
 284 #ifdef CONFIG_PCI
 285 static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
 286 {
 287         return (dma_addr + size) > SZ_64M;
 288 }
 289
 290 static int ixp4xx_platform_notify_remove(struct device *dev)
 291 {
 292         if (dev_is_pci(dev))
 293                 dmabounce_unregister_dev(dev);
 294
 295         return 0;
 296 }
 297 #endif
 298
 299 /*
 300  * Setup DMA mask to 64MB on PCI devices and 4 GB on all other things.
 301  */
 302 static int ixp4xx_platform_notify(struct device *dev)
 303 {
 304         dev->dma_mask = &dev->coherent_dma_mask;
 305
 306 #ifdef CONFIG_PCI
 307         if (dev_is_pci(dev)) {
 308                 dev->coherent_dma_mask = DMA_BIT_MASK(28); /* 64 MB */
 309                 dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
 310                 return 0;
 311         }
 312 #endif
 313
 314         dev->coherent_dma_mask = DMA_BIT_MASK(32);
 315         return 0;
 316 }
 317
 318 int dma_set_coherent_mask(struct device *dev, u64 mask)
 319 {
 320         if (dev_is_pci(dev))
 321                 mask &= DMA_BIT_MASK(28); /* 64 MB */
 322
 323         if ((mask & DMA_BIT_MASK(28)) == DMA_BIT_MASK(28)) {
 324                 dev->coherent_dma_mask = mask;
 325                 return 0;
 326         }
 327
 328         return -EIO;            /* device wanted sub-64MB mask */
 329 }
 330 EXPORT_SYMBOL(dma_set_coherent_mask);
 331
 332 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
 333 /*
 334  * In the case of using indirect PCI, we simply return the actual PCI
 335  * address and our read/write implementation use that to drive the
 336  * access registers. If something outside of PCI is ioremap'd, we
 337  * fallback to the default.
 338  */
 339
 340 static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
 341                                            unsigned int mtype, void *caller)
 342 {
 343         if (!is_pci_memory(addr))
 344                 return __arm_ioremap_caller(addr, size, mtype, caller);
 345
 346         return (void __iomem *)addr;
 347 }
 348
 349 static void ixp4xx_iounmap(volatile void __iomem *addr)
 350 {
 351         if (!is_pci_memory((__force u32)addr))
 352                 __iounmap(addr);
 353 }
 354 #endif
 355
 356 void __init ixp4xx_init_early(void)
 357 {
 358         platform_notify = ixp4xx_platform_notify;
 359 #ifdef CONFIG_PCI
 360         platform_notify_remove = ixp4xx_platform_notify_remove;
 361 #endif
 362 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
 363         arch_ioremap_caller = ixp4xx_ioremap_caller;
 364         arch_iounmap = ixp4xx_iounmap;
 365 #endif
 366 }