2 * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
4 * Register definitions for IXP4xx chipset. This file contains
5 * register location and bit definitions only. Platform specific
6 * definitions and helper function declarations are in platform.h
9 * Copyright (C) 2002 Intel Corporation.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #ifndef _ASM_ARM_IXP4XX_H_
19 #define _ASM_ARM_IXP4XX_H_
22 * IXP4xx Linux Memory Map:
24 * Phy Size Virt Description
25 * =========================================================================
27 * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM
29 * 0x48000000 0x04000000 ioremap'd PCI Memory Space
31 * 0x50000000 0x10000000 ioremap'd EXP BUS
33 * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals
35 * 0xC0000000 0x00001000 0xFEF13000 PCI CFG
37 * 0xC4000000 0x00001000 0xFEF14000 EXP CFG
39 * 0x60000000 0x00004000 0xFEF15000 QMgr
45 #define IXP4XX_QMGR_BASE_PHYS 0x60000000
48 * Peripheral space, including debug UART. Must be section-aligned so that
49 * it can be used with the low-level debug code.
51 #define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000
52 #define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000)
53 #define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000
56 * PCI Config registers
58 #define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000
59 #define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000)
60 #define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000
63 * Expansion BUS Configuration registers
65 #define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000
66 #define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000
67 #define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000
69 #define IXP4XX_EXP_CS0_OFFSET 0x00
70 #define IXP4XX_EXP_CS1_OFFSET 0x04
71 #define IXP4XX_EXP_CS2_OFFSET 0x08
72 #define IXP4XX_EXP_CS3_OFFSET 0x0C
73 #define IXP4XX_EXP_CS4_OFFSET 0x10
74 #define IXP4XX_EXP_CS5_OFFSET 0x14
75 #define IXP4XX_EXP_CS6_OFFSET 0x18
76 #define IXP4XX_EXP_CS7_OFFSET 0x1C
77 #define IXP4XX_EXP_CFG0_OFFSET 0x20
78 #define IXP4XX_EXP_CFG1_OFFSET 0x24
79 #define IXP4XX_EXP_CFG2_OFFSET 0x28
80 #define IXP4XX_EXP_CFG3_OFFSET 0x2C
83 * Expansion Bus Controller registers.
85 #define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
87 #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
88 #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
89 #define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET)
90 #define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
91 #define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
92 #define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
93 #define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)
94 #define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
96 #define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET)
97 #define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET)
98 #define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET)
99 #define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
103 * Peripheral Space Register Region Base Addresses
105 #define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
106 #define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
107 #define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
108 #define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
109 #define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
110 #define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
111 #define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
112 #define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
113 #define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
114 #define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
115 #define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
116 #define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
118 #define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
119 #define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
120 #define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
121 #define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
122 #define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
123 #define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
124 #define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
127 #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
128 #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
129 #define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
130 #define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
131 #define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
132 #define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
133 #define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
134 #define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
135 #define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
137 #define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
138 #define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
139 #define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
140 #define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
141 #define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
142 #define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
143 #define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
146 * Constants to make it easy to access Timer Control/Status registers
148 #define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */
149 #define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
150 #define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
151 #define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
152 #define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
153 #define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
154 #define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
155 #define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
156 #define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
159 * Operating System Timer Register Definitions.
162 #define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
164 #define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
165 #define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
166 #define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
167 #define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
168 #define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
169 #define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
170 #define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
171 #define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
172 #define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
175 * Timer register values and bit definitions
177 #define IXP4XX_OST_ENABLE 0x00000001
178 #define IXP4XX_OST_ONE_SHOT 0x00000002
179 /* Low order bits of reload value ignored */
180 #define IXP4XX_OST_RELOAD_MASK 0x00000003
181 #define IXP4XX_OST_DISABLED 0x00000000
182 #define IXP4XX_OSST_TIMER_1_PEND 0x00000001
183 #define IXP4XX_OSST_TIMER_2_PEND 0x00000002
184 #define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
185 #define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
186 #define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
188 #define IXP4XX_WDT_KEY 0x0000482E
190 #define IXP4XX_WDT_RESET_ENABLE 0x00000001
191 #define IXP4XX_WDT_IRQ_ENABLE 0x00000002
192 #define IXP4XX_WDT_COUNT_ENABLE 0x00000004
196 * Constants to make it easy to access PCI Control/Status registers
198 #define PCI_NP_AD_OFFSET 0x00
199 #define PCI_NP_CBE_OFFSET 0x04
200 #define PCI_NP_WDATA_OFFSET 0x08
201 #define PCI_NP_RDATA_OFFSET 0x0c
202 #define PCI_CRP_AD_CBE_OFFSET 0x10
203 #define PCI_CRP_WDATA_OFFSET 0x14
204 #define PCI_CRP_RDATA_OFFSET 0x18
205 #define PCI_CSR_OFFSET 0x1c
206 #define PCI_ISR_OFFSET 0x20
207 #define PCI_INTEN_OFFSET 0x24
208 #define PCI_DMACTRL_OFFSET 0x28
209 #define PCI_AHBMEMBASE_OFFSET 0x2c
210 #define PCI_AHBIOBASE_OFFSET 0x30
211 #define PCI_PCIMEMBASE_OFFSET 0x34
212 #define PCI_AHBDOORBELL_OFFSET 0x38
213 #define PCI_PCIDOORBELL_OFFSET 0x3C
214 #define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
215 #define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
216 #define PCI_ATPDMA0_LENADDR_OFFSET 0x48
217 #define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
218 #define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
219 #define PCI_ATPDMA1_LENADDR_OFFSET 0x54
222 * PCI Control/Status Registers
224 #define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
226 #define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
227 #define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
228 #define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
229 #define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
230 #define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
231 #define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
232 #define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
233 #define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET)
234 #define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
235 #define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
236 #define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
237 #define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
238 #define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
239 #define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
240 #define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
241 #define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
242 #define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
243 #define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
244 #define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
245 #define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
246 #define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
247 #define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
250 * PCI register values and bit definitions
253 /* CSR bit definitions */
254 #define PCI_CSR_HOST 0x00000001
255 #define PCI_CSR_ARBEN 0x00000002
256 #define PCI_CSR_ADS 0x00000004
257 #define PCI_CSR_PDS 0x00000008
258 #define PCI_CSR_ABE 0x00000010
259 #define PCI_CSR_DBT 0x00000020
260 #define PCI_CSR_ASE 0x00000100
261 #define PCI_CSR_IC 0x00008000
263 /* ISR (Interrupt status) Register bit definitions */
264 #define PCI_ISR_PSE 0x00000001
265 #define PCI_ISR_PFE 0x00000002
266 #define PCI_ISR_PPE 0x00000004
267 #define PCI_ISR_AHBE 0x00000008
268 #define PCI_ISR_APDC 0x00000010
269 #define PCI_ISR_PADC 0x00000020
270 #define PCI_ISR_ADB 0x00000040
271 #define PCI_ISR_PDB 0x00000080
273 /* INTEN (Interrupt Enable) Register bit definitions */
274 #define PCI_INTEN_PSE 0x00000001
275 #define PCI_INTEN_PFE 0x00000002
276 #define PCI_INTEN_PPE 0x00000004
277 #define PCI_INTEN_AHBE 0x00000008
278 #define PCI_INTEN_APDC 0x00000010
279 #define PCI_INTEN_PADC 0x00000020
280 #define PCI_INTEN_ADB 0x00000040
281 #define PCI_INTEN_PDB 0x00000080
284 * Shift value for byte enable on NP cmd/byte enable register
286 #define IXP4XX_PCI_NP_CBE_BESL 4
289 * PCI commands supported by NP access unit
291 #define NP_CMD_IOREAD 0x2
292 #define NP_CMD_IOWRITE 0x3
293 #define NP_CMD_CONFIGREAD 0xa
294 #define NP_CMD_CONFIGWRITE 0xb
295 #define NP_CMD_MEMREAD 0x6
296 #define NP_CMD_MEMWRITE 0x7
299 * Constants for CRP access into local config space
301 #define CRP_AD_CBE_BESL 20
302 #define CRP_AD_CBE_WRITE 0x00010000
304 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
306 /* "fuse" bits of IXP_EXP_CFG2 */
307 /* All IXP4xx CPUs */
308 #define IXP4XX_FEATURE_RCOMP (1 << 0)
309 #define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
310 #define IXP4XX_FEATURE_HASH (1 << 2)
311 #define IXP4XX_FEATURE_AES (1 << 3)
312 #define IXP4XX_FEATURE_DES (1 << 4)
313 #define IXP4XX_FEATURE_HDLC (1 << 5)
314 #define IXP4XX_FEATURE_AAL (1 << 6)
315 #define IXP4XX_FEATURE_HSS (1 << 7)
316 #define IXP4XX_FEATURE_UTOPIA (1 << 8)
317 #define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
318 #define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
319 #define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
320 #define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
321 #define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
322 #define IXP4XX_FEATURE_PCI (1 << 14)
323 #define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
324 #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
325 #define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \
326 IXP4XX_FEATURE_USB_DEVICE | \
327 IXP4XX_FEATURE_HASH | \
328 IXP4XX_FEATURE_AES | \
329 IXP4XX_FEATURE_DES | \
330 IXP4XX_FEATURE_HDLC | \
331 IXP4XX_FEATURE_AAL | \
332 IXP4XX_FEATURE_HSS | \
333 IXP4XX_FEATURE_UTOPIA | \
334 IXP4XX_FEATURE_NPEB_ETH0 | \
335 IXP4XX_FEATURE_NPEC_ETH | \
336 IXP4XX_FEATURE_RESET_NPEA | \
337 IXP4XX_FEATURE_RESET_NPEB | \
338 IXP4XX_FEATURE_RESET_NPEC | \
339 IXP4XX_FEATURE_PCI | \
340 IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \
341 IXP4XX_FEATURE_XSCALE_MAX_FREQ)
344 /* IXP43x/46x CPUs */
345 #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
346 #define IXP4XX_FEATURE_USB_HOST (1 << 18)
347 #define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
348 #define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \
349 IXP4XX_FEATURE_ECC_TIMESYNC | \
350 IXP4XX_FEATURE_USB_HOST | \
351 IXP4XX_FEATURE_NPEA_ETH)
353 /* IXP46x CPU (including IXP455) only */
354 #define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
355 #define IXP4XX_FEATURE_RSA (1 << 21)
356 #define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \
357 IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \