arch/arm/mach-mvebu/irq-armada-370-xp.c

   1 /*
   2  * Marvell Armada 370 and Armada XP SoC IRQ handling
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  * Ben Dooks <ben.dooks@codethink.co.uk>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/irq.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/irqdomain.h>
  25 #include <asm/mach/arch.h>
  26 #include <asm/exception.h>
  27 #include <asm/smp_plat.h>
  28 #include <asm/hardware/cache-l2x0.h>
  29
  30 /* Interrupt Controller Registers Map */
  31 #define ARMADA_370_XP_INT_SET_MASK_OFFS         (0x48)
  32 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS       (0x4C)
  33
  34 #define ARMADA_370_XP_INT_CONTROL               (0x00)
  35 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS       (0x30)
  36 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS     (0x34)
  37 #define ARMADA_370_XP_INT_SOURCE_CTL(irq)       (0x100 + irq*4)
  38
  39 #define ARMADA_370_XP_CPU_INTACK_OFFS           (0x44)
  40
  41 #define ARMADA_370_XP_SW_TRIG_INT_OFFS           (0x4)
  42 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS          (0xc)
  43 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS        (0x8)
  44
  45 #define ARMADA_370_XP_MAX_PER_CPU_IRQS          (28)
  46
  47 #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ        (5)
  48
  49 #define ACTIVE_DOORBELLS                        (8)
  50
  51 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
  52
  53 static void __iomem *per_cpu_int_base;
  54 static void __iomem *main_int_base;
  55 static struct irq_domain *armada_370_xp_mpic_domain;
  56
  57 /*
  58  * In SMP mode:
  59  * For shared global interrupts, mask/unmask global enable bit
  60  * For CPU interrupts, mask/unmask the calling CPU's bit
  61  */
  62 static void armada_370_xp_irq_mask(struct irq_data *d)
  63 {
  64         irq_hw_number_t hwirq = irqd_to_hwirq(d);
  65
  66         if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
  67                 writel(hwirq, main_int_base +
  68                                 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
  69         else
  70                 writel(hwirq, per_cpu_int_base +
  71                                 ARMADA_370_XP_INT_SET_MASK_OFFS);
  72 }
  73
  74 static void armada_370_xp_irq_unmask(struct irq_data *d)
  75 {
  76         irq_hw_number_t hwirq = irqd_to_hwirq(d);
  77
  78         if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
  79                 writel(hwirq, main_int_base +
  80                                 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
  81         else
  82                 writel(hwirq, per_cpu_int_base +
  83                                 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
  84 }
  85
  86 #ifdef CONFIG_SMP
  87 static int armada_xp_set_affinity(struct irq_data *d,
  88                                   const struct cpumask *mask_val, bool force)
  89 {
  90         unsigned long reg;
  91         unsigned long new_mask = 0;
  92         unsigned long online_mask = 0;
  93         unsigned long count = 0;
  94         irq_hw_number_t hwirq = irqd_to_hwirq(d);
  95         int cpu;
  96
  97         for_each_cpu(cpu, mask_val) {
  98                 new_mask |= 1 << cpu_logical_map(cpu);
  99                 count++;
 100         }
 101
 102         /*
 103          * Forbid mutlicore interrupt affinity
 104          * This is required since the MPIC HW doesn't limit
 105          * several CPUs from acknowledging the same interrupt.
 106          */
 107         if (count > 1)
 108                 return -EINVAL;
 109
 110         for_each_cpu(cpu, cpu_online_mask)
 111                 online_mask |= 1 << cpu_logical_map(cpu);
 112
 113         raw_spin_lock(&irq_controller_lock);
 114
 115         reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
 116         reg = (reg & (~online_mask)) | new_mask;
 117         writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
 118
 119         raw_spin_unlock(&irq_controller_lock);
 120
 121         return 0;
 122 }
 123 #endif
 124
 125 static struct irq_chip armada_370_xp_irq_chip = {
 126         .name           = "armada_370_xp_irq",
 127         .irq_mask       = armada_370_xp_irq_mask,
 128         .irq_mask_ack   = armada_370_xp_irq_mask,
 129         .irq_unmask     = armada_370_xp_irq_unmask,
 130 #ifdef CONFIG_SMP
 131         .irq_set_affinity = armada_xp_set_affinity,
 132 #endif
 133 };
 134
 135 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 136                                       unsigned int virq, irq_hw_number_t hw)
 137 {
 138         armada_370_xp_irq_mask(irq_get_irq_data(virq));
 139         if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
 140                 writel(hw, per_cpu_int_base +
 141                         ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 142         else
 143                 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
 144         irq_set_status_flags(virq, IRQ_LEVEL);
 145
 146         if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
 147                 irq_set_percpu_devid(virq);
 148                 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
 149                                         handle_percpu_devid_irq);
 150
 151         } else {
 152                 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
 153                                         handle_level_irq);
 154         }
 155         set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
 156
 157         return 0;
 158 }
 159
 160 #ifdef CONFIG_SMP
 161 void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq)
 162 {
 163         int cpu;
 164         unsigned long map = 0;
 165
 166         /* Convert our logical CPU mask into a physical one. */
 167         for_each_cpu(cpu, mask)
 168                 map |= 1 << cpu_logical_map(cpu);
 169
 170         /*
 171          * Ensure that stores to Normal memory are visible to the
 172          * other CPUs before issuing the IPI.
 173          */
 174         dsb();
 175
 176         /* submit softirq */
 177         writel((map << 8) | irq, main_int_base +
 178                 ARMADA_370_XP_SW_TRIG_INT_OFFS);
 179 }
 180
 181 void armada_xp_mpic_smp_cpu_init(void)
 182 {
 183         /* Clear pending IPIs */
 184         writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 185
 186         /* Enable first 8 IPIs */
 187         writel((1 << ACTIVE_DOORBELLS) - 1, per_cpu_int_base +
 188                 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 189
 190         /* Unmask IPI interrupt */
 191         writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 192 }
 193 #endif /* CONFIG_SMP */
 194
 195 static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
 196         .map = armada_370_xp_mpic_irq_map,
 197         .xlate = irq_domain_xlate_onecell,
 198 };
 199
 200 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 201                                              struct device_node *parent)
 202 {
 203         u32 control;
 204
 205         main_int_base = of_iomap(node, 0);
 206         per_cpu_int_base = of_iomap(node, 1);
 207
 208         BUG_ON(!main_int_base);
 209         BUG_ON(!per_cpu_int_base);
 210
 211         control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
 212
 213         armada_370_xp_mpic_domain =
 214                 irq_domain_add_linear(node, (control >> 2) & 0x3ff,
 215                                 &armada_370_xp_mpic_irq_ops, NULL);
 216
 217         if (!armada_370_xp_mpic_domain)
 218                 panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
 219
 220         irq_set_default_host(armada_370_xp_mpic_domain);
 221
 222 #ifdef CONFIG_SMP
 223         armada_xp_mpic_smp_cpu_init();
 224
 225         /*
 226          * Set the default affinity from all CPUs to the boot cpu.
 227          * This is required since the MPIC doesn't limit several CPUs
 228          * from acknowledging the same interrupt.
 229          */
 230         cpumask_clear(irq_default_affinity);
 231         cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
 232
 233 #endif
 234
 235         return 0;
 236 }
 237
 238 asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
 239                                                                *regs)
 240 {
 241         u32 irqstat, irqnr;
 242
 243         do {
 244                 irqstat = readl_relaxed(per_cpu_int_base +
 245                                         ARMADA_370_XP_CPU_INTACK_OFFS);
 246                 irqnr = irqstat & 0x3FF;
 247
 248                 if (irqnr > 1022)
 249                         break;
 250
 251                 if (irqnr > 0) {
 252                         irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
 253                                         irqnr);
 254                         handle_IRQ(irqnr, regs);
 255                         continue;
 256                 }
 257 #ifdef CONFIG_SMP
 258                 /* IPI Handling */
 259                 if (irqnr == 0) {
 260                         u32 ipimask, ipinr;
 261
 262                         ipimask = readl_relaxed(per_cpu_int_base +
 263                                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
 264                                 & 0xFF;
 265
 266                         writel(0x0, per_cpu_int_base +
 267                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 268
 269                         /* Handle all pending doorbells */
 270                         for (ipinr = 0; ipinr < ACTIVE_DOORBELLS; ipinr++) {
 271                                 if (ipimask & (0x1 << ipinr))
 272                                         handle_IPI(ipinr, regs);
 273                         }
 274                         continue;
 275                 }
 276 #endif
 277
 278         } while (1);
 279 }
 280
 281 static const struct of_device_id mpic_of_match[] __initconst = {
 282         {.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
 283         {},
 284 };
 285
 286 void __init armada_370_xp_init_irq(void)
 287 {
 288         of_irq_init(mpic_of_match);
 289 #ifdef CONFIG_CACHE_L2X0
 290         l2x0_of_init(0, ~0UL);
 291 #endif
 292 }