2 * linux/arch/arm/mach-omap2/io.c
4 * OMAP2 I/O mapping code
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
23 #include <linux/clk.h>
26 #include <asm/mach/map.h>
28 #include <linux/omap-dma.h>
30 #include "omap_hwmod.h"
34 #include "powerdomain.h"
35 #include "clockdomain.h"
38 #include "clock2xxx.h"
39 #include "clock3xxx.h"
51 #include "prcm_mpu44xx.h"
52 #include "prminst44xx.h"
60 * omap_clk_soc_init: points to a function that does the SoC-specific
61 * clock initializations
63 static int (*omap_clk_soc_init)(void);
66 * The machine specific code may provide the extra mapping besides the
67 * default mapping provided here.
70 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
71 static struct map_desc omap24xx_io_desc[] __initdata = {
73 .virtual = L3_24XX_VIRT,
74 .pfn = __phys_to_pfn(L3_24XX_PHYS),
75 .length = L3_24XX_SIZE,
79 .virtual = L4_24XX_VIRT,
80 .pfn = __phys_to_pfn(L4_24XX_PHYS),
81 .length = L4_24XX_SIZE,
86 #ifdef CONFIG_SOC_OMAP2420
87 static struct map_desc omap242x_io_desc[] __initdata = {
89 .virtual = DSP_MEM_2420_VIRT,
90 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
91 .length = DSP_MEM_2420_SIZE,
95 .virtual = DSP_IPI_2420_VIRT,
96 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
97 .length = DSP_IPI_2420_SIZE,
101 .virtual = DSP_MMU_2420_VIRT,
102 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
103 .length = DSP_MMU_2420_SIZE,
110 #ifdef CONFIG_SOC_OMAP2430
111 static struct map_desc omap243x_io_desc[] __initdata = {
113 .virtual = L4_WK_243X_VIRT,
114 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
115 .length = L4_WK_243X_SIZE,
119 .virtual = OMAP243X_GPMC_VIRT,
120 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
121 .length = OMAP243X_GPMC_SIZE,
125 .virtual = OMAP243X_SDRC_VIRT,
126 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
127 .length = OMAP243X_SDRC_SIZE,
131 .virtual = OMAP243X_SMS_VIRT,
132 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
133 .length = OMAP243X_SMS_SIZE,
140 #ifdef CONFIG_ARCH_OMAP3
141 static struct map_desc omap34xx_io_desc[] __initdata = {
143 .virtual = L3_34XX_VIRT,
144 .pfn = __phys_to_pfn(L3_34XX_PHYS),
145 .length = L3_34XX_SIZE,
149 .virtual = L4_34XX_VIRT,
150 .pfn = __phys_to_pfn(L4_34XX_PHYS),
151 .length = L4_34XX_SIZE,
155 .virtual = OMAP34XX_GPMC_VIRT,
156 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
157 .length = OMAP34XX_GPMC_SIZE,
161 .virtual = OMAP343X_SMS_VIRT,
162 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
163 .length = OMAP343X_SMS_SIZE,
167 .virtual = OMAP343X_SDRC_VIRT,
168 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
169 .length = OMAP343X_SDRC_SIZE,
173 .virtual = L4_PER_34XX_VIRT,
174 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
175 .length = L4_PER_34XX_SIZE,
179 .virtual = L4_EMU_34XX_VIRT,
180 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
181 .length = L4_EMU_34XX_SIZE,
187 #ifdef CONFIG_SOC_TI81XX
188 static struct map_desc omapti81xx_io_desc[] __initdata = {
190 .virtual = L4_34XX_VIRT,
191 .pfn = __phys_to_pfn(L4_34XX_PHYS),
192 .length = L4_34XX_SIZE,
198 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
199 static struct map_desc omapam33xx_io_desc[] __initdata = {
201 .virtual = L4_34XX_VIRT,
202 .pfn = __phys_to_pfn(L4_34XX_PHYS),
203 .length = L4_34XX_SIZE,
207 .virtual = L4_WK_AM33XX_VIRT,
208 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
209 .length = L4_WK_AM33XX_SIZE,
215 #ifdef CONFIG_ARCH_OMAP4
216 static struct map_desc omap44xx_io_desc[] __initdata = {
218 .virtual = L3_44XX_VIRT,
219 .pfn = __phys_to_pfn(L3_44XX_PHYS),
220 .length = L3_44XX_SIZE,
224 .virtual = L4_44XX_VIRT,
225 .pfn = __phys_to_pfn(L4_44XX_PHYS),
226 .length = L4_44XX_SIZE,
230 .virtual = L4_PER_44XX_VIRT,
231 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
232 .length = L4_PER_44XX_SIZE,
238 #ifdef CONFIG_SOC_OMAP5
239 static struct map_desc omap54xx_io_desc[] __initdata = {
241 .virtual = L3_54XX_VIRT,
242 .pfn = __phys_to_pfn(L3_54XX_PHYS),
243 .length = L3_54XX_SIZE,
247 .virtual = L4_54XX_VIRT,
248 .pfn = __phys_to_pfn(L4_54XX_PHYS),
249 .length = L4_54XX_SIZE,
253 .virtual = L4_WK_54XX_VIRT,
254 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
255 .length = L4_WK_54XX_SIZE,
259 .virtual = L4_PER_54XX_VIRT,
260 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
261 .length = L4_PER_54XX_SIZE,
267 #ifdef CONFIG_SOC_DRA7XX
268 static struct map_desc dra7xx_io_desc[] __initdata = {
270 .virtual = L4_CFG_MPU_DRA7XX_VIRT,
271 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
272 .length = L4_CFG_MPU_DRA7XX_SIZE,
276 .virtual = L3_MAIN_SN_DRA7XX_VIRT,
277 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
278 .length = L3_MAIN_SN_DRA7XX_SIZE,
282 .virtual = L4_PER1_DRA7XX_VIRT,
283 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
284 .length = L4_PER1_DRA7XX_SIZE,
288 .virtual = L4_PER2_DRA7XX_VIRT,
289 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
290 .length = L4_PER2_DRA7XX_SIZE,
294 .virtual = L4_PER3_DRA7XX_VIRT,
295 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
296 .length = L4_PER3_DRA7XX_SIZE,
300 .virtual = L4_CFG_DRA7XX_VIRT,
301 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
302 .length = L4_CFG_DRA7XX_SIZE,
306 .virtual = L4_WKUP_DRA7XX_VIRT,
307 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
308 .length = L4_WKUP_DRA7XX_SIZE,
314 #ifdef CONFIG_SOC_OMAP2420
315 void __init omap242x_map_io(void)
317 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
318 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
322 #ifdef CONFIG_SOC_OMAP2430
323 void __init omap243x_map_io(void)
325 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
326 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
330 #ifdef CONFIG_ARCH_OMAP3
331 void __init omap3_map_io(void)
333 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
337 #ifdef CONFIG_SOC_TI81XX
338 void __init ti81xx_map_io(void)
340 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
344 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
345 void __init am33xx_map_io(void)
347 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
351 #ifdef CONFIG_ARCH_OMAP4
352 void __init omap4_map_io(void)
354 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
355 omap_barriers_init();
359 #ifdef CONFIG_SOC_OMAP5
360 void __init omap5_map_io(void)
362 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
363 omap_barriers_init();
367 #ifdef CONFIG_SOC_DRA7XX
368 void __init dra7xx_map_io(void)
370 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
371 omap_barriers_init();
375 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
377 * Sets the CORE DPLL3 M2 divider to the same value that it's at
378 * currently. This has the effect of setting the SDRC SDRAM AC timing
379 * registers to the values currently defined by the kernel. Currently
380 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
381 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
382 * or passes along the return value of clk_set_rate().
384 static int __init _omap2_init_reprogram_sdrc(void)
386 struct clk *dpll3_m2_ck;
390 if (!cpu_is_omap34xx())
393 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
394 if (IS_ERR(dpll3_m2_ck))
397 rate = clk_get_rate(dpll3_m2_ck);
398 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
399 v = clk_set_rate(dpll3_m2_ck, rate);
401 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
403 clk_put(dpll3_m2_ck);
408 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
410 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
413 static void __init __maybe_unused omap_hwmod_init_postsetup(void)
417 /* Set the default postsetup state for all hwmods */
419 postsetup_state = _HWMOD_STATE_IDLE;
421 postsetup_state = _HWMOD_STATE_ENABLED;
423 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
425 omap_pm_if_early_init();
428 static void __init __maybe_unused omap_common_late_init(void)
430 omap2_common_pm_late_init();
431 omap_soc_device_init();
434 #ifdef CONFIG_SOC_OMAP2420
435 void __init omap2420_init_early(void)
437 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
438 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
439 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
440 omap2_control_base_init();
441 omap2xxx_check_revision();
442 omap2_prcm_base_init();
443 omap2xxx_voltagedomains_init();
444 omap242x_powerdomains_init();
445 omap242x_clockdomains_init();
446 omap2420_hwmod_init();
447 omap_hwmod_init_postsetup();
448 omap_clk_soc_init = omap2420_dt_clk_init;
449 rate_table = omap2420_rate_table;
452 void __init omap2420_init_late(void)
454 omap_common_late_init();
456 omap2_clk_enable_autoidle_all();
460 #ifdef CONFIG_SOC_OMAP2430
461 void __init omap2430_init_early(void)
463 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
464 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
465 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
466 omap2_control_base_init();
467 omap2xxx_check_revision();
468 omap2_prcm_base_init();
469 omap2xxx_voltagedomains_init();
470 omap243x_powerdomains_init();
471 omap243x_clockdomains_init();
472 omap2430_hwmod_init();
473 omap_hwmod_init_postsetup();
474 omap_clk_soc_init = omap2430_dt_clk_init;
475 rate_table = omap2430_rate_table;
478 void __init omap2430_init_late(void)
480 omap_common_late_init();
482 omap2_clk_enable_autoidle_all();
487 * Currently only board-omap3beagle.c should call this because of the
488 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
490 #ifdef CONFIG_ARCH_OMAP3
491 void __init omap3_init_early(void)
493 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
494 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
495 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
496 omap2_control_base_init();
497 omap3xxx_check_revision();
498 omap3xxx_check_features();
499 omap2_prcm_base_init();
500 omap3xxx_voltagedomains_init();
501 omap3xxx_powerdomains_init();
502 omap3xxx_clockdomains_init();
503 omap3xxx_hwmod_init();
504 omap_hwmod_init_postsetup();
507 void __init omap3430_init_early(void)
510 omap_clk_soc_init = omap3430_dt_clk_init;
513 void __init omap35xx_init_early(void)
516 omap_clk_soc_init = omap3430_dt_clk_init;
519 void __init omap3630_init_early(void)
522 omap_clk_soc_init = omap3630_dt_clk_init;
525 void __init am35xx_init_early(void)
528 omap_clk_soc_init = am35xx_dt_clk_init;
531 void __init omap3_init_late(void)
533 omap_common_late_init();
535 omap2_clk_enable_autoidle_all();
538 void __init omap3430_init_late(void)
540 omap_common_late_init();
542 omap2_clk_enable_autoidle_all();
545 void __init omap35xx_init_late(void)
547 omap_common_late_init();
549 omap2_clk_enable_autoidle_all();
552 void __init omap3630_init_late(void)
554 omap_common_late_init();
556 omap2_clk_enable_autoidle_all();
559 void __init am35xx_init_late(void)
561 omap_common_late_init();
563 omap2_clk_enable_autoidle_all();
566 void __init ti81xx_init_late(void)
568 omap_common_late_init();
569 omap2_clk_enable_autoidle_all();
573 #ifdef CONFIG_SOC_TI81XX
574 void __init ti814x_init_early(void)
576 omap2_set_globals_tap(TI814X_CLASS,
577 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
578 omap2_control_base_init();
579 omap3xxx_check_revision();
580 ti81xx_check_features();
581 omap2_prcm_base_init();
582 omap3xxx_voltagedomains_init();
583 omap3xxx_powerdomains_init();
584 ti814x_clockdomains_init();
586 omap_hwmod_init_postsetup();
587 omap_clk_soc_init = dm814x_dt_clk_init;
590 void __init ti816x_init_early(void)
592 omap2_set_globals_tap(TI816X_CLASS,
593 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
594 omap2_control_base_init();
595 omap3xxx_check_revision();
596 ti81xx_check_features();
597 omap2_prcm_base_init();
598 omap3xxx_voltagedomains_init();
599 omap3xxx_powerdomains_init();
600 ti816x_clockdomains_init();
602 omap_hwmod_init_postsetup();
603 omap_clk_soc_init = dm816x_dt_clk_init;
607 #ifdef CONFIG_SOC_AM33XX
608 void __init am33xx_init_early(void)
610 omap2_set_globals_tap(AM335X_CLASS,
611 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
612 omap2_control_base_init();
613 omap3xxx_check_revision();
614 am33xx_check_features();
615 omap2_prcm_base_init();
616 am33xx_powerdomains_init();
617 am33xx_clockdomains_init();
619 omap_hwmod_init_postsetup();
620 omap_clk_soc_init = am33xx_dt_clk_init;
623 void __init am33xx_init_late(void)
625 omap_common_late_init();
629 #ifdef CONFIG_SOC_AM43XX
630 void __init am43xx_init_early(void)
632 omap2_set_globals_tap(AM335X_CLASS,
633 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
634 omap2_control_base_init();
635 omap3xxx_check_revision();
636 am33xx_check_features();
637 omap2_prcm_base_init();
638 am43xx_powerdomains_init();
639 am43xx_clockdomains_init();
641 omap_hwmod_init_postsetup();
642 omap_l2_cache_init();
643 omap_clk_soc_init = am43xx_dt_clk_init;
646 void __init am43xx_init_late(void)
648 omap_common_late_init();
649 omap2_clk_enable_autoidle_all();
653 #ifdef CONFIG_ARCH_OMAP4
654 void __init omap4430_init_early(void)
656 omap2_set_globals_tap(OMAP443X_CLASS,
657 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
658 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
659 omap2_control_base_init();
660 omap4xxx_check_revision();
661 omap4xxx_check_features();
662 omap2_prcm_base_init();
663 omap4_sar_ram_init();
664 omap4_mpuss_early_init();
665 omap4_pm_init_early();
666 omap44xx_voltagedomains_init();
667 omap44xx_powerdomains_init();
668 omap44xx_clockdomains_init();
669 omap44xx_hwmod_init();
670 omap_hwmod_init_postsetup();
671 omap_l2_cache_init();
672 omap_clk_soc_init = omap4xxx_dt_clk_init;
675 void __init omap4430_init_late(void)
677 omap_common_late_init();
679 omap2_clk_enable_autoidle_all();
683 #ifdef CONFIG_SOC_OMAP5
684 void __init omap5_init_early(void)
686 omap2_set_globals_tap(OMAP54XX_CLASS,
687 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
688 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
689 omap2_control_base_init();
690 omap2_prcm_base_init();
691 omap5xxx_check_revision();
692 omap4_sar_ram_init();
693 omap4_mpuss_early_init();
694 omap4_pm_init_early();
695 omap54xx_voltagedomains_init();
696 omap54xx_powerdomains_init();
697 omap54xx_clockdomains_init();
698 omap54xx_hwmod_init();
699 omap_hwmod_init_postsetup();
700 omap_clk_soc_init = omap5xxx_dt_clk_init;
703 void __init omap5_init_late(void)
705 omap_common_late_init();
707 omap2_clk_enable_autoidle_all();
711 #ifdef CONFIG_SOC_DRA7XX
712 void __init dra7xx_init_early(void)
714 omap2_set_globals_tap(DRA7XX_CLASS,
715 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
716 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
717 omap2_control_base_init();
718 omap4_pm_init_early();
719 omap2_prcm_base_init();
720 dra7xxx_check_revision();
721 dra7xx_powerdomains_init();
722 dra7xx_clockdomains_init();
724 omap_hwmod_init_postsetup();
725 omap_clk_soc_init = dra7xx_dt_clk_init;
728 void __init dra7xx_init_late(void)
730 omap_common_late_init();
732 omap2_clk_enable_autoidle_all();
737 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
738 struct omap_sdrc_params *sdrc_cs1)
742 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
743 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
744 _omap2_init_reprogram_sdrc();
748 int __init omap_clk_init(void)
752 if (!omap_clk_soc_init)
755 ti_clk_init_features();
757 omap2_clk_setup_ll_ops();
759 ret = omap_control_init();
763 ret = omap_prcm_init();
769 ti_dt_clk_init_retry_clks();
771 ti_dt_clockdomains_setup();
773 ret = omap_clk_soc_init();