1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2012 Texas Instruments, Inc.
9 * XXX handle crossbar/shared link difference for L3?
10 * XXX these should be marked initdata for multi-OMAP kernels
13 #include <linux/platform_data/i2c-omap.h>
15 #include "omap_hwmod.h"
19 #include "omap_hwmod_common_data.h"
21 #include "cm-regbits-24xx.h"
22 #include "prm-regbits-24xx.h"
29 * OMAP2420 hardware module integration data
31 * All of the data in this section should be autogeneratable from the
32 * TI hardware database or other technical documentation. Data that
33 * is driver-specific or driver-kernel integration-specific belongs
42 static struct omap_hwmod_class iva1_hwmod_class = {
46 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
47 { .name = "iva", .rst_shift = 8 },
50 static struct omap_hwmod omap2420_iva_hwmod = {
52 .class = &iva1_hwmod_class,
53 .clkdm_name = "iva1_clkdm",
54 .rst_lines = omap2420_iva_resets,
55 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
56 .main_clk = "iva1_ifck",
60 static struct omap_hwmod_class dsp_hwmod_class = {
64 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
65 { .name = "logic", .rst_shift = 0 },
66 { .name = "mmu", .rst_shift = 1 },
69 static struct omap_hwmod omap2420_dsp_hwmod = {
71 .class = &dsp_hwmod_class,
72 .clkdm_name = "dsp_clkdm",
73 .rst_lines = omap2420_dsp_resets,
74 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
75 .main_clk = "dsp_fck",
79 static struct omap_hwmod_class_sysconfig i2c_sysc = {
83 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
84 .sysc_fields = &omap_hwmod_sysc_type1,
87 static struct omap_hwmod_class i2c_class = {
90 .reset = &omap_i2c_reset,
94 static struct omap_hwmod omap2420_i2c1_hwmod = {
96 .main_clk = "i2c1_fck",
99 .module_offs = CORE_MOD,
101 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
106 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
107 * while a transfer is active seems to cause the I2C block to
108 * timeout. Why? Good question."
110 .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
114 static struct omap_hwmod omap2420_i2c2_hwmod = {
116 .main_clk = "i2c2_fck",
119 .module_offs = CORE_MOD,
121 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
125 .flags = HWMOD_16BIT_REG,
129 static struct omap_hwmod omap2420_mailbox_hwmod = {
131 .class = &omap2xxx_mailbox_hwmod_class,
132 .main_clk = "mailboxes_ick",
135 .module_offs = CORE_MOD,
137 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
144 * multi channel buffered serial port controller
147 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
151 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
152 { .role = "pad_fck", .clk = "mcbsp_clks" },
153 { .role = "prcm_fck", .clk = "func_96m_ck" },
157 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
159 .class = &omap2420_mcbsp_hwmod_class,
160 .main_clk = "mcbsp1_fck",
163 .module_offs = CORE_MOD,
165 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
168 .opt_clks = mcbsp_opt_clks,
169 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
173 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
175 .class = &omap2420_mcbsp_hwmod_class,
176 .main_clk = "mcbsp2_fck",
179 .module_offs = CORE_MOD,
181 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
184 .opt_clks = mcbsp_opt_clks,
185 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
188 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
192 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
193 .sysc_fields = &omap_hwmod_sysc_type1,
196 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
198 .sysc = &omap2420_msdi_sysc,
199 .reset = &omap_msdi_reset,
203 static struct omap_hwmod omap2420_msdi1_hwmod = {
205 .class = &omap2420_msdi_hwmod_class,
206 .main_clk = "mmc_fck",
209 .module_offs = CORE_MOD,
211 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
214 .flags = HWMOD_16BIT_REG,
218 static struct omap_hwmod omap2420_hdq1w_hwmod = {
220 .main_clk = "hdq_fck",
223 .module_offs = CORE_MOD,
225 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
228 .class = &omap2_hdq1w_class,
235 /* L4 CORE -> I2C1 interface */
236 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
237 .master = &omap2xxx_l4_core_hwmod,
238 .slave = &omap2420_i2c1_hwmod,
240 .user = OCP_USER_MPU | OCP_USER_SDMA,
243 /* L4 CORE -> I2C2 interface */
244 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
245 .master = &omap2xxx_l4_core_hwmod,
246 .slave = &omap2420_i2c2_hwmod,
248 .user = OCP_USER_MPU | OCP_USER_SDMA,
251 /* IVA <- L3 interface */
252 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
253 .master = &omap2xxx_l3_main_hwmod,
254 .slave = &omap2420_iva_hwmod,
256 .user = OCP_USER_MPU | OCP_USER_SDMA,
259 /* DSP <- L3 interface */
260 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
261 .master = &omap2xxx_l3_main_hwmod,
262 .slave = &omap2420_dsp_hwmod,
264 .user = OCP_USER_MPU | OCP_USER_SDMA,
267 /* l4_wkup -> timer1 */
268 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
269 .master = &omap2xxx_l4_wkup_hwmod,
270 .slave = &omap2xxx_timer1_hwmod,
272 .user = OCP_USER_MPU | OCP_USER_SDMA,
275 /* l4_wkup -> wd_timer2 */
276 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
277 .master = &omap2xxx_l4_wkup_hwmod,
278 .slave = &omap2xxx_wd_timer2_hwmod,
279 .clk = "mpu_wdt_ick",
280 .user = OCP_USER_MPU | OCP_USER_SDMA,
283 /* l4_wkup -> gpio1 */
284 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
285 .master = &omap2xxx_l4_wkup_hwmod,
286 .slave = &omap2xxx_gpio1_hwmod,
288 .user = OCP_USER_MPU | OCP_USER_SDMA,
291 /* l4_wkup -> gpio2 */
292 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
293 .master = &omap2xxx_l4_wkup_hwmod,
294 .slave = &omap2xxx_gpio2_hwmod,
296 .user = OCP_USER_MPU | OCP_USER_SDMA,
299 /* l4_wkup -> gpio3 */
300 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
301 .master = &omap2xxx_l4_wkup_hwmod,
302 .slave = &omap2xxx_gpio3_hwmod,
304 .user = OCP_USER_MPU | OCP_USER_SDMA,
307 /* l4_wkup -> gpio4 */
308 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
309 .master = &omap2xxx_l4_wkup_hwmod,
310 .slave = &omap2xxx_gpio4_hwmod,
312 .user = OCP_USER_MPU | OCP_USER_SDMA,
315 /* l4_core -> mailbox */
316 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
317 .master = &omap2xxx_l4_core_hwmod,
318 .slave = &omap2420_mailbox_hwmod,
319 .user = OCP_USER_MPU | OCP_USER_SDMA,
322 /* l4_core -> mcbsp1 */
323 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
324 .master = &omap2xxx_l4_core_hwmod,
325 .slave = &omap2420_mcbsp1_hwmod,
327 .user = OCP_USER_MPU | OCP_USER_SDMA,
330 /* l4_core -> mcbsp2 */
331 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
332 .master = &omap2xxx_l4_core_hwmod,
333 .slave = &omap2420_mcbsp2_hwmod,
335 .user = OCP_USER_MPU | OCP_USER_SDMA,
338 /* l4_core -> msdi1 */
339 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
340 .master = &omap2xxx_l4_core_hwmod,
341 .slave = &omap2420_msdi1_hwmod,
343 .user = OCP_USER_MPU | OCP_USER_SDMA,
346 /* l4_core -> hdq1w interface */
347 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
348 .master = &omap2xxx_l4_core_hwmod,
349 .slave = &omap2420_hdq1w_hwmod,
351 .user = OCP_USER_MPU | OCP_USER_SDMA,
352 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
356 /* l4_wkup -> 32ksync_counter */
357 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
358 .master = &omap2xxx_l4_wkup_hwmod,
359 .slave = &omap2xxx_counter_32k_hwmod,
360 .clk = "sync_32k_ick",
361 .user = OCP_USER_MPU | OCP_USER_SDMA,
364 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
365 .master = &omap2xxx_l3_main_hwmod,
366 .slave = &omap2xxx_gpmc_hwmod,
368 .user = OCP_USER_MPU | OCP_USER_SDMA,
371 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
372 &omap2xxx_l3_main__l4_core,
373 &omap2xxx_mpu__l3_main,
375 &omap2xxx_l4_core__mcspi1,
376 &omap2xxx_l4_core__mcspi2,
377 &omap2xxx_l4_core__l4_wkup,
378 &omap2_l4_core__uart1,
379 &omap2_l4_core__uart2,
380 &omap2_l4_core__uart3,
381 &omap2420_l4_core__i2c1,
382 &omap2420_l4_core__i2c2,
385 &omap2420_l4_wkup__timer1,
386 &omap2xxx_l4_core__timer2,
387 &omap2xxx_l4_core__timer3,
388 &omap2xxx_l4_core__timer4,
389 &omap2xxx_l4_core__timer5,
390 &omap2xxx_l4_core__timer6,
391 &omap2xxx_l4_core__timer7,
392 &omap2xxx_l4_core__timer8,
393 &omap2xxx_l4_core__timer9,
394 &omap2xxx_l4_core__timer10,
395 &omap2xxx_l4_core__timer11,
396 &omap2xxx_l4_core__timer12,
397 &omap2420_l4_wkup__wd_timer2,
398 &omap2xxx_l4_core__dss,
399 &omap2xxx_l4_core__dss_dispc,
400 &omap2xxx_l4_core__dss_rfbi,
401 &omap2xxx_l4_core__dss_venc,
402 &omap2420_l4_wkup__gpio1,
403 &omap2420_l4_wkup__gpio2,
404 &omap2420_l4_wkup__gpio3,
405 &omap2420_l4_wkup__gpio4,
406 &omap2420_l4_core__mailbox,
407 &omap2420_l4_core__mcbsp1,
408 &omap2420_l4_core__mcbsp2,
409 &omap2420_l4_core__msdi1,
410 &omap2xxx_l4_core__rng,
411 &omap2xxx_l4_core__sham,
412 &omap2xxx_l4_core__aes,
413 &omap2420_l4_core__hdq1w,
414 &omap2420_l4_wkup__counter_32k,
419 int __init omap2420_hwmod_init(void)
422 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);